© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f2xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F2XX_H
-#define __SYSTEM_STM32F2XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F2xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F2xx_System_Exported_types
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F2XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Release_Notes.html b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Release_Notes.html
deleted file mode 100644
index d170438838..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Release_Notes.html
+++ /dev/null
@@ -1,223 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s
deleted file mode 100644
index d42cd591c6..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/arm/startup_stm32f205xx.s
+++ /dev/null
@@ -1,415 +0,0 @@
-;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32f205xx.s
-;* Author : MCD Application Team
-;* Description : STM32F205xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-;
-
-
-
-
-
-
-
-
|
-
© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl entry
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s
deleted file mode 100644
index 3da594e695..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f207xx.s
+++ /dev/null
@@ -1,503 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f207xx.s
- * @author MCD Application Team
- * @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl entry
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word 0 /* CRYP crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
-
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s
deleted file mode 100644
index 39bc444cc7..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f215xx.s
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f215xx.s
- * @author MCD Application Team
- * @brief STM32F215xx Devices vector table for Atollic TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl entry
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word 0 /* Reserved */
- .word CRYP_IRQHandler /* CRYP crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s
deleted file mode 100644
index ee80d5d955..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/gcc/startup_stm32f217xx.s
+++ /dev/null
@@ -1,505 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f217xx.s
- * @author MCD Application Team
- * @brief STM32F217xx Devices vector table for Atollic TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl entry
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FSMC_IRQHandler /* FSMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word CRYP_IRQHandler /* CRYP crypto */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FSMC_IRQHandler
- .thumb_set FSMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak CRYP_IRQHandler
- .thumb_set CRYP_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_flash.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_flash.icf
deleted file mode 100644
index 477f14eee3..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20020000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_sram.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_sram.icf
deleted file mode 100644
index 71b2990cea..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f205xx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_flash.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_flash.icf
deleted file mode 100644
index 477f14eee3..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20020000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_sram.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_sram.icf
deleted file mode 100644
index 71b2990cea..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f207xx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_flash.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_flash.icf
deleted file mode 100644
index 477f14eee3..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20020000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_sram.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_sram.icf
deleted file mode 100644
index 71b2990cea..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f215xx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_flash.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_flash.icf
deleted file mode 100644
index 477f14eee3..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_flash.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20020000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_sram.icf b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_sram.icf
deleted file mode 100644
index 71b2990cea..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/linker/stm32f217xx_sram.icf
+++ /dev/null
@@ -1,31 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s
deleted file mode 100644
index f60726d16b..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f205xx.s
+++ /dev/null
@@ -1,602 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32f205xx.s
-;* Author : MCD Application Team
-;* Description : STM32F20x/21x devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* © Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD HASH_RNG_IRQHandler ; Hash and RNG
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler
- B CAN1_TX_IRQHandler
-
- PUBWEAK CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler
- B CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_TIM9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler
- B TIM1_BRK_TIM9_IRQHandler
-
- PUBWEAK TIM1_UP_TIM10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler
- B TIM1_UP_TIM10_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler
- B TIM1_TRG_COM_TIM11_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FSMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler
- B FSMC_IRQHandler
-
- PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
- B SDIO_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s
deleted file mode 100644
index e72150d1da..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f207xx.s
+++ /dev/null
@@ -1,618 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32f207xx.s
-;* Author : MCD Application Team
-;* Description : STM32F20x/21x devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* © Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD 0 ; Reserved
- DCD HASH_RNG_IRQHandler ; Hash and RNG
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler
- B CAN1_TX_IRQHandler
-
- PUBWEAK CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler
- B CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_TIM9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler
- B TIM1_BRK_TIM9_IRQHandler
-
- PUBWEAK TIM1_UP_TIM10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler
- B TIM1_UP_TIM10_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler
- B TIM1_TRG_COM_TIM11_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FSMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler
- B FSMC_IRQHandler
-
- PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
- B SDIO_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK ETH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler
- B ETH_IRQHandler
-
- PUBWEAK ETH_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_WKUP_IRQHandler
- B ETH_WKUP_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK DCMI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler
- B DCMI_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
-
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s
deleted file mode 100644
index 4d9ab95d04..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f215xx.s
+++ /dev/null
@@ -1,608 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32f215xx.s
-;* Author : MCD Application Team
-;* Description : STM32F20x/21x devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* © Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD 0 ; Reserved
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and RNG
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler
- B CAN1_TX_IRQHandler
-
- PUBWEAK CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler
- B CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_TIM9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler
- B TIM1_BRK_TIM9_IRQHandler
-
- PUBWEAK TIM1_UP_TIM10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler
- B TIM1_UP_TIM10_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler
- B TIM1_TRG_COM_TIM11_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FSMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler
- B FSMC_IRQHandler
-
- PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
- B SDIO_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK CRYP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler
- B CRYP_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
-
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s
deleted file mode 100644
index dbfeb077cc..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/iar/startup_stm32f217xx.s
+++ /dev/null
@@ -1,623 +0,0 @@
-;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
-;* File Name : startup_stm32f217xx.s
-;* Author : MCD Application Team
-;* Description : STM32F20x/21x devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M3 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;* @attention
-;*
-;* © Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
- DCD CAN1_TX_IRQHandler ; CAN1 TX
- DCD CAN1_RX0_IRQHandler ; CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
- DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
- DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
- DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD FSMC_IRQHandler ; FSMC
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD ETH_IRQHandler ; Ethernet
- DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
- DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
- DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
- DCD OTG_HS_IRQHandler ; USB OTG HS
- DCD DCMI_IRQHandler ; DCMI
- DCD CRYP_IRQHandler ; CRYP crypto
- DCD HASH_RNG_IRQHandler ; Hash and RNG
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler
- B DMA1_Stream0_IRQHandler
-
- PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler
- B DMA1_Stream1_IRQHandler
-
- PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler
- B DMA1_Stream2_IRQHandler
-
- PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler
- B DMA1_Stream3_IRQHandler
-
- PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler
- B DMA1_Stream4_IRQHandler
-
- PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler
- B DMA1_Stream5_IRQHandler
-
- PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler
- B DMA1_Stream6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler
- B CAN1_TX_IRQHandler
-
- PUBWEAK CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler
- B CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_TIM9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler
- B TIM1_BRK_TIM9_IRQHandler
-
- PUBWEAK TIM1_UP_TIM10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler
- B TIM1_UP_TIM10_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler
- B TIM1_TRG_COM_TIM11_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler
- B OTG_FS_WKUP_IRQHandler
-
- PUBWEAK TIM8_BRK_TIM12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler
- B TIM8_BRK_TIM12_IRQHandler
-
- PUBWEAK TIM8_UP_TIM13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler
- B TIM8_UP_TIM13_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler
- B TIM8_TRG_COM_TIM14_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler
- B DMA1_Stream7_IRQHandler
-
- PUBWEAK FSMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler
- B FSMC_IRQHandler
-
- PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler
- B SDIO_IRQHandler
-
- PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
- B TIM5_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler
- B DMA2_Stream0_IRQHandler
-
- PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler
- B DMA2_Stream1_IRQHandler
-
- PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler
- B DMA2_Stream2_IRQHandler
-
- PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler
- B DMA2_Stream3_IRQHandler
-
- PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler
- B DMA2_Stream4_IRQHandler
-
- PUBWEAK ETH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler
- B ETH_IRQHandler
-
- PUBWEAK ETH_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_WKUP_IRQHandler
- B ETH_WKUP_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler
- B OTG_FS_IRQHandler
-
- PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler
- B DMA2_Stream5_IRQHandler
-
- PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler
- B DMA2_Stream6_IRQHandler
-
- PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler
- B DMA2_Stream7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK OTG_HS_EP1_OUT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler
- B OTG_HS_EP1_OUT_IRQHandler
-
- PUBWEAK OTG_HS_EP1_IN_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler
- B OTG_HS_EP1_IN_IRQHandler
-
- PUBWEAK OTG_HS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler
- B OTG_HS_WKUP_IRQHandler
-
- PUBWEAK OTG_HS_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler
- B OTG_HS_IRQHandler
-
- PUBWEAK DCMI_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler
- B DCMI_IRQHandler
-
- PUBWEAK CRYP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler
- B CRYP_IRQHandler
-
- PUBWEAK HASH_RNG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HASH_RNG_IRQHandler
- B HASH_RNG_IRQHandler
-
-
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
deleted file mode 100644
index 2139bbf913..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f2xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f2xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f2xx_system
- * @{
- */
-
-/** @addtogroup STM32F2xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f2xx.h"
-
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_Defines
- * @{
- */
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM mounted
- on STM322xG_EVAL board as data memory */
-/* #define DATA_IN_ExtSRAM */
-
-/* Note: Following vector table addresses must be defined in line with linker
- configuration. */
-/*!< Uncomment the following line if you need to relocate the vector table
- anywhere in Flash or Sram, else the vector table is kept at the automatic
- remap of boot address selected */
-/* #define USER_VECT_TAB_ADDRESS */
-
-#if defined(USER_VECT_TAB_ADDRESS)
-/*!< Uncomment the following line if you need to relocate your vector Table
- in Sram else user remap will be done in Flash. */
-/* #define VECT_TAB_SRAM */
-#if defined(VECT_TAB_SRAM)
-#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-#else
-#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
- This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-#endif /* VECT_TAB_SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_Variables
- * @{
- */
-
- /* This variable can be updated in Three ways :
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
- uint32_t SystemCoreClock = 16000000;
- const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
- const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F2xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemFrequency variable.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
-#ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM */
-
- /* Configure the Vector Table location -------------------------------------*/
-#if defined(USER_VECT_TAB_ADDRESS)
- SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
- * depends on the application requirements), user has to ensure that HSE_VALUE
- * is same as the real frequency of the crystal used. Otherwise, this function
- * may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f2xx.s before jump to main.
- * This function configures the external SRAM mounted on STM322xG_EVAL board
- * This SRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- __IO uint32_t tmp = 0x00;
-
-/*-- GPIOs Configuration -----------------------------------------------------*/
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB1ENR |= 0x00000078;
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
- (void)(tmp);
-
- /* Connect PDx pins to FSMC Alternate function */
- GPIOD->AFR[0] = 0x00CCC0CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAA0A8A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0FCF;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FSMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA828A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FSMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCC0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA000AAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFF000FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FSMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0x000000C0;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x00085AAA;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x000CAFFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
-/*--FSMC Configuration -------------------------------------------------------*/
- /* Enable the FSMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
- /* Configure and enable Bank1_SRAM2 */
- FSMC_Bank1->BTCR[2] = 0x00001011;
- FSMC_Bank1->BTCR[3] = 0x00000201;
- FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/SConscript b/bsp/stm32/libraries/STM32F2xx_HAL/SConscript
deleted file mode 100644
index fa65acbd9a..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/SConscript
+++ /dev/null
@@ -1,86 +0,0 @@
-import rtconfig
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_dma.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_cortex.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_crc.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pwr.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rcc_ex.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c
-STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_gpio.c
-""")
-
-if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_uart.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_usart.c']
-
-if GetDepend(['RT_USING_I2C']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2c.c']
-
-if GetDepend(['RT_USING_SPI']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_spi.c']
-
-if GetDepend(['RT_USING_USB']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pccard.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_pcd_ex.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_ll_usb.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_hcd.c']
-
-if GetDepend(['RT_USING_CAN']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_can.c']
-
-if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_tim_ex.c']
-
-if GetDepend(['BSP_USING_ETH']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_eth.c']
-
-if GetDepend(['RT_USING_ADC']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_adc_ex.c']
-
-if GetDepend(['RT_USING_RTC']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_rtc_ex.c']
-
-if GetDepend(['RT_USING_WDT']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_iwdg.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_wwdg.c']
-
-if GetDepend(['RT_USING_SDIO']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_mmc.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c']
-
-if GetDepend(['RT_USING_AUDIO']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_i2s.c']
-
-if GetDepend(['RT_USING_MTD_NOR']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nor.c']
-
-if GetDepend(['RT_USING_MTD_NAND']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_nand.c']
-
-if GetDepend(['BSP_USING_EXT_FMC_IO']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sram.c']
-
-if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash.c']
- src += ['STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_flash_ex.c']
-
-path = [cwd + '/CMSIS/Device/ST/STM32F2xx/Include',
- cwd + '/STM32F2xx_HAL_Driver/Inc']
-
-CPPDEFINES = ['USE_HAL_DRIVER']
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
deleted file mode 100644
index 6ccac10d25..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ /dev/null
@@ -1,3788 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @brief This file contains aliases definition for the STM32Cube HAL constants
- * macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
- * @}
- */
-
-/** @defgroup CRC_Aliases CRC API aliases
- * @{
- */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7)
-#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-/**
- * @}
- */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
- defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
-
-#if defined(STM32L1)
-#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
- */
-#define HRTIM_EVENTSRC_1 (0x00000000U)
-#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
- */
-#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
-#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE I2S_IT_TXP
-#define I2S_IT_RXNE I2S_IT_RXP
-
-#define I2S_FLAG_TXE I2S_FLAG_TXP
-#define I2S_FLAG_RXNE I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE SPI_FLAG_TXP
-#define SPI_FLAG_RXNE SPI_FLAG_RXP
-
-#define SPI_IT_TXE SPI_IT_TXP
-#define SPI_IT_RXNE SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
- || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
- || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
- || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
- || defined(STM32H7)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
- for compatibility with legacy code */
-/**
- * @}
- */
-
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
- * @{
- */
-#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
-/**
- *
- * @}
- */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
-#define CR_PMODE_BB CR_VOS_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
-#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
-#else
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4) || defined(STM32F2)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16 0x00000000U
-#define USART_OVERSAMPLING_8 USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
- * @}
- */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32f2xx_hal_can_legacy.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32f2xx_hal_can_legacy.h
deleted file mode 100644
index cab04cddcd..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/Legacy/stm32f2xx_hal_can_legacy.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_can_legacy.h
- * @author MCD Application Team
- * @brief Header file of CAN HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CAN_LEGACY_H
-#define __STM32F2xx_HAL_CAN_LEGACY_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
-
-}HAL_CAN_StateTypeDef;
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
-
-/**
- * @brief CAN filter configuration structure definition
- */
-typedef struct
-{
- uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
-
- uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint32_t FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t BankNumber; /*!< Select the start slave bank filter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
-
-}CAN_FilterConfTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_Identifier_Type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-}CanTxMsgTypeDef;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_Identifier_Type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
- * @brief CAN handle Structure definition
- */
-typedef struct
-{
- CAN_TypeDef *Instance; /*!< Register base address */
-
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
-
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
- HAL_LockTypeDef Lock; /*!< CAN locking object */
-
- __IO uint32_t ErrorCode; /*!< CAN Error code
- This parameter can be a value of @ref CAN_Error_Code */
-}CAN_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
- * @{
- */
-
-/** @defgroup CAN_Error_Code CAN Error Code
- * @{
- */
-#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
-#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
-#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
-#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
-#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
-/**
- * @}
- */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
- * @{
- */
-#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
- * @{
- */
-#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
-#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
-#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
-#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
- * @{
- */
-#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
-#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
-#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
- * @{
- */
-#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
-#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
-#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
-#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
-#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
-#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
-#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
-#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
-#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
-#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
-#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
-#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
-#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
-#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
-#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
- * @{
- */
-#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
-#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
-#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
-#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
-#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
-#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
-#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
- * @{
- */
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
- * @{
- */
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
- * @{
- */
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-/**
- * @}
- */
-
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
- * @{
- */
-#define CAN_ID_STD 0x00000000U /*!< Standard Id */
-#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
- * @{
- */
-#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
-#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags CAN Flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
-#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
-#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
-#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
-#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
-#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
-/**
- * @}
- */
-
-/** @defgroup CAN_Interrupts CAN Interrupts
- * @{
- */
-#define CAN_IT_TME CAN_IER_TMEIE /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 CAN_IER_FMPIE0 /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 CAN_IER_FFIE0 /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 CAN_IER_FOVIE0 /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 CAN_IER_FMPIE1 /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 CAN_IER_FFIE1 /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 CAN_IER_FOVIE1 /*!< FIFO 1 overrun interrupt */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU CAN_IER_WKUIE /*!< Wake-up interrupt */
-#define CAN_IT_SLK CAN_IER_SLKIE /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG CAN_IER_EWGIE /*!< Error warning interrupt */
-#define CAN_IT_EPV CAN_IER_EPVIE /*!< Error passive interrupt */
-#define CAN_IT_BOF CAN_IER_BOFIE /*!< Bus-off interrupt */
-#define CAN_IT_LEC CAN_IER_LECIE /*!< Last error code interrupt */
-#define CAN_IT_ERR CAN_IER_ERRIE /*!< Error Interrupt */
-/**
- * @}
- */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
- * @{
- */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
- * @{
- */
-
-/** @brief Reset CAN handle state
- * @param __HANDLE__ specifies the CAN Handle.
- * @retval None
- */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
- * @brief Enable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle
- * @param __INTERRUPT__ CAN Interrupt
- * @retval None
- */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle
- * @param __INTERRUPT__ CAN Interrupt
- * @retval None
- */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__ CAN handle
- * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
- */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
-
-/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__ CAN Handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__ CAN Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__ CAN Handle
- * @param __INTERRUPT__ specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
- * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__ CAN Handle
- * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__ CAN handle
- * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__ CAN Handle
- * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
- * @retval None
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disable the DBG Freeze for CAN.
- * @param __HANDLE__ CAN Handle
- * @param __NEWSTATE__ new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
- * @{
- */
-
-/** @addtogroup CAN_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK 0x000000FFU
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_CAN_LEGACY_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32_assert_template.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32_assert_template.h
deleted file mode 100644
index fb61382766..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32_assert_template.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_assert.h
- * @author MCD Application Team
- * @brief STM32 assert template file.
- * This file should be copied to the application folder and renamed
- * to stm32_assert.h.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
deleted file mode 100644
index 1fa049d31c..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_H
-#define __STM32F2xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_conf.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
- * @{
- */
-typedef enum
-{
- HAL_TICK_FREQ_10HZ = 100U,
- HAL_TICK_FREQ_100HZ = 10U,
- HAL_TICK_FREQ_1KHZ = 1U,
- HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
- * @{
- */
-
-/** @brief Freeze/Unfreeze Peripherals in Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-/** @brief Main Flash memory mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
-
-/** @brief System Flash memory mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
- }while(0);
-
-/** @brief Embedded SRAM mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
-
-/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
- */
-#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
- SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
- }while(0);
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
- ((FREQ) == HAL_TICK_FREQ_100HZ) || \
- ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
- * @{
- */
-/** @addtogroup HAL_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
- * @}
- */
-
- /* Exported variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
- * @{
- */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_EnableCompensationCell(void);
-void HAL_DisableCompensationCell(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h
deleted file mode 100644
index d5b96be3e8..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc.h
+++ /dev/null
@@ -1,891 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_ADC_H
-#define __STM32F2xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
- * @{
- */
-
-/**
- * @brief Structure definition of ADC and regular group initialization
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
- * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
- * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled
- * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
- * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
- * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- */
-typedef struct
-{
- uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
- all the ADCs.
- This parameter can be a value of @ref ADC_ClockPrescaler */
- uint32_t Resolution; /*!< Configures the ADC resolution.
- This parameter can be a value of @ref ADC_Resolution */
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
- This parameter can be a value of @ref ADC_Data_align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
- This parameter can be a value of @ref ADC_EOCSelection.
- Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
- Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
- or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
- Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
- If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
- FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge by default.
- This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
- uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
- If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
- This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
- or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
- Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
- Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
- This parameter can be set to ENABLE or DISABLE. */
-}ADC_InitTypeDef;
-
-
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
- * ADC can be either disabled or enabled without conversion on going on regular group.
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADC_channels */
- uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
- uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
- uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
-}ADC_ChannelConfTypeDef;
-
-/**
- * @brief ADC Configuration multi-mode structure definition
- */
-typedef struct
-{
- uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
- This parameter can be a value of @ref ADC_analog_watchdog_selection */
- uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a 12-bit value. */
- uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a 12-bit value. */
- uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
- This parameter has an effect only if watchdog mode is configured on single channel
- This parameter can be a value of @ref ADC_channels */
- FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
- is interrupt mode or in polling mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/**
- * @brief HAL ADC state machine: ADC states definition (bitfields)
- */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
-
-/**
- * @brief ADC handle Structure definition
- */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-typedef struct __ADC_HandleTypeDef
-#else
-typedef struct
-#endif
-{
- ADC_TypeDef *Instance; /*!< Register base address */
-
- ADC_InitTypeDef Init; /*!< ADC required parameters */
-
- __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
-
- HAL_LockTypeDef Lock; /*!< ADC locking object */
-
- __IO uint32_t State; /*!< ADC communication state */
-
- __IO uint32_t ErrorCode; /*!< ADC Error code */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
- void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
- void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
- void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
- void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
- void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
- void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL ADC Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
- HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
- HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
- HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
- HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
- HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */
- HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
- * @brief HAL ADC Callback pointer definition
- */
-typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_Error_Code ADC Error Code
- * @{
- */
-#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
- enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-
-/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
- * @{
- */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
-#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
-#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
-/**
- * @}
- */
-
-/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
- * @{
- */
-#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
-#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
-#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
-#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
-#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
-#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
-#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
-/**
- * @}
- */
-
-/** @defgroup ADC_Resolution ADC Resolution
- * @{
- */
-#define ADC_RESOLUTION_12B 0x00000000U
-#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
-#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
-#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
-/**
- * @}
- */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
-#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
-/**
- * @}
- */
-
-/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
- * @{
- */
-/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
-/* compatibility with other STM32 devices. */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
-#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
-#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
-#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
-/**
- * @}
- */
-
-/** @defgroup ADC_Data_align ADC Data Align
- * @{
- */
-#define ADC_DATAALIGN_RIGHT 0x00000000U
-#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
-/**
- * @}
- */
-
-/** @defgroup ADC_channels ADC Common Channels
- * @{
- */
-#define ADC_CHANNEL_0 0x00000000U
-#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
-#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
-#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
-#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
-#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
-#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
-#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
-#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
-
-#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
-#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times ADC Sampling Times
- * @{
- */
-#define ADC_SAMPLETIME_3CYCLES 0x00000000U
-#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
-#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
-#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
-#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
-#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
-#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
-/**
- * @}
- */
-
- /** @defgroup ADC_EOCSelection ADC EOC Selection
- * @{
- */
-#define ADC_EOC_SEQ_CONV 0x00000000U
-#define ADC_EOC_SINGLE_CONV 0x00000001U
-#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
-/**
- * @}
- */
-
-/** @defgroup ADC_Event_type ADC Event Type
- * @{
- */
-#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
-#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
- * @{
- */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
- * @{
- */
-#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
-#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
-#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
-#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition ADC Flags Definition
- * @{
- */
-#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
-#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
-#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
-#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
-#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
-#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
-/**
- * @}
- */
-
-/** @defgroup ADC_channels_type ADC Channels Type
- * @{
- */
-#define ADC_ALL_CHANNELS 0x00000001U
-#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
-#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/** @brief Reset ADC handle state
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- do{ \
- (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
-
-/**
- * @brief Enable the ADC peripheral.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
-
-/**
- * @brief Disable the ADC peripheral.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
-
-/**
- * @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__ specifies the ADC Handle.
- * @param __INTERRUPT__ ADC Interrupt.
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__ specifies the ADC Handle.
- * @param __INTERRUPT__ ADC interrupt.
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
-
-/** @brief Check if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the ADC Handle.
- * @param __INTERRUPT__ specifies the ADC interrupt source to check.
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clear the ADC's pending flags.
- * @param __HANDLE__ specifies the ADC Handle.
- * @param __FLAG__ ADC flag.
- * @retval None
- */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/**
- * @brief Get the selected ADC's flag status.
- * @param __HANDLE__ specifies the ADC Handle.
- * @param __FLAG__ ADC flag.
- * @retval None
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
- * @}
- */
-
-/* Include ADC HAL Extension module */
-#include "stm32f2xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
- * @}
- */
-
-/** @addtogroup ADC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-/* Delay for ADC stabilization time. */
-/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
-/* Unit: us */
-#define ADC_STAB_DELAY_US 3U
-/* Delay for temperature sensor stabilization time. */
-/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
-/* Unit: us */
-#define ADC_TEMPSENSOR_DELAY_US 10U
-/**
- * @}
- */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in
- code of final user */
-
-/**
- * @brief Verification of ADC state: enabled or disabled
- * @param __HANDLE__ ADC handle
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_IS_ENABLE(__HANDLE__) \
- ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
- ) ? SET : RESET)
-
-/**
- * @brief Test if conversion trigger of regular group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__ ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
-
-/**
- * @brief Simultaneously clears and sets specific bits of the handle State
- * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
- * the first parameter is the ADC handle State, the second parameter is the
- * bit field to clear, the third and last parameter is the bit field to set.
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Clear ADC error code (set it to error code: "no error")
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
- ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
- ((RESOLUTION) == ADC_RESOLUTION_10B) || \
- ((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B))
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
- ((REGTRIG) == ADC_SOFTWARE_START))
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT))
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
- ((TIME) == ADC_SAMPLETIME_480CYCLES))
-#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
- ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
- ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
- ((EVENT) == ADC_OVR_EVENT))
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
-#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
- ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
- ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
-
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
- (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
-
-/**
- * @brief Set ADC Regular channel sequence length.
- * @param _NbrOfConversion_ Regular channel sequence length.
- * @retval None
- */
-#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U)
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 10 and 18.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 0 and 9.
- * @param _SAMPLETIME_ Sample time parameter.
- * @param _CHANNELNB_ Channel number.
- * @retval None
- */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
-
-/**
- * @brief Set the selected regular channel rank for rank between 1 and 6.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 7 and 12.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 13 and 16.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @retval None
- */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param _CONTINUOUS_MODE_ Continuous mode.
- * @retval None
- */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
-
-/**
- * @brief Configures the number of discontinuous conversions for the regular group channels.
- * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
-
-/**
- * @brief Enable ADC scan mode.
- * @param _SCANCONV_MODE_ Scan conversion mode.
- * @retval None
- */
-#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
-
-/**
- * @brief Enable the ADC end of conversion selection.
- * @param _EOCSelection_MODE_ End of conversion selection mode.
- * @retval None
- */
-#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
-
-/**
- * @brief Enable the ADC DMA continuous request.
- * @param _DMAContReq_MODE_ DMA continuous request mode.
- * @retval None
- */
-#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
-
-/**
- * @brief Return resolution bits in CR1 register.
- * @param __HANDLE__ ADC handle
- * @retval None
- */
-#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F2xx_ADC_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h
deleted file mode 100644
index 29c421f4d0..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_adc_ex.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_adc_ex.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_ADC_EX_H
-#define __STM32F2xx_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Exported Types
- * @{
- */
-
-/**
- * @brief ADC Configuration injected Channel structure definition
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
- * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
- * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
- * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled
- * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
- * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
- */
-typedef struct
-{
- uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
- uint32_t InjectedRank; /*!< Rank in the injected group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
- Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
- This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
- If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-
-/**
- * @brief ADC Configuration multi-mode structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
- This parameter can be a value of @ref ADCEx_Common_mode */
- uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
- This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
- uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
-}ADC_MultiModeTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADCEx_Common_mode ADC Common Mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT 0x00000000U
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
-#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
-#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
-#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
- * @{
- */
-#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
-#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
-/**
- * @}
- */
-
-/** @defgroup ADCEx_injected_rank ADC Injected Rank
- * @{
- */
-#define ADC_INJECTED_RANK_1 0x00000001U
-#define ADC_INJECTED_RANK_2 0x00000002U
-#define ADC_INJECTED_RANK_3 0x00000003U
-#define ADC_INJECTED_RANK_4 0x00000004U
-/**
- * @}
- */
-
-/** @defgroup ADCEx_channels ADC Specific Channels
- * @{
- */
-#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
- * @{
- */
-
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-
-/* Peripheral Control functions *************************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Macros ADC Private Macros
- * @{
- */
-#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
-
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERL) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
- ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
- ((MODE) == ADC_TRIPLEMODE_INTERL) || \
- ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
- ((MODE) == ADC_DMAACCESSMODE_1) || \
- ((MODE) == ADC_DMAACCESSMODE_2) || \
- ((MODE) == ADC_DMAACCESSMODE_3))
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
- ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)4U)))
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1U)) && ((RANK) <= ((uint32_t)4U)))
-
-/**
- * @brief Set the selected injected Channel rank.
- * @param _CHANNELNB_ Channel number.
- * @param _RANKNB_ Rank number.
- * @param _JSQR_JL_ Sequence length.
- * @retval None
- */
-#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Functions ADC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F2xx_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h
deleted file mode 100644
index 1a6f452a84..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_can.h
+++ /dev/null
@@ -1,848 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_can.h
- * @author MCD Application Team
- * @brief Header file of CAN HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_CAN_H
-#define STM32F2xx_HAL_CAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-#if defined (CAN1)
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
- * @{
- */
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
- HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
- HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
- HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
-
-} HAL_CAN_StateTypeDef;
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
- is allowed to lengthen or shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE. */
-
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter configuration structure definition
- */
-typedef struct
-{
- uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
- For single CAN instance(14 dedicated filter banks),
- this parameter must be a number between Min_Data = 0 and Max_Data = 13.
- For dual CAN instances(28 filter banks shared),
- this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-
- uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint32_t FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be a value of @ref CAN_filter_activation */
-
- uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
- For single CAN instances, this parameter is meaningless.
- For dual CAN instances, all filter banks with lower index are assigned to master
- CAN instance, whereas all filter banks with greater index are assigned to slave
- CAN instance.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-
-} CAN_FilterTypeDef;
-
-/**
- * @brief CAN Tx message header structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
- FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
- of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
- @note: Time Triggered Communication Mode must be enabled.
- @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
- This parameter can be set to ENABLE or DISABLE. */
-
-} CAN_TxHeaderTypeDef;
-
-/**
- * @brief CAN Rx message header structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
- uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
- @note: Time Triggered Communication Mode must be enabled.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
-} CAN_RxHeaderTypeDef;
-
-/**
- * @brief CAN handle Structure definition
- */
-typedef struct __CAN_HandleTypeDef
-{
- CAN_TypeDef *Instance; /*!< Register base address */
-
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
- __IO uint32_t ErrorCode; /*!< CAN Error code.
- This parameter can be a value of @ref CAN_Error_Code */
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
- void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
- void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
- void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
- void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
- void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
- void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
- void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
- void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
- void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
- void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
- void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
- void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
- void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
-
- void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
- void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
-
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-} CAN_HandleTypeDef;
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-/**
- * @brief HAL CAN common Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
- HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
- HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
- HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
- HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
- HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
- HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
- HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
- HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
- HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
- HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
- HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
- HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
-
- HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
- HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
-
-} HAL_CAN_CallbackIDTypeDef;
-
-/**
- * @brief HAL CAN Callback pointer definition
- */
-typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
-
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
- * @{
- */
-
-/** @defgroup CAN_Error_Code CAN Error Code
- * @{
- */
-#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
-#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
-#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
-#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
-#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
-#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
-#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
-#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
-#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
-#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
-#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
-#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
-#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
-#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
-#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
-#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
-#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
- * @{
- */
-#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
- * @{
- */
-#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
-#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
-#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
-#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-/**
- * @}
- */
-
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
- * @{
- */
-#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
-#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
-#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
- * @{
- */
-#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
-#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
-#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
-#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
-#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
-#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
-#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
-#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
-#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
-#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
-#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
-#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
-#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
-#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
-#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
- * @{
- */
-#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
-#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
-#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
-#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
-#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
-#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
-#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
-#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
- * @{
- */
-#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
- * @{
- */
-#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_activation CAN Filter Activation
- * @{
- */
-#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
-#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
- * @{
- */
-#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type CAN Identifier Type
- * @{
- */
-#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
-#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
- * @{
- */
-#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
-#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
- * @{
- */
-#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
-#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
- * @{
- */
-#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
-#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
-#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags CAN Flags
- * @{
- */
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
-#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
-#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
-#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
-#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
-#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
-#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
-#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
-#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
-#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
-#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
-#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
-#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
-#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
-#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
-#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
-#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
-#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
-#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
-#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
-#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
-
-/* Error Flags */
-#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
-#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
-#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Interrupts CAN Interrupts
- * @{
- */
-/* Transmit Interrupt */
-#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
- * @{
- */
-
-/** @brief Reset CAN handle state
- * @param __HANDLE__ CAN handle.
- * @retval None
- */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_CAN_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle.
- * @param __INTERRUPT__ CAN Interrupt sources to enable.
- * This parameter can be any combination of @arg CAN_Interrupts
- * @retval None
- */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CAN interrupts.
- * @param __HANDLE__ CAN handle.
- * @param __INTERRUPT__ CAN Interrupt sources to disable.
- * This parameter can be any combination of @arg CAN_Interrupts
- * @retval None
- */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __INTERRUPT__ specifies the CAN interrupt source to check.
- * This parameter can be a value of @arg CAN_Interrupts
- * @retval The state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
-
-/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of @arg CAN_flags
- * @retval The state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__ specifies the CAN Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
- * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
- * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
- * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
- * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
- * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
- * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
- * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
- * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
- * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
- * @retval None
- */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions CAN Exported Functions
- * @{
- */
-
-/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
-HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
-
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
- * @brief Configuration functions
- * @{
- */
-
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- * @{
- */
-
-/* Control functions **********************************************************/
-HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
-HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
-uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
-uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
-HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
-uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- * @{
- */
-/* Interrupts management ******************************************************/
-HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
-HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
- * @brief Callback functions
- * @{
- */
-/* Callbacks functions ********************************************************/
-
-void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-#define CAN_FLAG_MASK (0x000000FFU)
-/**
- * @}
- */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
- ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
- ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
- ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
- ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
- ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
- ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
- ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
-#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
- ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
- ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
- ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
-#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
-#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
- ((ACTIVATION) == CAN_FILTER_ENABLE))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
- ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
- ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
-#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
-#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
-#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
- CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
- CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
- CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
- CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
- CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
- CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/**
- * @}
- */
-
-
-#endif /* CAN1 */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h
deleted file mode 100644
index c26dc66dc0..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_conf_template.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_conf_template.h
- * @author MCD Application Team
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32f2xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CONF_H
-#define __STM32F2xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DCMI_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_PCCARD_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_HASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_HCD_MODULE_ENABLED
-#define HAL_MMC_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
- #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
- #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature.*/
-/**
- * @brief External Low Speed oscillator (LSE) value.
- */
-#if !defined (LSE_VALUE)
- #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
- * @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
- * frequency, this source is inserted directly through I2S_CKIN pad.
- */
-#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
-#define INSTRUCTION_CACHE_ENABLE 1U
-#define DATA_CACHE_ENABLE 1U
-
-#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
-#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
-#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
-#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
-#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
-#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
-#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
-#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
-#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
-#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
-#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
-#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
-#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
-#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
-#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
-#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
-#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
-#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
-#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
-#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
-#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
-#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
-#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
-#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
-#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2U
-#define MAC_ADDR1 0U
-#define MAC_ADDR2 0U
-#define MAC_ADDR3 0U
-#define MAC_ADDR4 0U
-#define MAC_ADDR5 0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY 0x00000FFFU
-
-#define PHY_READ_TO 0x0000FFFFU
-#define PHY_WRITE_TO 0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
-
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
-#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
-
-#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
-#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
-
-#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
-#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC 1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f2xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f2xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32f2xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32f2xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f2xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f2xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f2xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "stm32f2xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f2xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32f2xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f2xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
- #include "stm32f2xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
- #include "stm32f2xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f2xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f2xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f2xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f2xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f2xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f2xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f2xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f2xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f2xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f2xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f2xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f2xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f2xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f2xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f2xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f2xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f2xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f2xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f2xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f2xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f2xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f2xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f2xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h
deleted file mode 100644
index 8502ef1a63..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cortex.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CORTEX_H
-#define __STM32F2xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
-#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
-#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h
deleted file mode 100644
index 40b6a60b36..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_crc.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_CRC_H
-#define STM32F2xx_HAL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
- * @{
- */
-
-/**
- * @brief CRC HAL State Structure definition
- */
-typedef enum
-{
- HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
- HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
-} HAL_CRC_StateTypeDef;
-
-
-/**
- * @brief CRC Handle Structure definition
- */
-typedef struct
-{
- CRC_TypeDef *Instance; /*!< Register base address */
-
- HAL_LockTypeDef Lock; /*!< CRC Locking object */
-
- __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-
-} CRC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @brief Reset CRC handle state.
- * @param __HANDLE__ CRC handle.
- * @retval None
- */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
- * @brief Reset CRC Data Register.
- * @param __HANDLE__ CRC handle
- * @retval None
- */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
- * @brief Store data in the Independent Data (ID) register.
- * @param __HANDLE__ CRC handle
- * @param __VALUE__ Value to be stored in the ID register
- * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
- * @retval None
- */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
- * @brief Return the data stored in the Independent Data (ID) register.
- * @param __HANDLE__ CRC handle
- * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
- * @retval Value of the ID register
- */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
- * @}
- */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRC_Private_Macros CRC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
- * @}
- */
-
-/* Peripheral State and Error functions ***************************************/
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h
deleted file mode 100644
index 8d09e5c45b..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_cryp.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_cryp.h
- * @author MCD Application Team
- * @brief Header file of CRYP HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_CRYP_H
-#define __STM32F2xx_HAL_CRYP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(CRYP)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CRYP CRYP
- * @brief CRYP HAL module driver.
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
- * @{
- */
-
-/**
- * @brief CRYP Init Structure definition
- */
-
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
- This parameter can be a value of @ref CRYP_Data_Type */
- uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
- This parameter can be a value of @ref CRYP_Key_Size */
- uint32_t* pKey; /*!< The key used for encryption/decryption */
- uint32_t* pInitVect; /*!< The initialization vector used also as initialization
- counter in CTR mode */
- uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC*/
-
- uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
-}CRYP_ConfigTypeDef;
-
-
-/**
- * @brief CRYP State Structure definition
- */
-
-typedef enum
-{
- HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
- HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
- HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
-}HAL_CRYP_STATETypeDef;
-
-
-/**
- * @brief CRYP handle Structure definition
- */
-
-typedef struct __CRYP_HandleTypeDef
-{
-
- CRYP_TypeDef *Instance; /*!< CRYP registers base address */
-
- CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
-
- uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
- __IO uint16_t CrypInCount; /*!< Counter of input data */
-
- __IO uint16_t CrypOutCount; /*!< Counter of output data */
-
- uint16_t Size; /*!< length of input data in word */
-
- uint32_t Phase; /*!< CRYP peripheral phase */
-
- DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-
- DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
- __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
- __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
- void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */
- void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */
- void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */
-
- void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
- void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
-
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-
-}CRYP_HandleTypeDef;
-
-
-/**
- * @}
- */
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
- * @brief HAL CRYP Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */
- HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */
- HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */
-
- HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
- HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
-
-}HAL_CRYP_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
- * @brief HAL CRYP Callback pointer definition
- * @{
- */
-
-typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */
-
-/**
- * @}
- */
-
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
- * @{
- */
-
-/** @defgroup CRYP_Error_Definition CRYP Error Definition
- * @{
- */
-#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
-#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
-#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
-#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
-#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
-#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
-#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
- * @{
- */
-
-#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
- * @{
- */
-
-#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
-#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
-#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
-#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
-#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
-#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
-#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Key_Size CRYP Key Size
- * @{
- */
-
-#define CRYP_KEYSIZE_128B 0x00000000U
-#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
-#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
- * @{
- */
-
-#define CRYP_DATATYPE_32B 0x00000000U
-#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Interrupt CRYP Interrupt
- * @{
- */
-
-#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
-#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
-
-/**
- * @}
- */
-
-/** @defgroup CRYP_Flags CRYP Flags
- * @{
- */
-
-/* Flags in the SR register */
-#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
-#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
-#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
-#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
-#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
- or a key preparation (for AES decryption). */
-/* Flags in the RISR register */
-#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
-#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
- * @{
- */
-
-/** @brief Reset CRYP handle state
- * @param __HANDLE__ specifies the CRYP handle.
- * @retval None
- */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0)
-#else
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__: specifies the CRYP handle.
- * @retval None
- */
-
-#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
-#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
-
-/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values for CRYP:
- * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
- * or a key preparation (for AES decryption).
- * @arg CRYP_FLAG_IFEM: Input FIFO is empty
- * @arg CRYP_FLAG_IFNF: Input FIFO is not full
- * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
- * @arg CRYP_FLAG_OFNE: Output FIFO is not empty
- * @arg CRYP_FLAG_OFFU: Output FIFO is full
- * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
- */
-#define CRYP_FLAG_MASK 0x0000001FU
-
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
-
-/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
- * This parameter can be one of the following values for CRYP:
- * @arg CRYP_IT_INI: Input FIFO service masked interrupt status
- * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
- * @retval The state of __INTERRUPT__ (TRUE or FALSE).
- */
-
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Enable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for CRYP:
- * @ CRYP_IT_INI : Input FIFO service interrupt mask.
- * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
- * @retval None
- */
-
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
- * This parameter can be one of the following values for CRYP:
- * @ CRYP_IT_INI : Input FIFO service interrupt mask.
- * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
- * @retval None
- */
-
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
- * @{
- */
-
-/** @addtogroup CRYP_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup CRYP_Exported_Functions_Group2
- * @{
- */
-
-/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-
-/**
- * @}
- */
-
-
-/** @addtogroup CRYP_Exported_Functions_Group3
- * @{
- */
-/* Interrupt Handler functions **********************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
- * @{
- */
-
-/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
- * @{
- */
-
-#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
- ((ALGORITHM) == CRYP_DES_CBC) || \
- ((ALGORITHM) == CRYP_TDES_ECB) || \
- ((ALGORITHM) == CRYP_TDES_CBC) || \
- ((ALGORITHM) == CRYP_AES_ECB) || \
- ((ALGORITHM) == CRYP_AES_CBC) || \
- ((ALGORITHM) == CRYP_AES_CTR))
-
-#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_192B) || \
- ((KEYSIZE) == CRYP_KEYSIZE_256B))
-
-#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
- ((DATATYPE) == CRYP_DATATYPE_16B) || \
- ((DATATYPE) == CRYP_DATATYPE_8B) || \
- ((DATATYPE) == CRYP_DATATYPE_1B))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
- * @{
- */
-
-/**
- * @}
- */
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-#endif /* CRYP */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h
deleted file mode 100644
index 368d800c79..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DAC_H
-#define STM32F2xx_HAL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
-
-} HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
- */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-{
- DAC_TypeDef *Instance; /*!< Register base address */
-
- __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
-
- HAL_LockTypeDef Lock; /*!< DAC locking object */
-
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
- __IO uint32_t ErrorCode; /*!< DAC Error code */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
-
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
-
-
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-} DAC_HandleTypeDef;
-
-/**
- * @brief DAC Configuration regular Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-
-} DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL DAC Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
- HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
- HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
- HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
-
- HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
- HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
- HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
- HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
-
- HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
- HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
- HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
-} HAL_DAC_CallbackIDTypeDef;
-
-/**
- * @brief HAL DAC Callback pointer definition
- */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_Error_Code DAC Error Code
- * @{
- */
-#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
-#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
-#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
- * @{
- */
-#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer DAC output buffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
- * @{
- */
-#define DAC_CHANNEL_1 0x00000000U
-
-#define DAC_CHANNEL_2 0x00000010U
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment DAC data alignment
- * @{
- */
-#define DAC_ALIGN_12B_R 0x00000000U
-#define DAC_ALIGN_12B_L 0x00000004U
-#define DAC_ALIGN_8B_R 0x00000008U
-
-/**
- * @}
- */
-
-/** @defgroup DAC_flags_definition DAC flags definition
- * @{
- */
-#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
-
-#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
-
-
-/**
- * @}
- */
-
-/** @defgroup DAC_IT_definition DAC IT definition
- * @{
- */
-#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
-
-#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @brief Reset DAC handle state.
- * @param __HANDLE__ specifies the DAC handle.
- * @retval None
- */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __DAC_Channel__ specifies the DAC channel
- * @retval None
- */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
- ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Disable the DAC channel.
- * @param __HANDLE__ specifies the DAC handle
- * @param __DAC_Channel__ specifies the DAC channel.
- * @retval None
- */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
- ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Set DHR12R1 alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
-
-
-/** @brief Set DHR12R2 alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
-
-
-/** @brief Set DHR12RD alignment.
- * @param __ALIGNMENT__ specifies the DAC alignment
- * @retval None
- */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
- * @param __HANDLE__ specifies the DAC handle
- * @param __INTERRUPT__ specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief Check whether the specified DAC interrupt source is enabled or not.
- * @param __HANDLE__ DAC handle
- * @param __INTERRUPT__ DAC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
- & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to get.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the DAC's flag.
- * @param __HANDLE__ specifies the DAC handle.
- * @param __FLAG__ specifies the DAC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-
-/**
- * @}
- */
-
-/* Include DAC HAL Extended module */
-#include "stm32f2xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
- pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Private_Functions DAC Private Functions
- * @{
- */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h
deleted file mode 100644
index 6a760320fd..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dac_ex.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_dac_ex.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DAC_EX_H
-#define STM32F2xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DACEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL State structures definition
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
- * @{
- */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
- * @{
- */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-
-HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
-
-/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
-/* are called by HAL_DAC_Start_DMA */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h
deleted file mode 100644
index b6ab036e2e..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi.h
+++ /dev/null
@@ -1,588 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_dcmi.h
- * @author MCD Application Team
- * @brief Header file of DCMI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_DCMI_H
-#define STM32F2xx_HAL_DCMI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined (DCMI)
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DCMI DCMI
- * @brief DCMI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DCMI_Exported_Types DCMI Exported Types
- * @{
- */
-/**
- * @brief HAL DCMI State structures definition
- */
-typedef enum
-{
- HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
- HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
- HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
- HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
- HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
- HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
-} HAL_DCMI_StateTypeDef;
-
-/**
- * @brief DCMIEx Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
- uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
- uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
- uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-} DCMI_CodesInitTypeDef;
-
-/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
- */
-typedef struct
-{
- uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
- uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
- uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
- uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
-} DCMI_SyncUnmaskTypeDef;
-/**
- * @brief DCMI Init structure definition
- */
-typedef struct
-{
- uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
- This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
- uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
- This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
- uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
- uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
- This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
- uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
- This parameter can be a value of @ref DCMI_Capture_Rate */
-
- uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
- This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
- DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
- line/frame end delimiter */
-
- uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-} DCMI_InitTypeDef;
-
-/**
- * @brief DCMI handle Structure definition
- */
-typedef struct __DCMI_HandleTypeDef
-{
- DCMI_TypeDef *Instance; /*!< DCMI Register base address */
-
- DCMI_InitTypeDef Init; /*!< DCMI parameters */
-
- HAL_LockTypeDef Lock; /*!< DCMI locking object */
-
- __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
-
- __IO uint32_t XferCount; /*!< DMA transfer counter */
-
- __IO uint32_t XferSize; /*!< DMA transfer size */
-
- uint32_t XferTransferNumber; /*!< DMA transfer number */
-
- uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
-
- __IO uint32_t ErrorCode; /*!< DCMI Error code */
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
- void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
- void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
- void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
- void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
- void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
- void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-} DCMI_HandleTypeDef;
-
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-typedef enum
-{
- HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
- HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
- HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
- HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
- HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
- HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
-
-} HAL_DCMI_CallbackIDTypeDef;
-
-typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
- * @{
- */
-
-/** @defgroup DCMI_Error_Code DCMI Error Code
- * @{
- */
-#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
-#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
-#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
-#endif
-/**
- * @}
- */
-
-/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
- * @{
- */
-#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
- into the destination memory through the DMA */
-#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
- frame and then transfers a single frame through the DMA */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
- * @{
- */
-#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
- is synchronized with the HSYNC/VSYNC signals */
-#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
- synchronization codes embedded in the data flow */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
- * @{
- */
-#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
-#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
- * @{
- */
-#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
-#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
- * @{
- */
-#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
-#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
- * @{
- */
-#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
-#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
- * @{
- */
-#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
-#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
-#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
- * @{
- */
-#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
-#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
- * @{
- */
-#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_Window_Height DCMI Window Height
- * @{
- */
-#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
-
-/**
- * @}
- */
-
-/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
- * @{
- */
-#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
-#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
-#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
-#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
-#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
-/**
- * @}
- */
-
-/** @defgroup DCMI_Flags DCMI Flags
- * @{
- */
-
-/**
- * @brief DCMI SR register
- */
-#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
-#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
-#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
-/**
- * @brief DCMI RIS register
- */
-#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
-#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
-#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
-#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
-#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
-/**
- * @brief DCMI MIS register
- */
-#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
-#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
-#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
-#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
-#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
- * @{
- */
-
-/** @brief Reset DCMI handle state
- * @param __HANDLE__ specifies the DCMI handle.
- * @retval None
- */
-#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-
-/**
- * @brief Enable the DCMI.
- * @param __HANDLE__ DCMI handle
- * @retval None
- */
-#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
-
-/**
- * @brief Disable the DCMI.
- * @param __HANDLE__ DCMI handle
- * @retval None
- */
-#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
-
-/* Interrupt & Flag management */
-/**
- * @brief Get the DCMI pending flag.
- * @param __HANDLE__ DCMI handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be one of the following values (no combination allowed)
- * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
- * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
- * @arg DCMI_FLAG_FNE: FIFO empty flag
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
- * @arg DCMI_FLAG_OVRRI: Overrun flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
- * @arg DCMI_FLAG_LINERI: Line flag mask
- * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
- * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
- * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
- * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
- * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
- * @retval The state of FLAG.
- */
-#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
-((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
- (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
-
-/**
- * @brief Clear the DCMI pending flags.
- * @param __HANDLE__ DCMI handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
- * @arg DCMI_FLAG_OVFRI: Overflow flag mask
- * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
- * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
- * @arg DCMI_FLAG_LINERI: Line flag mask
- * @retval None
- */
-#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/**
- * @brief Enable the specified DCMI interrupts.
- * @param __HANDLE__ DCMI handle
- * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified DCMI interrupts.
- * @param __HANDLE__ DCMI handle
- * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval None
- */
-#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified DCMI interrupt has occurred or not.
- * @param __HANDLE__ DCMI handle
- * @param __INTERRUPT__ specifies the DCMI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
- * @arg DCMI_IT_OVF: Overflow interrupt mask
- * @arg DCMI_IT_ERR: Synchronization error interrupt mask
- * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
- * @arg DCMI_IT_LINE: Line interrupt mask
- * @retval The state of INTERRUPT.
- */
-#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
- * @{
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
-HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
-void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
-HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
-HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
-
-/**
- * @}
- */
-
-/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
-uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DCMI_Private_Constants DCMI Private Constants
- * @{
- */
-#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
-#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
-/**
- * @}
- */
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup DCMI_Private_Macros DCMI Private Macros
- * @{
- */
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
- ((MODE) == DCMI_MODE_SNAPSHOT))
-
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
- ((MODE) == DCMI_SYNCHRO_EMBEDDED))
-
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
- ((POLARITY) == DCMI_PCKPOLARITY_RISING))
-
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_VSPOLARITY_HIGH))
-
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
- ((POLARITY) == DCMI_HSPOLARITY_HIGH))
-
-#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
- ((JPEG_MODE) == DCMI_JPEG_ENABLE))
-
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
- ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
-
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
- ((DATA) == DCMI_EXTEND_DATA_10B) || \
- ((DATA) == DCMI_EXTEND_DATA_12B) || \
- ((DATA) == DCMI_EXTEND_DATA_14B))
-
-#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
-
-#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DCMI_Private_Functions DCMI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* DCMI */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi_ex.h
deleted file mode 100644
index 9d917e6f12..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dcmi_ex.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_dcmi_ex.h
- * @author MCD Application Team
- * @brief Header file of DCMI Extension HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DCMI_EX_H
-#define __STM32F2xx_HAL_DCMI_EX_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-#endif /* __STM32F2xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h
deleted file mode 100644
index 20b47c69f6..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_def.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DEF
-#define __STM32F2xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DMA_H
-#define __STM32F2xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @brief DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specifies the channel used for the specified stream.
- This parameter can be a value of @ref DMA_Channel_selection */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
- This parameter can be a value of @ref DMA_Priority_level */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
- This parameter can be a value of @ref DMA_FIFO_direct_mode
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected stream */
-
- uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_FIFO_threshold_level */
-
- uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_Memory_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-
- uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_Peripheral_burst
- @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
- HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
- HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
- HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- DMA_Stream_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
-
- void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
-
- uint32_t StreamIndex; /*!< DMA Stream Index */
-
-}DMA_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @brief DMA Exported constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @brief DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
-#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
-#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
-#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
-#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
-#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
-#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Channel_selection DMA Channel selection
- * @brief DMA channel selection
- * @{
- */
-#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @brief DMA data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @brief DMA peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @brief DMA memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @brief DMA peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @brief DMA memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @brief DMA mode
- * @{
- */
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
-#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @brief DMA priority levels
- * @{
- */
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
-/**
- * @}
- */
-
-/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
- * @brief DMA FIFO direct mode
- * @{
- */
-#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
- * @brief DMA FIFO level
- * @{
- */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
-#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_burst DMA Memory burst
- * @brief DMA memory burst
- * @{
- */
-#define DMA_MBURST_SINGLE 0x00000000U
-#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
-#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
-#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
- * @brief DMA peripheral burst
- * @{
- */
-#define DMA_PBURST_SINGLE 0x00000000U
-#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @brief DMA interrupts definition
- * @{
- */
-#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE 0x00000080U
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @brief DMA flag definitions
- * @{
- */
-#define DMA_FLAG_FEIF0_4 0x00000001U
-#define DMA_FLAG_DMEIF0_4 0x00000004U
-#define DMA_FLAG_TEIF0_4 0x00000008U
-#define DMA_FLAG_HTIF0_4 0x00000010U
-#define DMA_FLAG_TCIF0_4 0x00000020U
-#define DMA_FLAG_FEIF1_5 0x00000040U
-#define DMA_FLAG_DMEIF1_5 0x00000100U
-#define DMA_FLAG_TEIF1_5 0x00000200U
-#define DMA_FLAG_HTIF1_5 0x00000400U
-#define DMA_FLAG_TCIF1_5 0x00000800U
-#define DMA_FLAG_FEIF2_6 0x00010000U
-#define DMA_FLAG_DMEIF2_6 0x00040000U
-#define DMA_FLAG_TEIF2_6 0x00080000U
-#define DMA_FLAG_HTIF2_6 0x00100000U
-#define DMA_FLAG_TCIF2_6 0x00200000U
-#define DMA_FLAG_FEIF3_7 0x00400000U
-#define DMA_FLAG_DMEIF3_7 0x01000000U
-#define DMA_FLAG_TEIF3_7 0x02000000U
-#define DMA_FLAG_HTIF3_7 0x04000000U
-#define DMA_FLAG_TCIF3_7 0x08000000U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reset DMA handle state
- * @param __HANDLE__ specifies the DMA handle.
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Return the current DMA Stream FIFO filled level.
- * @param __HANDLE__ DMA handle
- * @retval The FIFO filling state.
- * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
- * and not empty.
- * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
- * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
- * - DMA_FIFOStatus_Empty: when FIFO is empty
- * - DMA_FIFOStatus_Full: when FIFO is full
- */
-#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
-
-/**
- * @brief Enable the specified DMA Stream.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
-
-/**
- * @brief Disable the specified DMA Stream.
- * @param __HANDLE__ DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Return the current DMA Stream transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
- DMA_FLAG_TCIF3_7)
-
-/**
- * @brief Return the current DMA Stream half transfer complete flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
- DMA_FLAG_HTIF3_7)
-
-/**
- * @brief Return the current DMA Stream transfer error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
- DMA_FLAG_TEIF3_7)
-
-/**
- * @brief Return the current DMA Stream FIFO error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified FIFO error flag index.
- */
-#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
- DMA_FLAG_FEIF3_7)
-
-/**
- * @brief Return the current DMA Stream direct mode error flag.
- * @param __HANDLE__ DMA handle
- * @retval The specified direct mode error flag index.
- */
-#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
- DMA_FLAG_DMEIF3_7)
-
-/**
- * @brief Get the DMA Stream pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag.
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
- * @arg DMA_FLAG_TEIFx: Transfer error flag.
- * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
- * @arg DMA_FLAG_FEIFx: FIFO error flag.
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
-
-/**
- * @brief Clear the DMA Stream pending flags.
- * @param __HANDLE__ DMA handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCIFx: Transfer complete flag.
- * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
- * @arg DMA_FLAG_TEIFx: Transfer error flag.
- * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
- * @arg DMA_FLAG_FEIFx: FIFO error flag.
- * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
-
-/**
- * @brief Enable the specified DMA Stream interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
-
-/**
- * @brief Disable the specified DMA Stream interrupts.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
-
-/**
- * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
- * @param __HANDLE__ DMA handle
- * @param __INTERRUPT__ specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask.
- * @arg DMA_IT_HT: Half transfer complete interrupt mask.
- * @arg DMA_IT_TE: Transfer error interrupt mask.
- * @arg DMA_IT_FE: FIFO error interrupt mask.
- * @arg DMA_IT_DME: Direct mode error interrupt.
- * @retval The state of DMA_IT.
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
- ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
- ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
-
-/**
- * @brief Writes the number of data units to be transferred on the DMA Stream.
- * @param __HANDLE__ DMA handle
- * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
- * Number of data items depends only on the Peripheral data format.
- *
- * @note If Peripheral data format is Bytes: number of data units is equal
- * to total number of bytes to be transferred.
- *
- * @note If Peripheral data format is Half-Word: number of data units is
- * equal to total number of bytes to be transferred / 2.
- *
- * @note If Peripheral data format is Word: number of data units is equal
- * to total number of bytes to be transferred / 4.
- *
- * @retval The number of remaining data units in the current DMAy Streamx transfer.
- */
-#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
-
-/**
- * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param __HANDLE__ DMA handle
- *
- * @retval The number of remaining data units in the current DMA Stream transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
-
-
-/* Include DMA HAL Extension module */
-#include "stm32f2xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
- * @brief DMA Exported functions
- * @{
- */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
- * @brief I/O operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/**
- * @}
- */
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
- * @brief DMA private defines and constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @brief DMA private macros
- * @{
- */
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
- ((CHANNEL) == DMA_CHANNEL_1) || \
- ((CHANNEL) == DMA_CHANNEL_2) || \
- ((CHANNEL) == DMA_CHANNEL_3) || \
- ((CHANNEL) == DMA_CHANNEL_4) || \
- ((CHANNEL) == DMA_CHANNEL_5) || \
- ((CHANNEL) == DMA_CHANNEL_6) || \
- ((CHANNEL) == DMA_CHANNEL_7))
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR) || \
- ((MODE) == DMA_PFCTRL))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
- ((STATE) == DMA_FIFOMODE_ENABLE))
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
- ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
- ((BURST) == DMA_MBURST_INC4) || \
- ((BURST) == DMA_MBURST_INC8) || \
- ((BURST) == DMA_MBURST_INC16))
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
- ((BURST) == DMA_PBURST_INC4) || \
- ((BURST) == DMA_PBURST_INC8) || \
- ((BURST) == DMA_PBURST_INC16))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @brief DMA private functions
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h
deleted file mode 100644
index e633c564a4..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_dma_ex.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_DMA_EX_H
-#define __STM32F2xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
- * @brief DMAEx Exported types
- * @{
- */
-
-/**
- * @brief HAL DMA Memory definition
- */
-typedef enum
-{
- MEMORY0 = 0x00U, /*!< Memory 0 */
- MEMORY1 = 0x01U /*!< Memory 1 */
-}HAL_DMA_MemoryTypeDef;
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
- * @brief DMAEx Exported functions
- * @{
- */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- * @{
- */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
- * @brief DMAEx Private functions
- * @{
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h
deleted file mode 100644
index cef213e472..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_eth.h
+++ /dev/null
@@ -1,2217 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_eth.h
- * @author MCD Application Team
- * @brief Header file of ETH HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_ETH_H
-#define __STM32F2xx_HAL_ETH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined (ETH)
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ETH
- * @{
- */
-
-/** @defgroup ETH_Private_Macros ETH Private Macros
- * @{
- */
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
- ((SPEED) == ETH_SPEED_100M))
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
- ((CMD) == ETH_WATCHDOG_DISABLE))
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
- ((CMD) == ETH_JABBER_DISABLE))
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
- ((CMD) == ETH_CARRIERSENCE_DISABLE))
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
- ((CMD) == ETH_RECEIVEOWN_DISABLE))
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_1))
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
- ((CMD) == ETH_RECEIVEAll_DISABLE))
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
- ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
- ((CMD) == ETH_FIXEDBURST_DISABLE))
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
- ((FLAG) == ETH_DMATXDESC_IC) || \
- ((FLAG) == ETH_DMATXDESC_LS) || \
- ((FLAG) == ETH_DMATXDESC_FS) || \
- ((FLAG) == ETH_DMATXDESC_DC) || \
- ((FLAG) == ETH_DMATXDESC_DP) || \
- ((FLAG) == ETH_DMATXDESC_TTSE) || \
- ((FLAG) == ETH_DMATXDESC_TER) || \
- ((FLAG) == ETH_DMATXDESC_TCH) || \
- ((FLAG) == ETH_DMATXDESC_TTSS) || \
- ((FLAG) == ETH_DMATXDESC_IHE) || \
- ((FLAG) == ETH_DMATXDESC_ES) || \
- ((FLAG) == ETH_DMATXDESC_JT) || \
- ((FLAG) == ETH_DMATXDESC_FF) || \
- ((FLAG) == ETH_DMATXDESC_PCE) || \
- ((FLAG) == ETH_DMATXDESC_LCA) || \
- ((FLAG) == ETH_DMATXDESC_NC) || \
- ((FLAG) == ETH_DMATXDESC_LCO) || \
- ((FLAG) == ETH_DMATXDESC_EC) || \
- ((FLAG) == ETH_DMATXDESC_VF) || \
- ((FLAG) == ETH_DMATXDESC_CC) || \
- ((FLAG) == ETH_DMATXDESC_ED) || \
- ((FLAG) == ETH_DMATXDESC_UF) || \
- ((FLAG) == ETH_DMATXDESC_DB))
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
- ((FLAG) == ETH_DMARXDESC_AFM) || \
- ((FLAG) == ETH_DMARXDESC_ES) || \
- ((FLAG) == ETH_DMARXDESC_DE) || \
- ((FLAG) == ETH_DMARXDESC_SAF) || \
- ((FLAG) == ETH_DMARXDESC_LE) || \
- ((FLAG) == ETH_DMARXDESC_OE) || \
- ((FLAG) == ETH_DMARXDESC_VLAN) || \
- ((FLAG) == ETH_DMARXDESC_FS) || \
- ((FLAG) == ETH_DMARXDESC_LS) || \
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
- ((FLAG) == ETH_DMARXDESC_LC) || \
- ((FLAG) == ETH_DMARXDESC_FT) || \
- ((FLAG) == ETH_DMARXDESC_RWT) || \
- ((FLAG) == ETH_DMARXDESC_RE) || \
- ((FLAG) == ETH_DMARXDESC_DBE) || \
- ((FLAG) == ETH_DMARXDESC_CE) || \
- ((FLAG) == ETH_DMARXDESC_MAMPCE))
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
- ((FLAG) == ETH_PMT_FLAG_MPR))
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
- ((FLAG) == ETH_DMA_FLAG_T))
-#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFD87U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
- ((IT) == ETH_MAC_IT_PMT))
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
- ((FLAG) == ETH_MAC_FLAG_PMT))
-#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
-#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFF) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
- ((IT) != 0x00U))
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
-
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Private_Defines ETH Private Defines
- * @{
- */
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY 0x00000001U
-
-/* ETHERNET Errors */
-#define ETH_SUCCESS 0U
-#define ETH_ERROR 1U
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
-
-/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
-
-/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
-
-/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8U
-
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Types ETH Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
- HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
- HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
- HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
- HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_ETH_StateTypeDef;
-
-/**
- * @brief ETH Init Structure definition
- */
-
-typedef struct
-{
- uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
- The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
- and the mode (half/full-duplex).
- This parameter can be a value of @ref ETH_AutoNegotiation */
-
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
- This parameter can be a value of @ref ETH_Speed */
-
- uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
- This parameter can be a value of @ref ETH_Duplex_Mode */
-
- uint16_t PhyAddress; /*!< Ethernet PHY address.
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
- This parameter can be a value of @ref ETH_Rx_Mode */
-
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
- This parameter can be a value of @ref ETH_Checksum_Mode */
-
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
- This parameter can be a value of @ref ETH_Media_Interface */
-
-} ETH_InitTypeDef;
-
-
-/**
- * @brief ETH MAC Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t Watchdog; /*!< Selects or not the Watchdog timer
- When enabled, the MAC allows no more then 2048 bytes to be received.
- When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_Watchdog */
-
- uint32_t Jabber; /*!< Selects or not Jabber timer
- When enabled, the MAC allows no more then 2048 bytes to be sent.
- When disabled, the MAC can send up to 16384 bytes.
- This parameter can be a value of @ref ETH_Jabber */
-
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
- This parameter can be a value of @ref ETH_Inter_Frame_Gap */
-
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
- This parameter can be a value of @ref ETH_Carrier_Sense */
-
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
- ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode.
- This parameter can be a value of @ref ETH_Receive_Own */
-
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
- This parameter can be a value of @ref ETH_Loop_Back_Mode */
-
- uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
- This parameter can be a value of @ref ETH_Checksum_Offload */
-
- uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a collision occurs (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Retry_Transmission */
-
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
- This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
-
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
- This parameter can be a value of @ref ETH_Back_Off_Limit */
-
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Deferral_Check */
-
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
- This parameter can be a value of @ref ETH_Receive_All */
-
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
- This parameter can be a value of @ref ETH_Source_Addr_Filter */
-
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
- This parameter can be a value of @ref ETH_Pass_Control_Frames */
-
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
- This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
-
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
- This parameter can be a value of @ref ETH_Destination_Addr_Filter */
-
- uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
- This parameter can be a value of @ref ETH_Promiscuous_Mode */
-
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
-
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
-
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
-
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
-
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
-
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
- This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
-
- uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame.
- This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
- uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address).
- This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
-
- uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
- disable its transmitter for a specified time (Pause Time)
- This parameter can be a value of @ref ETH_Receive_Flow_Control */
-
- uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
- or the MAC back-pressure operation (Half-Duplex mode)
- This parameter can be a value of @ref ETH_Transmit_Flow_Control */
-
- uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering.
- This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
-
- uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
-
-} ETH_MACInitTypeDef;
-
-
-/**
- * @brief ETH DMA Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
- This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
-
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
- This parameter can be a value of @ref ETH_Receive_Store_Forward */
-
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
- This parameter can be a value of @ref ETH_Flush_Received_Frame */
-
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
- This parameter can be a value of @ref ETH_Transmit_Store_Forward */
-
- uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
- This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
-
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
- This parameter can be a value of @ref ETH_Forward_Error_Frames */
-
- uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
- and length less than 64 bytes) including pad-bytes and CRC)
- This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
-
- uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
- This parameter can be a value of @ref ETH_Receive_Threshold_Control */
-
- uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
- frame of Transmit data even before obtaining the status for the first frame.
- This parameter can be a value of @ref ETH_Second_Frame_Operate */
-
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
- This parameter can be a value of @ref ETH_Address_Aligned_Beats */
-
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
- This parameter can be a value of @ref ETH_Fixed_Burst */
-
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
- This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
-
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
- This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-
- uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
- This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
-
- uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
- This parameter can be a value of @ref ETH_DMA_Arbitration */
-} ETH_DMAInitTypeDef;
-
-
-/**
- * @brief ETH DMA Descriptors data structure definition
- */
-
-typedef struct
-{
- __IO uint32_t Status; /*!< Status */
-
- uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
-
- uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
-
- uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
-
- /*!< Enhanced ETHERNET DMA PTP Descriptors */
- uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
-
- uint32_t Reserved1; /*!< Reserved */
-
- uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
-
- uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
-
-} ETH_DMADescTypeDef;
-
-
-/**
- * @brief Received Frame Information structure definition
- */
-typedef struct
-{
- ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
-
- ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
-
- uint32_t SegCount; /*!< Segment count */
-
- uint32_t length; /*!< Frame length */
-
- uint32_t buffer; /*!< Frame buffer */
-
-} ETH_DMARxFrameInfos;
-
-
-/**
- * @brief ETH Handle Structure definition
- */
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-typedef struct __ETH_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-{
- ETH_TypeDef *Instance; /*!< Register base address */
-
- ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
-
- uint32_t LinkStatus; /*!< Ethernet link status */
-
- ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
-
- ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
-
- ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
-
- __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
-
- HAL_LockTypeDef Lock; /*!< ETH Lock */
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-
- void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */
- void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */
- void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */
- void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */
- void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */
-
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-} ETH_HandleTypeDef;
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL ETH Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
- HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
- HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
- HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
- HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
-
-} HAL_ETH_CallbackIDTypeDef;
-
-/**
- * @brief HAL ETH Callback pointer definition
- */
-typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */
-
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ETH_Exported_Constants ETH Exported Constants
- * @{
- */
-
-/** @defgroup ETH_Buffers_setting ETH Buffers setting
- * @{
- */
-#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC 4U /*!< Ethernet CRC */
-#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
-
-/* Ethernet driver receive buffers are organized in a chained linked-list, when
- an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
- to the driver receive buffers memory.
-
- Depending on the size of the received ethernet packet and the size of
- each ethernet driver receive buffer, the received packet can take one or more
- ethernet driver receive buffer.
-
- In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
- and the total count of the driver receive buffers ETH_RXBUFNB.
-
- The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_RX_BUF_SIZE
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
-#ifndef ETH_RXBUFNB
-#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
-#endif
-
-
-/* Ethernet driver transmit buffers are organized in a chained linked-list, when
- an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
- driver transmit buffers memory to the TxFIFO.
-
- Depending on the size of the Ethernet packet to be transmitted and the size of
- each ethernet driver transmit buffer, the packet to be transmitted can take
- one or more ethernet driver transmit buffer.
-
- In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
- and the total count of the driver transmit buffers ETH_TXBUFNB.
-
- The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_TX_BUF_SIZE
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
-#ifndef ETH_TXBUFNB
-#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
- * @{
- */
-
-/*
- DMA Tx Descriptor
- -----------------------------------------------------------------------------------------------
- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
- -----------------------------------------------------------------------------------------------
- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
- -----------------------------------------------------------------------------------------------
- TDES2 | Buffer1 Address [31:0] |
- -----------------------------------------------------------------------------------------------
- TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
- -----------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
- */
-#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
-#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
-#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
-#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
-#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
-#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
-
-/**
- * @brief Bit definition of TDES1 register
- */
-#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
-
-/**
- * @brief Bit definition of TDES2 register
- */
-#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
- * @brief Bit definition of TDES3 register
- */
-#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/*---------------------------------------------------------------------------------------------
-TDES6 | Transmit Time Stamp Low [31:0] |
------------------------------------------------------------------------------------------------
-TDES7 | Transmit Time Stamp High [31:0] |
-----------------------------------------------------------------------------------------------*/
-
-/* Bit definition of TDES6 register */
-#define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
-
-/* Bit definition of TDES7 register */
-#define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
-
-/**
- * @}
- */
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
- * @{
- */
-
-/*
- DMA Rx Descriptor
- --------------------------------------------------------------------------------------------------------------------
- RDES0 | OWN(31) | Status [30:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES2 | Buffer1 Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
- */
-#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/**
- * @brief Bit definition of RDES1 register
- */
-#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
-
-/**
- * @brief Bit definition of RDES2 register
- */
-#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
- * @brief Bit definition of RDES3 register
- */
-#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/*---------------------------------------------------------------------------------------------------------------------
- RDES4 | Reserved[31:15] | Extended Status [14:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES5 | Reserved[31:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES6 | Receive Time Stamp Low [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES7 | Receive Time Stamp High [31:0] |
- --------------------------------------------------------------------------------------------------------------------*/
-
-/* Bit definition of RDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
-#define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
-#define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
-
-/* Bit definition of RDES6 register */
-#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
-
-/* Bit definition of RDES7 register */
-#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
-/**
- * @}
- */
-/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
- * @{
- */
-#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
-#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
-
-/**
- * @}
- */
-/** @defgroup ETH_Speed ETH Speed
- * @{
- */
-#define ETH_SPEED_10M 0x00000000U
-#define ETH_SPEED_100M 0x00004000U
-
-/**
- * @}
- */
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
- * @{
- */
-#define ETH_MODE_FULLDUPLEX 0x00000800U
-#define ETH_MODE_HALFDUPLEX 0x00000000U
-/**
- * @}
- */
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
- * @{
- */
-#define ETH_RXPOLLING_MODE 0x00000000U
-#define ETH_RXINTERRUPT_MODE 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
- * @{
- */
-#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
-#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup ETH_Media_Interface ETH Media Interface
- * @{
- */
-#define ETH_MEDIA_INTERFACE_MII 0x00000000U
-#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
-/**
- * @}
- */
-
-/** @defgroup ETH_Watchdog ETH Watchdog
- * @{
- */
-#define ETH_WATCHDOG_ENABLE 0x00000000U
-#define ETH_WATCHDOG_DISABLE 0x00800000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Jabber ETH Jabber
- * @{
- */
-#define ETH_JABBER_ENABLE 0x00000000U
-#define ETH_JABBER_DISABLE 0x00400000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
- * @{
- */
-#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
-/**
- * @}
- */
-
-/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
- * @{
- */
-#define ETH_CARRIERSENCE_ENABLE 0x00000000U
-#define ETH_CARRIERSENCE_DISABLE 0x00010000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Own ETH Receive Own
- * @{
- */
-#define ETH_RECEIVEOWN_ENABLE 0x00000000U
-#define ETH_RECEIVEOWN_DISABLE 0x00002000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
- * @{
- */
-#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
-#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
- * @{
- */
-#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
-#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
- * @{
- */
-#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
-#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
-/**
- * @}
- */
-
-/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
- * @{
- */
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
- * @{
- */
-#define ETH_BACKOFFLIMIT_10 0x00000000U
-#define ETH_BACKOFFLIMIT_8 0x00000020U
-#define ETH_BACKOFFLIMIT_4 0x00000040U
-#define ETH_BACKOFFLIMIT_1 0x00000060U
-/**
- * @}
- */
-
-/** @defgroup ETH_Deferral_Check ETH Deferral Check
- * @{
- */
-#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
-#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_All ETH Receive All
- * @{
- */
-#define ETH_RECEIVEALL_ENABLE 0x80000000U
-#define ETH_RECEIVEAll_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
- * @{
- */
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
-#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
- * @{
- */
-#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
-/**
- * @}
- */
-
-/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
- * @{
- */
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
-/**
- * @}
- */
-
-/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
- * @{
- */
-#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
-#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
- * @{
- */
-#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
-#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
- * @{
- */
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
-#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
-#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
- * @{
- */
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
-#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
- * @{
- */
-#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
-#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
- * @{
- */
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
- * @{
- */
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
- * @{
- */
-#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
-#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
- * @{
- */
-#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
-#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
- * @{
- */
-#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
-#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses ETH MAC addresses
- * @{
- */
-#define ETH_MAC_ADDRESS0 0x00000000U
-#define ETH_MAC_ADDRESS1 0x00000008U
-#define ETH_MAC_ADDRESS2 0x00000010U
-#define ETH_MAC_ADDRESS3 0x00000018U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
- * @{
- */
-#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
-#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
- * @{
- */
-#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
-/**
- * @}
- */
-
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
- * @{
- */
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
- * @{
- */
-#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
-#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
- * @{
- */
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
- * @{
- */
-#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
-#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
- * @{
- */
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
- * @{
- */
-#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
-#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
- * @{
- */
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
- * @{
- */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
- * @{
- */
-#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
-#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
- * @{
- */
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
- * @{
- */
-#define ETH_FIXEDBURST_ENABLE 0x00010000U
-#define ETH_FIXEDBURST_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
- * @{
- */
-#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-/**
- * @}
- */
-
-/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
- * @{
- */
-#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
- * @{
- */
-#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
-#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
- * @{
- */
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
-#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
- * @{
- */
-#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
- * @{
- */
-#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
- * @{
- */
-#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
-/**
- * @}
- */
-
-/** @defgroup ETH_PMT_Flags ETH PMT Flags
- * @{
- */
-#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
-/**
- * @}
- */
-
-/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
- * @{
- */
-#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
-/**
- * @}
- */
-
-/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
- * @{
- */
-#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Flags ETH MAC Flags
- * @{
- */
-#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
-#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Flags ETH DMA Flags
- * @{
- */
-#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
-#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
-#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
- * @{
- */
-#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
- * @{
- */
-#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
-#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
- * @{
- */
-#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
- * @{
- */
-#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_overflow ETH DMA overflow
- * @{
- */
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
-/**
- * @}
- */
-
-/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
- * @{
- */
-#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Macros ETH Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/** @brief Reset ETH handle state
- * @param __HANDLE__ specifies the ETH handle.
- * @retval None
- */
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
-#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
- * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag of TDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag of RDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
- * @brief Enables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
-
-/**
- * @brief Disables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
-
-/**
- * @brief Set the specified DMA Rx Desc Own bit.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
-
-/**
- * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
- * @param __HANDLE__ ETH Handle
- * @retval The Transmit descriptor collision counter value.
- */
-#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
-
-/**
- * @brief Set the specified DMA Tx Desc Own bit.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
-
-/**
- * @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
-
-/**
- * @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
-
-/**
- * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__ ETH Handle
- * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
- * This parameter can be one of the following values:
- * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
- * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
-
-/**
- * @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
-
-/**
- * @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
-
-/**
- * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
-
-/**
- * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
-
-/**
- * @brief Enables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
-
-/**
- * @brief Initiate a Pause Control Frame (Full-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the ETHERNET flow control busy bit is set or not.
- * @param __HANDLE__ ETH Handle
- * @retval The new state of flow control busy status bit (SET or RESET).
- */
-#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the specified ETHERNET MAC flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- * @arg ETH_MAC_FLAG_MMC : MMC flag
- * @arg ETH_MAC_FLAG_PMT : PMT flag
- * @retval The state of ETHERNET MAC flag.
- */
-#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Enables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
- * enabled @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
- * disabled. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Clears the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __OVERFLOW__ specifies the DMA overflow flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
- * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
- * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
-
-/**
- * @brief Set the DMA Receive status watchdog timer register value
- * @param __HANDLE__ ETH Handle
- * @param __VALUE__ DMA Receive status watchdog timer register value
- * @retval None
- */
-#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
-
-/**
- * @brief Enables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
-
-/**
- * @brief Disables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
-
-/**
- * @brief Enables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Disables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Magic Packet Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
-
-/**
- * @brief Disables the MAC Magic Packet Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Power Down.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
-
-/**
- * @brief Disables the MAC Power Down.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
-
-/**
- * @brief Checks whether the specified ETHERNET PMT flag is set or not.
- * @param __HANDLE__ ETH Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
- * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
- * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
- * @retval The new state of ETHERNET PMT Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
- (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
-
-/**
- * @brief Enables the MMC Counter Freeze.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
-
-/**
- * @brief Disables the MMC Counter Freeze.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
-
-/**
- * @brief Enables the MMC Reset On Read.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
-
-/**
- * @brief Disables the MMC Reset On Read.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
-
-/**
- * @brief Enables the MMC Counter Stop Rollover.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
-
-/**
- * @brief Disables the MMC Counter Stop Rollover.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
-
-/**
- * @brief Resets the MMC Counters.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
-
-/**
- * @brief Enables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
-/**
- * @brief Disables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
-/**
- * @brief Enables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
-
-/**
- * @brief Enables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enable event on ETH External event line.
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disable event on ETH External event line
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Get flag of the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Clear flag of the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables rising edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
-/**
- * @brief Disables the rising edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
- }while(0)
-
-/**
- * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- }while(0)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup ETH_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-
-/** @addtogroup ETH_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* IO operation functions ****************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-/* Communication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-/* Callback in non blocking modes (Interrupt) */
-void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group3
- * @{
- */
-
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group4
- * @{
- */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ETH */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_ETH_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_exti.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_exti.h
deleted file mode 100644
index 6b62747335..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_exti.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_EXTI_H
-#define STM32F2xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @defgroup EXTI EXTI
- * @brief EXTI HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
- * @{
- */
-
-/**
- * @brief HAL EXTI common Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_EXTI_COMMON_CB_ID = 0x00U
-} EXTI_CallbackIDTypeDef;
-
-/**
- * @brief EXTI Handle structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< Exti line number */
- void (* PendingCallback)(void); /*!< Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
- * @brief EXTI Configuration structure definition
- */
-typedef struct
-{
- uint32_t Line; /*!< The Exti line to be configured. This parameter
- can be a value of @ref EXTI_Line */
- uint32_t Mode; /*!< The Exit Mode to be configured for a core.
- This parameter can be a combination of @ref EXTI_Mode */
- uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
- can be a value of @ref EXTI_Trigger */
- uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
- This parameter is only possible for line 0 to 15. It
- can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_Line EXTI Line
- * @{
- */
-#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
-#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
-#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
-#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
-#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
-#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
-#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
-#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
-#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
-#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
-#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
-#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
-#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
-#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
-#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
-#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
-#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
-#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Mode EXTI Mode
- * @{
- */
-#define EXTI_MODE_NONE 0x00000000u
-#define EXTI_MODE_INTERRUPT 0x00000001u
-#define EXTI_MODE_EVENT 0x00000002u
-/**
- * @}
- */
-
-/** @defgroup EXTI_Trigger EXTI Trigger
- * @{
- */
-#define EXTI_TRIGGER_NONE 0x00000000u
-#define EXTI_TRIGGER_RISING 0x00000001u
-#define EXTI_TRIGGER_FALLING 0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
- * @}
- */
-
-/** @defgroup EXTI_GPIOSel EXTI GPIOSel
- * @brief
- * @{
- */
-#define EXTI_GPIOA 0x00000000u
-#define EXTI_GPIOB 0x00000001u
-#define EXTI_GPIOC 0x00000002u
-#define EXTI_GPIOD 0x00000003u
-#define EXTI_GPIOE 0x00000004u
-#define EXTI_GPIOF 0x00000005u
-#define EXTI_GPIOG 0x00000006u
-#define EXTI_GPIOH 0x00000007u
-#define EXTI_GPIOI 0x00000008u
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
- * @{
- */
-/**
- * @brief EXTI Line property definition
- */
-#define EXTI_PROPERTY_SHIFT 24u
-#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
-
-/**
- * @brief EXTI bit usage
- */
-#define EXTI_PIN_MASK 0x0000001Fu
-
-/**
- * @brief EXTI Mask for interrupt & event mode
- */
-#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
- * @brief EXTI Mask for trigger possibilities
- */
-#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
- * @brief EXTI Line number
- */
-#define EXTI_LINE_NB 23uL
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
- * @{
- */
-#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-
-#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
- ((__PORT__) == EXTI_GPIOB) || \
- ((__PORT__) == EXTI_GPIOC) || \
- ((__PORT__) == EXTI_GPIOD) || \
- ((__PORT__) == EXTI_GPIOE) || \
- ((__PORT__) == EXTI_GPIOF) || \
- ((__PORT__) == EXTI_GPIOG) || \
- ((__PORT__) == EXTI_GPIOH) || \
- ((__PORT__) == EXTI_GPIOI))
-
-#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
- * @brief EXTI Exported Functions
- * @{
- */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
- * @brief Configuration functions
- * @{
- */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
- * @}
- */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h
deleted file mode 100644
index 5c8247dadd..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_FLASH_H
-#define __STM32F2xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0U,
- FLASH_PROC_SECTERASE,
- FLASH_PROC_MASSERASE,
- FLASH_PROC_PROGRAM
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/
-
- __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/
-
- __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/
-
- __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/
-
- __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/
-
- __IO uint32_t Address; /*Internal variable to save address selected for program*/
-
- HAL_LockTypeDef Lock; /* FLASH locking object */
-
- __IO uint32_t ErrorCode; /* FLASH error code */
-
-}FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-/** @defgroup FLASH_Error_Code FLASH Error Code
- * @brief FLASH Error Code
- * @{
- */
-#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_FLASH_ERROR_PGS 0x00000001U /*!< Programming Sequence error */
-#define HAL_FLASH_ERROR_PGP 0x00000002U /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA 0x00000004U /*!< Programming Alignment error */
-#define HAL_FLASH_ERROR_WRP 0x00000008U /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPERATION 0x00000010U /*!< Operation Error */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
- * @{
- */
-#define FLASH_TYPEPROGRAM_BYTE 0x00U /*!< Program byte (8-bit) at a specified address */
-#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!< Program a half-word (16-bit) at a specified address */
-#define FLASH_TYPEPROGRAM_WORD 0x02U /*!< Program a word (32-bit) at a specified address */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!< Program a double word (64-bit) at a specified address */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flag_definition FLASH Flag definition
- * @brief Flag definition
- * @{
- */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
-#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
-#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
- * @brief FLASH Interrupt definition
- * @{
- */
-#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
- * @{
- */
-#define FLASH_PSIZE_BYTE 0x00000000U
-#define FLASH_PSIZE_HALF_WORD 0x00000100U
-#define FLASH_PSIZE_WORD 0x00000200U
-#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U
-#define CR_PSIZE_MASK 0xFFFFFCFFU
-/**
- * @}
- */
-
-/** @defgroup FLASH_Keys FLASH Keys
- * @{
- */
-#define RDP_KEY ((uint16_t)0x00A5)
-#define FLASH_KEY1 0x45670123U
-#define FLASH_KEY2 0xCDEF89ABU
-#define FLASH_OPT_KEY1 0x08192A3BU
-#define FLASH_OPT_KEY2 0x4C5D6E7FU
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @{
- */
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__ FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @retval none
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH Latency
- * The value of this parameter depend on device used within the same series
- */
-#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
- * @brief Enable the FLASH prefetch buffer.
- * @retval none
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
-
-/**
- * @brief Disable the FLASH prefetch buffer.
- * @retval none
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
-
-/**
- * @brief Enable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN)
-
-/**
- * @brief Disable the FLASH instruction cache.
- * @retval none
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN))
-
-/**
- * @brief Enable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN)
-
-/**
- * @brief Disable the FLASH data cache.
- * @retval none
- */
-#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN))
-
-/**
- * @brief Resets the FLASH instruction Cache.
- * @note This function must be used only when the Instruction Cache is disabled.
- * @retval None
- */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \
- FLASH->ACR &= ~FLASH_ACR_ICRST; \
- }while(0U)
-
-/**
- * @brief Resets the FLASH data Cache.
- * @note This function must be used only when the data Cache is disabled.
- * @retval None
- */
-#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \
- FLASH->ACR &= ~FLASH_ACR_DCRST; \
- }while(0U)
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_ERR: Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
- * @arg FLASH_IT_ERR: Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
-
-/**
- * @brief Get the specified FLASH flag status.
- * @param __FLAG__ specifies the FLASH flags to check.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @arg FLASH_FLAG_BSY : FLASH Busy flag
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
-
-/**
- * @brief Clear the specified FLASH flags.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
- * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
- * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
- * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
- * @retval none
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
-/**
- * @}
- */
-
-/* Include FLASH HAL Extension module */
-#include "stm32f2xx_hal_flash_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-/* Program operation functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-uint32_t HAL_FLASH_GetError(void);
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
- * @{
- */
-
-/**
- * @brief ACR register byte 0 (Bits[7:0]) base address
- */
-#define ACR_BYTE0_ADDRESS 0x40023C00U
-/**
- * @brief OPTCR register byte 0 (Bits[7:0]) base address
- */
-#define OPTCR_BYTE0_ADDRESS 0x40023C14U
-/**
- * @brief OPTCR register byte 1 (Bits[15:8]) base address
- */
-#define OPTCR_BYTE1_ADDRESS 0x40023C15U
-/**
- * @brief OPTCR register byte 2 (Bits[23:16]) base address
- */
-#define OPTCR_BYTE2_ADDRESS 0x40023C16U
-/**
- * @brief OPTCR register byte 3 (Bits[31:24]) base address
- */
-#define OPTCR_BYTE3_ADDRESS 0x40023C17U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- * @{
- */
-
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
- * @{
- */
-#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
- ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h
deleted file mode 100644
index 9c0f4e950b..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_flash_ex.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of FLASH HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_FLASH_EX_H
-#define __STM32F2xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< Mass erase or sector Erase.
- This parameter can be a value of @ref FLASHEx_Type_Erase */
-
- uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
- This parameter must be a value of @ref FLASHEx_Sectors */
-
- uint32_t NbSectors; /*!< Number of sectors to be erased.
- This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
- uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
- This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Option Bytes Program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< Option byte to be configured.
- This parameter can be a value of @ref FLASHEx_Option_Type */
-
- uint32_t WRPState; /*!< Write protection activation or deactivation.
- This parameter can be a value of @ref FLASHEx_WRP_State */
-
- uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
- The value of this parameter depend on device used within the same series */
-
- uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint32_t RDPLevel; /*!< Set the read protection level.
- This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
- uint32_t BORLevel; /*!< Set the BOR Level.
- This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
-
- uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
-
-} FLASH_OBProgramInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
- * @{
- */
-#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */
-#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
- * @{
- */
-#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */
-#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */
-#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */
-#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_WRP_State FLASH WRP State
- * @{
- */
-#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Type FLASH Option Type
- * @{
- */
-#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
-#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
-#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
- * @{
- */
-#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
-#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
-#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
- it s no more possible to go back to level 1 or 0 */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
- * @{
- */
-#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
- * @{
- */
-#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
- * @{
- */
-#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Latency FLASH Latency
- * @{
- */
-#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
-#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
-#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
-#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
-#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
-#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
-
-/**
- * @}
- */
-
-
-/** @defgroup FLASHEx_Banks FLASH Banks
- * @{
- */
-#define FLASH_BANK_1 1U /*!< Bank 1 */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
- * @{
- */
-#define FLASH_MER_BIT FLASH_CR_MER /*!< only 1 MER Bit */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Sectors FLASH Sectors
- * @{
- */
-#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
-#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
-#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
-#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
-#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
-#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
-#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
-#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
-#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
-#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
-#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
-#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
-
-
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
- * @{
- */
-#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */
-#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */
-#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */
-#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */
-#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */
-#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */
-#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */
-#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */
-#define OB_WRP_SECTOR_8 0x00000100U /*!< Write protection of Sector8 */
-#define OB_WRP_SECTOR_9 0x00000200U /*!< Write protection of Sector9 */
-#define OB_WRP_SECTOR_10 0x00000400U /*!< Write protection of Sector10 */
-#define OB_WRP_SECTOR_11 0x00000800U /*!< Write protection of Sector11 */
-#define OB_WRP_SECTOR_All 0x00000FFFU /*!< Write protection of all Sectors */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-/* Extension Program operation functions *************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Variables FLASH Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
- * @{
- */
-
-#define FLASH_SECTOR_TOTAL 12U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
- * @{
- */
-
-/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
- ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
- ((RANGE) == FLASH_VOLTAGE_RANGE_4))
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
- ((VALUE) == OB_WRPSTATE_ENABLE))
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1) ||\
- ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
- ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1) || \
- ((LATENCY) == FLASH_LATENCY_2) || \
- ((LATENCY) == FLASH_LATENCY_3) || \
- ((LATENCY) == FLASH_LATENCY_4) || \
- ((LATENCY) == FLASH_LATENCY_5) || \
- ((LATENCY) == FLASH_LATENCY_6) || \
- ((LATENCY) == FLASH_LATENCY_7))
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
- ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
- ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
- ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
- ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
- ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11))
-
-
-
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
- (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
- * @{
- */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
-void FLASH_FlushCaches(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h
deleted file mode 100644
index 1623fbc1b7..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_GPIO_H
-#define __STM32F2xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode_define */
-
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
- This parameter can be a value of @ref GPIO_pull_define */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed_define */
-
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
- This parameter can be a value of @ref GPIO_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- GPIO_PIN_RESET = 0U,
- GPIO_PIN_SET
-}GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define GPIO pins define
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode_define GPIO mode define
- * @brief GPIO Configuration Mode
- * Elements values convention: 0x00WX00YZ
- * - W : EXTI trigger detection on 3 bits
- * - X : EXTI mode (IT or Event) on 2 bits
- * - Y : Output type (Push Pull or Open Drain) on 1 bit
- * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
- * @{
- */
-#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed_define GPIO speed define
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */
-/**
- * @}
- */
-
- /** @defgroup GPIO_pull_define GPIO pull define
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
-#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__ specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param __EXTI_LINE__ specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__ specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f2xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-#define GPIO_MODE_Pos 0U
-#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
-#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
-#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
-#define MODE_AF (0x2UL << GPIO_MODE_Pos)
-#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos 4U
-#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos 16U
-#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
-#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
-#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos 20U
-#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h
deleted file mode 100644
index 4e4f401c38..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_gpio_ex.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_GPIO_EX_H
-#define __STM32F2xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_Alternate_function_selection GPIO Alternate function selection
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
-#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
-#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
-#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
-#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
-#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */
-
-/**
- * @brief AF 11 selection
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
-#endif /* STM32F207xx || STM32F217xx */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */
-#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */
-
-/**
- * @brief AF 13 selection
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-#endif /* STM32F207xx || STM32F217xx */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
- * @{
- */
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
- * @{
- */
-/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
- * @{
- */
-#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :\
- ((__GPIOx__) == (GPIOG))? 6U :\
- ((__GPIOx__) == (GPIOH))? 7U :\
- ((__GPIOx__) == (GPIOI))? 8U : 9U)
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
- ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \
- ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
-#else /* STM32F207xx || STM32F217xx */
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
- ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
- ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
- ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
- ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
- ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
- ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \
- ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \
- ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
- ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \
- ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \
- ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
- ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \
- ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \
- ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT))
-#endif /* STM32F207xx || STM32F217xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h
deleted file mode 100644
index ab971d8727..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hash.h
+++ /dev/null
@@ -1,590 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_hash.h
- * @author MCD Application Team
- * @brief Header file of HASH HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_HASH_H
-#define STM32F2xx_HAL_HASH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-#if defined (HASH)
-/** @addtogroup HASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HASH_Exported_Types HASH Exported Types
- * @{
- */
-
-/**
- * @brief HASH Configuration Structure definition
- */
-typedef struct
-{
- uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
- This parameter can be a value of @ref HASH_Data_Type. */
-
- uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
-
- uint8_t *pKey; /*!< The key is used only in HMAC operation. */
-
-} HASH_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
- HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */
- HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
- HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */
- HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */
-} HAL_HASH_StateTypeDef;
-
-/**
- * @brief HAL phase structures definition
- */
-typedef enum
-{
- HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */
- HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */
- HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase
- (step 1 consists in entering the inner hash function key) */
- HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase
- (step 2 consists in entering the message text) */
- HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase
- (step 3 consists in entering the outer hash function key) */
-} HAL_HASH_PhaseTypeDef;
-
-/**
- * @brief HAL HASH mode suspend definitions
- */
-typedef enum
-{
- HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */
- HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */
-} HAL_HASH_SuspendTypeDef;
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL HASH common Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
- HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
- HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
- HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
- HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
-} HAL_HASH_CallbackIDTypeDef;
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-
-/**
- * @brief HASH Handle Structure definition
- */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-typedef struct __HASH_HandleTypeDef
-#else
-typedef struct
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
-{
- HASH_InitTypeDef Init; /*!< HASH required parameters */
-
- uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
-
- uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
-
- uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
-
- uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
-
- uint32_t HashBuffSize; /*!< Size of buffer to be processed */
-
- __IO uint32_t HashInCount; /*!< Counter of inputted data */
-
- __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
-
- __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
-
- HAL_StatusTypeDef Status; /*!< HASH peripheral status */
-
- HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
-
- DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
-
- HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
-
- FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
-
- __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
-
- __IO uint32_t ErrorCode; /*!< HASH Error code */
-
- __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
- void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */
-
- void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */
-
- void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */
-
- void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */
-
- void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */
-
-#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
-} HASH_HandleTypeDef;
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL HASH Callback pointer definition
- */
-typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants HASH Exported Constants
- * @{
- */
-
-/** @defgroup HASH_Algo_Selection HASH algorithm selection
- * @{
- */
-#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
-#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
-/**
- * @}
- */
-
-/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
- * @{
- */
-#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
-#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
-/**
- * @}
- */
-
-/** @defgroup HASH_Data_Type HASH input data type
- * @{
- */
-#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
-#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
-#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
-#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
-/**
- * @}
- */
-
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
- * @{
- */
-#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */
-#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
-/**
- * @}
- */
-
-/** @defgroup HASH_flags_definition HASH flags definitions
- * @{
- */
-#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
-#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
-#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
-#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
-#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
-
-/**
- * @}
- */
-
-/** @defgroup HASH_interrupts_definition HASH interrupts definitions
- * @{
- */
-#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
-
-/**
- * @}
- */
-
-/** @defgroup HASH_Error_Definition HASH Error Definition
- * @{
- */
-#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */
-#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
-#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HASH_Exported_Macros HASH Exported Macros
- * @{
- */
-
-/** @brief Check whether or not the specified HASH flag is set.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
- * @arg @ref HASH_FLAG_DCIS Digest calculation complete.
- * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
- * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
- * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
- ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
- ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
-
-
-/** @brief Clear the specified HASH flag.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
- * @arg @ref HASH_FLAG_DCIS Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
-
-
-/** @brief Enable the specified HASH interrupt.
- * @param __INTERRUPT__ specifies the HASH interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
- * @arg @ref HASH_IT_DCI Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief Disable the specified HASH interrupt.
- * @param __INTERRUPT__ specifies the HASH interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
- * @arg @ref HASH_IT_DCI Digest calculation complete
- * @retval None
- */
-#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
-
-/** @brief Reset HASH handle state.
- * @param __HANDLE__ HASH handle.
- * @retval None
- */
-
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_HASH_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- }while(0)
-#else
-#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-
-/** @brief Reset HASH handle status.
- * @param __HANDLE__ HASH handle.
- * @retval None
- */
-#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
-
-
-/**
- * @brief Start the digest computation.
- * @retval None
- */
-#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
-
-/**
- * @brief Set the number of valid bits in the last word written in data register DIN.
- * @param __SIZE__ size in bytes of last data written in Data register.
- * @retval None
- */
-#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
-
-/**
- * @brief Reset the HASH core.
- * @retval None
- */
-#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
-
-/**
- * @}
- */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup HASH_Private_Macros HASH Private Macros
- * @{
- */
-#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : 16)
-/**
- * @brief Return number of words already pushed in the FIFO.
- * @retval Number of words already pushed in the FIFO
- */
-#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)
-
-/**
- * @brief Ensure that HASH input data type is valid.
- * @param __DATATYPE__ HASH input data type.
- * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
- */
-#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
- ((__DATATYPE__) == HASH_DATATYPE_8B) || \
- ((__DATATYPE__) == HASH_DATATYPE_1B))
-
-/**
- * @brief Ensure that handle phase is set to HASH processing.
- * @param __HANDLE__ HASH handle.
- * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
- */
-#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
-
-/**
- * @brief Ensure that handle phase is set to HMAC processing.
- * @param __HANDLE__ HASH handle.
- * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
- */
-#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
- ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
- ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HASH_Exported_Functions HASH Exported Functions
- * @{
- */
-
-/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization methods **********************************/
-HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
-void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
- pHASH_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
-
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- * @{
- */
-
-
-/* HASH processing using polling *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer, uint32_t Timeout);
-
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- * @{
- */
-
-/* HASH processing using IT **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- * @{
- */
-
-/* HASH processing using DMA *************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- * @{
- */
-
-/* HASH-MAC processing using polling *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- * @{
- */
-
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
- uint8_t *pOutBuffer);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- * @{
- */
-
-/* HASH-HMAC processing using DMA ********************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
- * @{
- */
-
-
-/* Peripheral State methods **************************************************/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
-void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions -----------------------------------------------------------*/
-
-/** @addtogroup HASH_Private_Functions HASH Private Functions
- * @{
- */
-
-/* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
- uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* HASH*/
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_HASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h
deleted file mode 100644
index 99f542cbba..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_hcd.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_hcd.h
- * @author MCD Application Team
- * @brief Header file of HCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_HCD_H
-#define STM32F2xx_HAL_HCD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_usb.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HCD HCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Types HCD Exported Types
- * @{
- */
-
-/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
- * @{
- */
-typedef enum
-{
- HAL_HCD_STATE_RESET = 0x00,
- HAL_HCD_STATE_READY = 0x01,
- HAL_HCD_STATE_ERROR = 0x02,
- HAL_HCD_STATE_BUSY = 0x03,
- HAL_HCD_STATE_TIMEOUT = 0x04
-} HCD_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
-typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
-typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
- * @{
- */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-typedef struct __HCD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-{
- HCD_TypeDef *Instance; /*!< Register base address */
- HCD_InitTypeDef Init; /*!< HCD required parameters */
- HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
- HAL_LockTypeDef Lock; /*!< HCD peripheral status */
- __IO HCD_StateTypeDef State; /*!< HCD communication state */
- __IO uint32_t ErrorCode; /*!< HCD Error code */
- void *pData; /*!< Pointer Stack Handler */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
- void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
- void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
- void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
- void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
- void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
- void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
- HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
-
- void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
- void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-} HCD_HandleTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants HCD Exported Constants
- * @{
- */
-
-/** @defgroup HCD_Speed HCD Speed
- * @{
- */
-#define HCD_SPEED_HIGH USBH_HS_SPEED
-#define HCD_SPEED_FULL USBH_FSLS_SPEED
-#define HCD_SPEED_LOW USBH_FSLS_SPEED
-/**
- * @}
- */
-
-/** @defgroup HCD_Device_Speed HCD Device Speed
- * @{
- */
-#define HCD_DEVICE_SPEED_HIGH 0U
-#define HCD_DEVICE_SPEED_FULL 1U
-#define HCD_DEVICE_SPEED_LOW 2U
-/**
- * @}
- */
-
-/** @defgroup HCD_PHY_Module HCD PHY Module
- * @{
- */
-#define HCD_PHY_ULPI 1U
-#define HCD_PHY_EMBEDDED 2U
-/**
- * @}
- */
-
-/** @defgroup HCD_Error_Code_definition HCD Error Code definition
- * @brief HCD Error Code definition
- * @{
- */
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
- & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions HCD Exported Functions
- * @{
- */
-
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
- uint8_t epnum, uint8_t dev_address,
- uint8_t speed, uint8_t ep_type, uint16_t mps);
-
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
- * @brief HAL USB OTG HCD Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
- HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
- HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
- HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
- HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
-
- HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
- HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
-
-} HAL_HCD_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
- * @brief HAL USB OTG HCD Callback pointer definition
- * @{
- */
-
-typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
-typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
- uint8_t epnum,
- HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
-/**
- * @}
- */
-
-HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
- HAL_HCD_CallbackIDTypeDef CallbackID,
- pHCD_CallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
- HAL_HCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
- pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
- uint8_t direction, uint8_t ep_type,
- uint8_t token, uint8_t *pbuff,
- uint16_t length, uint8_t do_ping);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Private functions prototypes ----------------------------------------------*/
-
-/**
- * @}
- */
-/**
- * @}
- */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h
deleted file mode 100644
index e8b0a07001..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2c.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_I2C_H
-#define __STM32F2xx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
- * @{
- */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
- * @brief I2C Configuration Structure definition
- * @{
- */
-typedef struct
-{
- uint32_t ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_addressing_mode */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_dual_addressing_mode */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_nostretch_mode */
-
-} I2C_InitTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
- * @brief HAL State structure definition
- * @note HAL I2C State value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : Abort (Abort user request on going)
- * 10 : Timeout
- * 11 : Error
- * b5 Peripheral initialization status
- * 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)
- * b4 (not used)
- * x : Should be set to 0
- * b3
- * 0 : Ready or Busy (No Listen mode ongoing)
- * 1 : Listen (Peripheral in Address Listen Mode)
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (Peripheral busy with some configuration or internal operations)
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * @{
- */
-typedef enum
-{
- HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
- HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
- HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
- HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-
-} HAL_I2C_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
- * @brief HAL Mode structure definition
- * @note HAL I2C Mode value coding follow below described bitmap :\n
- * b7 (not used)\n
- * x : Should be set to 0\n
- * b6\n
- * 0 : None\n
- * 1 : Memory (HAL I2C communication is in Memory Mode)\n
- * b5\n
- * 0 : None\n
- * 1 : Slave (HAL I2C communication is in Slave Mode)\n
- * b4\n
- * 0 : None\n
- * 1 : Master (HAL I2C communication is in Master Mode)\n
- * b3-b2-b1-b0 (not used)\n
- * xxxx : Should be set to 0000
- * @{
- */
-typedef enum
-{
- HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
- * @brief I2C Error Code definition
- * @{
- */
-#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
-#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
-#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
-#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
-#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
-#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
- * @brief I2C handle Structure definition
- * @{
- */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-typedef struct __I2C_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- __IO uint32_t XferOptions; /*!< I2C transfer options */
-
- __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
- context for internal usage */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
- __IO uint32_t Devaddress; /*!< I2C Target device address */
-
- __IO uint32_t Memaddress; /*!< I2C Target memory address */
-
- __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
-
- __IO uint32_t EventCount; /*!< I2C Event counter */
-
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
- void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
- void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
- void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
- void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
- void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
- void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
- void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
- void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
- void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
-
- void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
-
- void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
- void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL I2C Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
- HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
- HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
- HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
- HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
- HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
- HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
- HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
- HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
-
- HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
- HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
-
-} HAL_I2C_CallbackIDTypeDef;
-
-/**
- * @brief HAL I2C Callback pointer definition
- */
-typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
- * @{
- */
-#define I2C_DUTYCYCLE_2 0x00000000U
-#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
-/**
- * @}
- */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
-#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
- * @{
- */
-#define I2C_DUALADDRESS_DISABLE 0x00000000U
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
-/**
- * @}
- */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
- * @{
- */
-#define I2C_GENERALCALL_DISABLE 0x00000000U
-#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
-/**
- * @}
- */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
- * @{
- */
-#define I2C_NOSTRETCH_DISABLE 0x00000000U
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
- * @{
- */
-#define I2C_MEMADD_SIZE_8BIT 0x00000001U
-#define I2C_MEMADD_SIZE_16BIT 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
- * @{
- */
-#define I2C_DIRECTION_RECEIVE 0x00000000U
-#define I2C_DIRECTION_TRANSMIT 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
- * @{
- */
-#define I2C_FIRST_FRAME 0x00000001U
-#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U
-#define I2C_NEXT_FRAME 0x00000004U
-#define I2C_FIRST_AND_LAST_FRAME 0x00000008U
-#define I2C_LAST_FRAME_NO_STOP 0x00000010U
-#define I2C_LAST_FRAME 0x00000020U
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define I2C_OTHER_FRAME (0x00AA0000U)
-#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
- * @brief I2C Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
- * @{
- */
-#define I2C_IT_BUF I2C_CR2_ITBUFEN
-#define I2C_IT_EVT I2C_CR2_ITEVTEN
-#define I2C_IT_ERR I2C_CR2_ITERREN
-/**
- * @}
- */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
- * @{
- */
-
-#define I2C_FLAG_OVR 0x00010800U
-#define I2C_FLAG_AF 0x00010400U
-#define I2C_FLAG_ARLO 0x00010200U
-#define I2C_FLAG_BERR 0x00010100U
-#define I2C_FLAG_TXE 0x00010080U
-#define I2C_FLAG_RXNE 0x00010040U
-#define I2C_FLAG_STOPF 0x00010010U
-#define I2C_FLAG_ADD10 0x00010008U
-#define I2C_FLAG_BTF 0x00010004U
-#define I2C_FLAG_ADDR 0x00010002U
-#define I2C_FLAG_SB 0x00010001U
-#define I2C_FLAG_DUALF 0x00100080U
-#define I2C_FLAG_GENCALL 0x00100010U
-#define I2C_FLAG_TRA 0x00100004U
-#define I2C_FLAG_BUSY 0x00100002U
-#define I2C_FLAG_MSL 0x00100001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @brief Reset I2C handle state.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
-
-/** @brief Enable or disable the specified I2C interrupts.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt enable
- * @arg I2C_IT_EVT: Event interrupt enable
- * @arg I2C_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__ specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt enable
- * @arg I2C_IT_EVT: Event interrupt enable
- * @arg I2C_IT_ERR: Error interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2C flag is set or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag
- * @arg I2C_FLAG_RXNE: Data register not empty flag
- * @arg I2C_FLAG_STOPF: Stop detection flag
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag
- * Address matched flag
- * @arg I2C_FLAG_SB: Start bit flag
- * @arg I2C_FLAG_DUALF: Dual flag
- * @arg I2C_FLAG_GENCALL: General call header flag
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \
- (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \
- (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))
-
-/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @retval None
- */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
-
-/** @brief Clears the I2C ADDR pending flag.
- * @param __HANDLE__ specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- tmpreg = (__HANDLE__)->Instance->SR2; \
- UNUSED(tmpreg); \
- } while(0)
-
-/** @brief Clears the I2C STOPF pending flag.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \
- UNUSED(tmpreg); \
- } while(0)
-
-/** @brief Enable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/** @brief Disable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* IO operation functions ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-/**
- * @}
- */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @{
- */
-/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-#define I2C_FLAG_MASK 0x0000FFFFU
-#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
-#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macros I2C Private Macros
- * @{
- */
-
-#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
-#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
-#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
-
-/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
- * @{
- */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
- ((CYCLE) == I2C_DUTYCYCLE_16_9))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
- ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
- ((REQUEST) == I2C_NEXT_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
- IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
- ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F2xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h
deleted file mode 100644
index 79b62cd216..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_i2s.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_i2s.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_I2S_H
-#define STM32F2xx_HAL_I2S_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2S
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-
- uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
- This parameter can be a value of @ref I2S_Clock_Source */
-} I2S_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-} HAL_I2S_StateTypeDef;
-
-/**
- * @brief I2S handle Structure definition
- */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
-typedef struct __I2S_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-{
- SPI_TypeDef *Instance; /*!< I2S registers base address */
-
- I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
- DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
-
- __IO uint32_t ErrorCode; /*!< I2S Error code
- This parameter can be a value of @ref I2S_Error */
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
- void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
- void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
- void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
- void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
- void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
- void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
-
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-} I2S_HandleTypeDef;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL I2S Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
- HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
- HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
- HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
- HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
- HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
- HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
-
-} HAL_I2S_CallbackIDTypeDef;
-
-/**
- * @brief HAL I2S Callback pointer definition
- */
-typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
-
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
- * @{
- */
-/** @defgroup I2S_Error I2S Error
- * @{
- */
-#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
-#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
-#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode I2S Mode
- * @{
- */
-#define I2S_MODE_SLAVE_TX (0x00000000U)
-#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard I2S Standard
- * @{
- */
-#define I2S_STANDARD_PHILIPS (0x00000000U)
-#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format I2S Data Format
- * @{
- */
-#define I2S_DATAFORMAT_16B (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
- * @{
- */
-#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
- * @{
- */
-#define I2S_AUDIOFREQ_192K (192000U)
-#define I2S_AUDIOFREQ_96K (96000U)
-#define I2S_AUDIOFREQ_48K (48000U)
-#define I2S_AUDIOFREQ_44K (44100U)
-#define I2S_AUDIOFREQ_32K (32000U)
-#define I2S_AUDIOFREQ_22K (22050U)
-#define I2S_AUDIOFREQ_16K (16000U)
-#define I2S_AUDIOFREQ_11K (11025U)
-#define I2S_AUDIOFREQ_8K (8000U)
-#define I2S_AUDIOFREQ_DEFAULT (2U)
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
- * @{
- */
-#define I2S_CPOL_LOW (0x00000000U)
-#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
-/**
- * @}
- */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
- * @{
- */
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
- * @{
- */
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
-
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
-
-#define I2S_FLAG_MASK (SPI_SR_RXNE\
- | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Source I2S Clock Source
- * @{
- */
-#define I2S_CLOCK_PLL 0x00000000U
-#define I2S_CLOCK_EXTERNAL 0x00000001U
-/**
- * @}
- */
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
- * @{
- */
-
-/** @brief Reset I2S handle state
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-/** @brief Enable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief Disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief Enable the specified I2S interrupts.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief Disable the specified I2S interrupts.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
- * @param __HANDLE__ specifies the I2S Handle.
- * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__ specifies the I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
- & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2S flag is set or not.
- * @param __HANDLE__ specifies the I2S Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
- * @arg I2S_FLAG_TXE: Transmit buffer empty flag
- * @arg I2S_FLAG_UDR: Underrun flag
- * @arg I2S_FLAG_OVR: Overrun flag
- * @arg I2S_FLAG_FRE: Frame error flag
- * @arg I2S_FLAG_CHSIDE: Channel Side flag
- * @arg I2S_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- }while(0U)
-/** @brief Clears the I2S UDR pending flag.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg_udr = 0x00U;\
- tmpreg_udr = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg_udr); \
- }while(0U)
-/** @brief Flush the I2S DR Register.
- * @param __HANDLE__ specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
- __IO uint32_t tmpreg_dr = 0x00U;\
- tmpreg_dr = ((__HANDLE__)->Instance->DR);\
- UNUSED(tmpreg_dr); \
- }while(0U)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
- pI2S_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
- * @{
- */
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of I2S SR register.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
- * @arg I2S_FLAG_TXE: Transmit buffer empty flag
- * @arg I2S_FLAG_UDR: Underrun error flag
- * @arg I2S_FLAG_OVR: Overrun flag
- * @arg I2S_FLAG_CHSIDE: Channel side flag
- * @arg I2S_FLAG_BSY: Busy flag
- * @retval SET or RESET.
- */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
- & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of I2S CR2 register.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval SET or RESET.
- */
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
- & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if I2S Mode parameter is in allowed range.
- * @param __MODE__ specifies the I2S Mode.
- * This parameter can be a value of @ref I2S_Mode
- * @retval None
- */
-#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
- ((__MODE__) == I2S_MODE_SLAVE_RX) || \
- ((__MODE__) == I2S_MODE_MASTER_TX) || \
- ((__MODE__) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
- ((__STANDARD__) == I2S_STANDARD_MSB) || \
- ((__STANDARD__) == I2S_STANDARD_LSB) || \
- ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
- ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
- ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
- ((__FORMAT__) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
- ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
- ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
- ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
-
-/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
- * @param __CPOL__ specifies the I2S serial clock steady state.
- * This parameter can be a value of @ref I2S_Clock_Polarity
- * @retval None
- */
-#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
- ((__CPOL__) == I2S_CPOL_HIGH))
-
-#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
- ((CLOCK) == I2S_CLOCK_PLL))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h
deleted file mode 100644
index 75b0db4bb3..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_irda.h
+++ /dev/null
@@ -1,684 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_irda.h
- * @author MCD Application Team
- * @brief Header file of IRDA HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_IRDA_H
-#define __STM32F2xx_HAL_IRDA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
- * @{
- */
-/**
- * @brief IRDA Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref IRDA_Word_Length */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref IRDA_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Mode */
-
- uint8_t Prescaler; /*!< Specifies the Prescaler value to be programmed
- in the IrDA low-power Baud Register, for defining pulse width on which
- burst acceptance/rejection will be decided. This value is used as divisor
- of system clock to achieve required pulse width. */
-
- uint32_t IrDAMode; /*!< Specifies the IrDA mode
- This parameter can be a value of @ref IRDA_Low_Power */
-} IRDA_InitTypeDef;
-
-/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
- * - gState contains IRDA state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initialisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL IRDA Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initialisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-} HAL_IRDA_StateTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
- */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-typedef struct __IRDA_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< IRDA Error code */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
- void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
-
- void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
-
- void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
-
- void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
-
- void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
-
- void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
-
- void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
-
- void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
-
-
- void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
-
- void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-} IRDA_HandleTypeDef;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL IRDA Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
- HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
- HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
- HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
- HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
- HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
- HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
- HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
-
- HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
- HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
-
-} HAL_IRDA_CallbackIDTypeDef;
-
-/**
- * @brief HAL IRDA Callback pointer definition
- */
-typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
-
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
- * @{
- */
-/** @defgroup IRDA_Error_Code IRDA Error Code
- * @{
- */
-#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
- * @{
- */
-#define IRDA_WORDLENGTH_8B 0x00000000U
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup IRDA_Parity IRDA Parity
- * @{
- */
-#define IRDA_PARITY_NONE 0x00000000U
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup IRDA_Mode IRDA Transfer Mode
- * @{
- */
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
- * @{
- */
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup IRDA_Flags IRDA Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * @{
- */
-#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
- * @{
- */
-
-/** @brief Reset IRDA handle gstate & RxState
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0U)
-#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/** @brief Flush the IRDA DR register
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Check whether the specified IRDA flag is set or not.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IRDA_FLAG_TXE: Transmit data register empty flag
- * @arg IRDA_FLAG_TC: Transmission Complete flag
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
- * @arg IRDA_FLAG_IDLE: Idle Line detection flag
- * @arg IRDA_FLAG_ORE: OverRun Error flag
- * @arg IRDA_FLAG_NE: Noise Error flag
- * @arg IRDA_FLAG_FE: Framing Error flag
- * @arg IRDA_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified IRDA pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg IRDA_FLAG_TC: Transmission Complete flag.
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified IRDA interrupt.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-/** @brief Disable the specified IRDA interrupt.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief Check whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __IT__ specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ERR: Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
-
-/** @brief Macro to enable the IRDA's one bit sample method
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
-
-/** @brief Macro to disable the IRDA's one bit sample method
- * @param __HANDLE__ specifies the IRDA Handle.
- * @retval None
- */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART/USART associated to IRDA Handle
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief Disable UART/USART associated to IRDA Handle
- * @param __HANDLE__ specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions
- * @{
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
- * @{
- */
-
-/** @brief IRDA interruptions flag mask
- *
- */
-#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-#define IRDA_CR1_REG_INDEX 1U
-#define IRDA_CR2_REG_INDEX 2U
-#define IRDA_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
- * @{
- */
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
-
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
-
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
-
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-
-#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) ((((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
-
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h
deleted file mode 100644
index c1ccaf1153..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_iwdg.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_IWDG_H
-#define STM32F2xx_HAL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @defgroup IWDG IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
- * @{
- */
-
-/**
- * @brief IWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
- This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
- * @brief IWDG Handle Structure definition
- */
-typedef struct
-{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
- IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-} IWDG_HandleTypeDef;
-
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
- * @{
- */
-#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the IWDG peripheral.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
- * @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
- * @{
- */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
- * @{
- */
-/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
- * @{
- */
-
-/**
- * @brief IWDG Key Register BitMask
- */
-#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
- * @{
- */
-
-/**
- * @brief Enable write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
- * @brief Disable write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
- * @brief Check IWDG prescaler value.
- * @param __PRESCALER__ IWDG prescaler value
- * @retval None
- */
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
- * @brief Check IWDG reload value.
- * @param __RELOAD__ IWDG reload value
- * @retval None
- */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
-
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_mmc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_mmc.h
deleted file mode 100644
index 111bc18b1f..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_mmc.h
+++ /dev/null
@@ -1,745 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_mmc.h
- * @author MCD Application Team
- * @brief Header file of MMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_MMC_H
-#define STM32F2xx_HAL_MMC_H
-
-#if defined(SDIO)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup MMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_Types MMC Exported Types
- * @{
- */
-
-/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
- HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
- HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
- HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
- HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
- HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */
- HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
- * @{
- */
-typedef uint32_t HAL_MMC_CardStateTypeDef;
-
-#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */
-#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
-#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
-#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
-#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
-#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
-#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
-#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
-#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
- * @{
- */
-#define MMC_InitTypeDef SDIO_InitTypeDef
-#define MMC_TypeDef SDIO_TypeDef
-
-/**
- * @brief MMC Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_MMC_CardInfoTypeDef;
-
-/**
- * @brief MMC handle Structure definition
- */
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-typedef struct __MMC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
-{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
-
- MMC_InitTypeDef Init; /*!< MMC required parameters */
-
- HAL_LockTypeDef Lock; /*!< MMC locking object */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< MMC Tx Transfer size */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< MMC Rx Transfer size */
-
- __IO uint32_t Context; /*!< MMC transfer context */
-
- __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
-
- __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
-
- DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
-
- HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
- uint32_t CSD[4U]; /*!< MMC card specific data table */
-
- uint32_t CID[4U]; /*!< MMC card identification number table */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
-
- void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc);
- void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc);
-#endif
-}MMC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGroup; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_MMC_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_MMC_CardCIDTypeDef;
-/**
- * @}
- */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */
- HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */
- HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */
- HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */
-
- HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */
- HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */
-}HAL_MMC_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition
- * @{
- */
-typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-#endif
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Constants Exported Constants
- * @{
- */
-
-#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
- * @{
- */
-#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
- * @{
- */
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
- * @{
- */
-/**
- * @brief
- */
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
-#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
- * @{
- */
-#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */
-#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset MMC handle state.
- * @param __HANDLE__ : MMC handle.
- * @retval None
- */
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_MMC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET)
-#endif
-
-/**
- * @brief Enable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval The new state of MMC FLAG (SET or RESET).
- */
-#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the MMC's pending flags.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval None
- */
-#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of MMC IT (SET or RESET).
- */
-#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Functions MMC Exported Functions
- * @{
- */
-
-/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
-
-#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
-/* MMC callback registering/unregistering */
-HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);
-#endif
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
- * @{
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MMC_Private_Types MMC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup MMC_Private_Defines MMC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Variables MMC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Constants MMC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MMC_Private_Macros MMC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SDIO */
-
-#endif /* STM32F2xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h
deleted file mode 100644
index 14a468d8a2..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nand.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_nand.h
- * @author MCD Application Team
- * @brief Header file of NAND HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_NAND_H
-#define STM32F2xx_HAL_NAND_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NAND
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
- * @{
- */
-
-/**
- * @brief HAL NAND State structures definition
- */
-typedef enum
-{
- HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-} HAL_NAND_StateTypeDef;
-
-/**
- * @brief NAND Memory electronic signature Structure definition
- */
-typedef struct
-{
- /*State = HAL_NAND_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
- FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* IO operation functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
-/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
- pNAND_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NAND_Private_Constants NAND Private Constants
- * @{
- */
-#define NAND_DEVICE1 0x70000000UL
-#define NAND_DEVICE2 0x80000000UL
-#define NAND_WRITE_TIMEOUT 0x01000000UL
-
-#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
-#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS 0x00000100UL
-#define NAND_INVALID_ADDRESS 0x00000200UL
-#define NAND_TIMEOUT_ERROR 0x00000400UL
-#define NAND_BUSY 0x00000000UL
-#define NAND_ERROR 0x00000001UL
-#define NAND_READY 0x00000040UL
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NAND_Private_Macros NAND Private Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__ NAND memory address.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + \
- (((__ADDRESS__)->Plane) * \
- ((__HANDLE__)->Config.PlaneSize))) * \
- ((__HANDLE__)->Config.BlockSize)))
-
-/**
- * @brief NAND memory Column address computation.
- * @param __HANDLE__ NAND handle.
- * @retval NAND Raw address value
- */
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/**
- * @brief NAND memory Columns cycling.
- * @param __ADDRESS__ NAND memory address.
- * @retval NAND Column address cycling value.
- */
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h
deleted file mode 100644
index e52c8c1b57..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_nor.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_nor.h
- * @author MCD Application Team
- * @brief Header file of NOR HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_NOR_H
-#define STM32F2xx_HAL_NOR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup NOR
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup NOR_Exported_Types NOR Exported Types
- * @{
- */
-
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
-} HAL_NOR_StateTypeDef;
-
-/**
- * @brief FSMC NOR Status typedef
- */
-typedef enum
-{
- HAL_NOR_STATUS_SUCCESS = 0U,
- HAL_NOR_STATUS_ONGOING,
- HAL_NOR_STATUS_ERROR,
- HAL_NOR_STATUS_TIMEOUT
-} HAL_NOR_StatusTypeDef;
-
-/**
- * @brief FSMC NOR ID typedef
- */
-typedef struct
-{
- uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
- These codes can be accessed by performing read operations with specific
- control signals and addresses set.They can also be accessed by issuing
- an Auto Select command */
-} NOR_IDTypeDef;
-
-/**
- * @brief FSMC NOR CFI typedef
- */
-typedef struct
-{
- /*!< Defines the information stored in the memory's Common flash interface
- which contains a description of various electrical and timing parameters,
- density information and functions supported by the memory */
-
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4;
-} NOR_CFITypeDef;
-
-/**
- * @brief NOR handle Structure definition
- */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-typedef struct __NOR_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-
-{
- FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
- __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
- uint32_t CommandSet; /*!< NOR algorithm command set and control */
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
- void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-} NOR_HandleTypeDef;
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL NOR Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
- HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
-} HAL_NOR_CallbackIDTypeDef;
-
-/**
- * @brief HAL NOR Callback pointer definition
- */
-typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup NOR_Exported_Macros NOR Exported Macros
- * @{
- */
-/** @brief Reset NOR handle state
- * @param __HANDLE__ specifies the NOR handle.
- * @retval None
- */
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_NOR_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
- FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
- uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
- uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
-/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
- pNOR_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
- * @{
- */
-
-/* NOR Control functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
- * @{
- */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
- * @{
- */
-/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x0061)
-#define CFI2_ADDRESS ((uint16_t)0x0062)
-#define CFI3_ADDRESS ((uint16_t)0x0063)
-#define CFI4_ADDRESS ((uint16_t)0x0064)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT ((uint16_t)0xFFFF)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x00)
-#define NOR_MEMORY_16B ((uint8_t)0x01)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 (0x60000000U)
-#define NOR_MEMORY_ADRESS2 (0x64000000U)
-#define NOR_MEMORY_ADRESS3 (0x68000000U)
-#define NOR_MEMORY_ADRESS4 (0x6C000000U)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Macros NOR Private Macros
- * @{
- */
-/**
- * @brief NOR memory address shifting.
- * @param __NOR_ADDRESS NOR base address
- * @param __NOR_MEMORY_WIDTH_ NOR memory width
- * @param __ADDRESS__ NOR memory address
- * @retval NOR shifted address value
- */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
- ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
- * @brief NOR memory write data to specified address.
- * @param __ADDRESS__ NOR memory address
- * @param __DATA__ Data to write
- * @retval None
- */
-#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
- (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
- __DSB(); \
- } while(0)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h
deleted file mode 100644
index 86e58fc0ad..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pccard.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_pccard.h
- * @author MCD Application Team
- * @brief Header file of PCCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCCARD_H
-#define STM32F2xx_HAL_PCCARD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCCARD
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
- * @{
- */
-
-/**
- * @brief HAL PCCARD State structures definition
- */
-typedef enum
-{
- HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
- HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
- HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
- HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
-} HAL_PCCARD_StateTypeDef;
-
-typedef enum
-{
- HAL_PCCARD_STATUS_SUCCESS = 0U,
- HAL_PCCARD_STATUS_ONGOING,
- HAL_PCCARD_STATUS_ERROR,
- HAL_PCCARD_STATUS_TIMEOUT
-} HAL_PCCARD_StatusTypeDef;
-
-/**
- * @brief FSMC_PCCARD handle Structure definition
- */
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-typedef struct __PCCARD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
-{
- FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
-
- FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
-
- __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
-
- HAL_LockTypeDef Lock; /*!< PCCARD Lock */
-
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
- void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
- void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
-#endif
-} PCCARD_HandleTypeDef;
-
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL PCCARD Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
- HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
- HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
-} HAL_PCCARD_CallbackIDTypeDef;
-
-/**
- * @brief HAL PCCARD Callback pointer definition
- */
-typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
-#endif
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
- * @{
- */
-/** @brief Reset PCCARD handle state
- * @param __HANDLE__ specifies the PCCARD handle.
- * @retval None
- */
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-#endif
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions
- * @{
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
- FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
- uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
- uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
-
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
-/* PCCARD callback registering/unregistering */
-HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
- pPCCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
- HAL_PCCARD_CallbackIDTypeDef CallbackId);
-#endif
-/**
- * @}
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group3
- * @{
- */
-/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
- * @{
- */
-#define PCCARD_DEVICE_ADDRESS 0x90000000U
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */
-#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */
-
-/* Flash-ATA registers description */
-#define ATA_DATA ((uint8_t)0x00) /* Data register */
-#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
-#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
-#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
-#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
-#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
-#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
-#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
-#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
-
-/* Flash-ATA commands */
-#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
-#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
-#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
-#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
-
-/* PC Card/Compact Flash status */
-#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
-#define PCCARD_BUSY ((uint8_t)0x80)
-#define PCCARD_PROGR ((uint8_t)0x01)
-#define PCCARD_READY ((uint8_t)0x40)
-
-#define PCCARD_SECTOR_SIZE 255U /* In half words */
-
-/**
- * @}
- */
-/* Compact Flash redefinition */
-#define HAL_CF_Init HAL_PCCARD_Init
-#define HAL_CF_DeInit HAL_PCCARD_DeInit
-#define HAL_CF_MspInit HAL_PCCARD_MspInit
-#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
-
-#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
-#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
-#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
-#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
-#define HAL_CF_Reset HAL_PCCARD_Reset
-#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
-#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
-
-#define HAL_CF_GetState HAL_PCCARD_GetState
-#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
-#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
-
-#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
-#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
-
-#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
-#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
-#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
-#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
-
-#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
-#define CF_BUSY PCCARD_BUSY
-#define CF_PROGR PCCARD_PROGR
-#define CF_READY PCCARD_READY
-
-#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
-
-/* Private macros ------------------------------------------------------------*/
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_PCCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h
deleted file mode 100644
index 5fd7ce155d..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_pcd.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCD_H
-#define STM32F2xx_HAL_PCD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_usb.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
- * @{
- */
-
-/**
- * @brief PCD State structure definition
- */
-typedef enum
-{
- HAL_PCD_STATE_RESET = 0x00,
- HAL_PCD_STATE_READY = 0x01,
- HAL_PCD_STATE_ERROR = 0x02,
- HAL_PCD_STATE_BUSY = 0x03,
- HAL_PCD_STATE_TIMEOUT = 0x04
-} PCD_StateTypeDef;
-
-/* Device LPM suspend state */
-typedef enum
-{
- LPM_L0 = 0x00, /* on */
- LPM_L1 = 0x01, /* LPM L1 sleep */
- LPM_L2 = 0x02, /* suspend */
- LPM_L3 = 0x03, /* off */
-} PCD_LPM_StateTypeDef;
-
-typedef enum
-{
- PCD_LPM_L0_ACTIVE = 0x00, /* on */
- PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
-} PCD_LPM_MsgTypeDef;
-
-typedef enum
-{
- PCD_BCD_ERROR = 0xFF,
- PCD_BCD_CONTACT_DETECTION = 0xFE,
- PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
- PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
- PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
- PCD_BCD_DISCOVERY_COMPLETED = 0x00,
-
-} PCD_BCD_MsgTypeDef;
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-/**
- * @brief PCD Handle Structure definition
- */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-typedef struct __PCD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
- uint32_t BESL;
-
- void *pData; /*!< Pointer to upper stack Handler */
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
- void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
- void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
- void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
- void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
- void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
- void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
-
- void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
- void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
- void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
- void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
-
- void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
- void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-} PCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Include PCD HAL Extended module */
-#include "stm32f2xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup PCD_Speed PCD Speed
- * @{
- */
-#define PCD_SPEED_HIGH USBD_HS_SPEED
-#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
-#define PCD_SPEED_FULL USBD_FS_SPEED
-/**
- * @}
- */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
- * @{
- */
-#define PCD_PHY_ULPI 1U
-#define PCD_PHY_EMBEDDED 2U
-#define PCD_PHY_UTMI 3U
-/**
- * @}
- */
-
-/** @defgroup PCD_Error_Code_definition PCD Error Code definition
- * @brief PCD Error Code definition
- * @{
- */
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
- ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
- *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
- *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
- ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
- } while(0U)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0U)
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
- * @brief HAL USB OTG PCD Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
- HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
- HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
- HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
- HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
- HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
-
- HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
- HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
-
-} HAL_PCD_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
- * @brief HAL USB OTG PCD Callback pointer definition
- * @{
- */
-
-typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
-typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
-typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
-typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
-typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
-
-/**
- * @}
- */
-
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
- pPCD_CallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
- pPCD_DataOutStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
- pPCD_DataInStageCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
- pPCD_IsoOutIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
- pPCD_IsoInIncpltCallbackTypeDef pCallback);
-
-HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
- * @{
- */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
- * @{
- */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
-#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-
-/**
- * @}
- */
-/**
- * @}
- */
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#ifndef USB_OTG_DOEPINT_OTEPSPR
-#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
-#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
-
-#ifndef USB_OTG_DOEPMSK_OTEPSPRM
-#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
-#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
-
-#ifndef USB_OTG_DOEPINT_NAK
-#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
-#endif /* defined USB_OTG_DOEPINT_NAK */
-
-#ifndef USB_OTG_DOEPMSK_NAKM
-#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
-#endif /* defined USB_OTG_DOEPMSK_NAKM */
-
-#ifndef USB_OTG_DOEPINT_STPKTRX
-#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
-#endif /* defined USB_OTG_DOEPINT_STPKTRX */
-
-#ifndef USB_OTG_DOEPMSK_NYETM
-#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
-#endif /* defined USB_OTG_DOEPMSK_NYETM */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h
deleted file mode 100644
index f0b180ee8c..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pcd_ex.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_pcd_ex.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_PCD_EX_H
-#define STM32F2xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCDEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
-void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h
deleted file mode 100644
index 15b0c260a5..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr.h
+++ /dev/null
@@ -1,425 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_PWR_H
-#define __STM32F2xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref PWR_PVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
- * @{
- */
-#define PWR_WAKEUP_PIN1 0x00000100U
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
- (Compare internally to VREFINT) */
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON 0x00000000U
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag PWR Flag
- * @{
- */
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-#define PWR_FLAG_BRR PWR_CSR_BRR
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
- * @{
- */
-
-/** @brief Check PWR flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm (Alarm A
- * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
- * when the device wakes up from Standby mode or by a system reset
- * or power reset.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the PWR's pending flags.
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
-
-/**
- * @brief Enable the PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Disable the PVD EXTI Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Enable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Disable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Enable the PVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
- }while(0)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
- }while(0)
-
-/**
- * @brief checks whether the specified PVD Exti interrupt flag is set or not.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Clear the PVD Exti flag.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Generates a Software interrupt on PVD EXTI line.
- * @retval None
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-
-/**
- * @}
- */
-
-/* Include PWR HAL Extension module */
-#include "stm32f2xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-/* Peripheral Control functions **********************************************/
-/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-
-/* Cortex System Control functions *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
- * @{
- */
-#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
- * @}
- */
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
- * @{
- */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET 0x00U
-#define PWR_CSR_OFFSET 0x04U
-#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
- * @}
- */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
- * @{
- */
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
-/**
- * @}
- */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
- * @{
- */
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
-#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-
-/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
- * @{
- */
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_NORMAL))
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F2xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h
deleted file mode 100644
index 7fe91d36b0..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_pwr_ex.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_pwr_ex.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_PWR_EX_H
-#define __STM32F2xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWREx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWR Exported Constants
- * @{
- */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWREx_Exported_Functions_Group1
- * @{
- */
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void);
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWR Private Constants
- * @{
- */
-
-/** @defgroup PWREx_register_alias_address PWR Register alias address
- * @{
- */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-/* --- CR Register ---*/
-/* Alias word address of FPDS bit */
-#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
-#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
-
- /**
- * @}
- */
-
-/** @defgroup PWREx_CSR_register_alias PWR CSR Register alias address
- * @{
- */
-/* --- CSR Register ---*/
-/* Alias word address of BRE bit */
-#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
-#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWR Private Macros
- * @{
- */
-
-/** @defgroup PWREx_IS_PWR_Definitions PWR Private macros to check input parameters
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F2xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h
deleted file mode 100644
index a793dd600a..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc.h
+++ /dev/null
@@ -1,2088 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_RCC_H
-#define __STM32F2xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
-
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
-
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
-
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
- This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
-
-}RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
- */
-typedef struct
-{
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-}RCC_OscInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
-
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_BYPASS ((uint8_t)0x05)
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_BYPASS ((uint8_t)0x05)
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF ((uint8_t)0x00)
-#define RCC_HSI_ON ((uint8_t)0x01)
-
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF ((uint8_t)0x00)
-#define RCC_LSI_ON ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE ((uint8_t)0x00)
-#define RCC_PLL_OFF ((uint8_t)0x01)
-#define RCC_PLL_ON ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
- * @{
- */
-#define RCC_PLLP_DIV2 0x00000002U
-#define RCC_PLLP_DIV4 0x00000004U
-#define RCC_PLLP_DIV6 0x00000006U
-#define RCC_PLLP_DIV8 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
-#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
-#define RCC_CLOCKTYPE_HCLK 0x00000002U
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
-#define RCC_RTCCLKSOURCE_LSE 0x00000100U
-#define RCC_RTCCLKSOURCE_LSI 0x00000200U
-#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
-#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
-#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
-#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
-#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
-#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
-#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
-#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
-#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
-#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
-#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
-#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
-#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
-#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
-#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
-#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
-#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
-#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
-#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
-#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-#define RCC_MCO1 0x00000000U
-#define RCC_MCO2 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_HSI 0x00000000U
-#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
-#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
-#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
- * @{
- */
-#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
-#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
- * @{
- */
-#define RCC_MCODIV_1 0x00000000U
-#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
-#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: 0XXYYYYYb
- * - YYYYY : Flag position in the register
- * - 0XX : Register index
- * - 01: CR register
- * - 10: BDCR register
- * - 11: CSR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)0x41)
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
-#define RCC_FLAG_BORRST ((uint8_t)0x79)
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-/**
- * @}
- */
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
- __HAL_RCC_SYSCFG_CLK_ENABLE();\
- }while(0)
-#define __HAL_RCC_RNG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
-#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
- * @brief Enables or disables the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB3 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_USART6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
-#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
-#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
- * @brief Force or release AHB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
- * @brief Force or release AHB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
- * @brief Force or release AHB3 peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
-#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
- * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
- * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
- * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__ specifies the calibration trimming value.
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
- RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
- * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator.
- * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
- */
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
- * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator.
- * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief Macros to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
- * a Power On Reset (POR).
- * @param __RTCCLKSource__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wake-up source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
- RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
- } while (0U)
-
-/** @brief Macro to get the RTC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/**
- * @brief Get the RTC and HSE clock divider (RTCPRE).
- * @retval Returned value can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
- */
-#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
-
-/** @brief Macros to force or release the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL can not be disabled if it is used as system clock source
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-
-/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
- * @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- * @param __PLLM__ specifies the division factor for PLL VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
- *
- * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
- * This parameter must be a number in the range {2, 4, 6, or 8}.
- *
- * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
- * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @note If the USB OTG FS is used in your application, you have to set the
- * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
- * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
- * correctly.
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
- MODIFY_REG(RCC->PLLCFGR, \
- (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ), \
- ((__RCC_PLLSource__) | (__PLLM__)| ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
- ((((__PLLP__) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)))
-/**
- * @}
- */
-
-/** @brief Macro to configure the PLL clock source.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- *
- */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief Macro to configure the PLL multiplication factor.
- * @note This function must be used only when the main PLL is disabled.
- * @param __PLLM__ specifies the division factor for PLL VCO input clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
- * @note You have to set the PLLM parameter correctly to ensure that the VCO input
- * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
- * of 2 MHz to limit PLL jitter.
- *
- */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
-
-/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the PLLI2S.
- * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
- * @note This macro must be used only when the PLLI2S is disabled.
- * @note PLLI2S clock source is common with the main PLL (configured in
- * HAL_RCC_ClockConfig() API).
- * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SR__ specifies the division factor for I2S clock
- * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
- * on the I2S clock frequency.
- */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
-
-/** @brief Macro to configure the I2S clock source (I2SCLK).
- * @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__ specifies the I2S clock source.
- * This parameter can be one of the following values:
- * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
- * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
- * used as I2S clock source.
- */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
- * @{
- */
-
-/** @brief Macro to configure the MCO1 clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
- * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCODIV_1: no division applied to MCOx clock
- * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
- * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
- * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
- * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
- */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @brief Macro to configure the MCO2 clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg RCC_MCODIV_1: no division applied to MCOx clock
- * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
- * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
- * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
- * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
- */
-#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
- * @{
- */
-/**
- * @brief Macro to configure the system clock source.
- * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be one
- * of the following:
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
- * the selected interrupts).
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt.
- * @arg RCC_IT_LSERDY: LSE ready interrupt.
- * @arg RCC_IT_HSIRDY: HSI ready interrupt.
- * @arg RCC_IT_HSERDY: HSE ready interrupt.
- * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
- * the selected interrupts).
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt.
- * @arg RCC_IT_LSERDY: LSE ready interrupt.
- * @arg RCC_IT_HSIRDY: HSI ready interrupt.
- * @arg RCC_IT_HSERDY: HSE ready interrupt.
- * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
- * bits to clear the selected interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt.
- * @arg RCC_IT_LSERDY: LSE ready interrupt.
- * @arg RCC_IT_HSIRDY: HSI ready interrupt.
- * @arg RCC_IT_HSERDY: HSE ready interrupt.
- * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
- * @arg RCC_IT_CSS: Clock Security System interrupt
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt.
- * @arg RCC_IT_LSERDY: LSE ready interrupt.
- * @arg RCC_IT_HSIRDY: HSI ready interrupt.
- * @arg RCC_IT_HSERDY: HSE ready interrupt.
- * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
- * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief Check RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
- * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
- * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
- * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
- * @arg RCC_FLAG_PINRST: Pin reset.
- * @arg RCC_FLAG_PORRST: POR/PDR reset.
- * @arg RCC_FLAG_SFTRST: Software reset.
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
- * @arg RCC_FLAG_LPWRRST: Low Power reset.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define RCC_FLAG_MASK ((uint8_t)0x1FU)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
-
-#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extended module */
-#include "stm32f2xx_hal_rcc_ex.h"
-/* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
- * @{
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
-#define RCC_HSION_BIT_NUMBER 0x00U
-#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER 0x13U
-#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER 0x18U
-#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
-/* Alias word address of PLLI2SON bit */
-#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
-#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
-
-/* --- CFGR Register ---*/
-/* Alias word address of I2SSRC bit */
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
-#define RCC_I2SSRC_BIT_NUMBER 0x17U
-#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
-
-/* --- BDCR Register ---*/
-/* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
-#define RCC_RTCEN_BIT_NUMBER 0x0FU
-#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER 0x10U
-#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
-#define RCC_LSION_BIT_NUMBER 0x00U
-#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS 0x40023802U
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
-
-/* BDCR register base address */
-#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-#define RCC_DBP_TIMEOUT_VALUE 2U
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
-
-#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 100 ms */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
- * @{
- */
-
-/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
- * @{
- */
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
-
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
-
-#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
-
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
-
-#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
- ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
- ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
- ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
- ((HCLK) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
- ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
- ((PCLK) == RCC_HCLK_DIV16))
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
- ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
-
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
- ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
- ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
- ((DIV) == RCC_MCODIV_5))
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h
deleted file mode 100644
index 18427df24c..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rcc_ex.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_RCC_EX_H
-#define __STM32F2xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-/**
- * @brief PLLI2S Clock structure definition
- */
-typedef struct
-{
- uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
- This parameter must be a number between Min_Data = 192 and Max_Data = 432.
- This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-
- uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 7.
- This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-
-}RCC_PLLI2SInitTypeDef;
-
-/**
- * @brief RCC extended clocks structure definition
- */
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
- This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
- This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-
-}RCC_PeriphCLKInitTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
- * @{
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
- * @{
- */
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
- * @{
- */
-#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
-#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
- * @brief Enables or disables the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
- __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
- __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
- __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
- __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-/**
- * @}
- */
-
-/**
- * @brief Enable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_ENABLE() do { \
- __HAL_RCC_ETHMAC_CLK_ENABLE(); \
- __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
- __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
- } while(0)
-/**
- * @brief Disable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_DISABLE() do { \
- __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
- __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
- __HAL_RCC_ETHMAC_CLK_DISABLE(); \
- } while(0)
-#endif /* STM32F207xx || STM32F217xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#endif /* STM32F207xx || STM32F217xx */
-
-#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
- UNUSED(tmpreg); \
- } while(0)
-#define __HAL_RCC_HASH_CLK_ENABLE() do { \
- __IO uint32_t tmpreg = 0x00; \
- SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
- UNUSED(tmpreg); \
- } while(0)
-
-#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F215xx || STM32F217xx */
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
-#endif /* defined(STM32F207xx) || defined(STM32F217xx) */
-#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
-#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
-
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
-#endif /* defined(STM32F215xx) || defined(STM32F217xx) */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
- * @brief Force or release AHB1 peripheral reset.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#endif /* STM32F207xx || STM32F217xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
- * @brief Force or release AHB2 peripheral reset.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#endif /* STM32F207xx || STM32F217xx */
-
-#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F215xx || STM32F217xx */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#endif /* STM32F207xx || STM32F217xx */
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
- * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
- * @note Peripheral clock gating in SLEEP mode can be used to further reduce
- * power consumption.
- * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
- * @note By default, all peripheral clocks are enabled during SLEEP mode.
- * @{
- */
-#if defined(STM32F207xx) || defined(STM32F217xx)
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-#endif /* STM32F207xx || STM32F217xx */
-
-#if defined(STM32F215xx) || defined(STM32F217xx)
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F215xx || STM32F217xx */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCC Private Constants
- * @{
- */
-
-/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCC Private Macros
- * @{
- */
-/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
- * @{
- */
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h
deleted file mode 100644
index 5b0e480c6c..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rng.h
+++ /dev/null
@@ -1,363 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_rng.h
- * @author MCD Application Team
- * @brief Header file of RNG HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_RNG_H
-#define STM32F2xx_HAL_RNG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-#if defined (RNG)
-
-/** @defgroup RNG RNG
- * @brief RNG HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
- * @{
- */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
- * @{
- */
-typedef enum
-{
- HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
- HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
- HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
- HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
- HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
-
-} HAL_RNG_StateTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
- * @{
- */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-typedef struct __RNG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-{
- RNG_TypeDef *Instance; /*!< Register base address */
-
- HAL_LockTypeDef Lock; /*!< RNG locking object */
-
- __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
-
- __IO uint32_t ErrorCode; /*!< RNG Error code */
-
- uint32_t RandomNumber; /*!< Last Generated RNG Data */
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
- void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
- void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
-
- void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
- void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-} RNG_HandleTypeDef;
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL RNG Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
-
- HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
- HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
-
-} HAL_RNG_CallbackIDTypeDef;
-
-/**
- * @brief HAL RNG Callback pointer definition
- */
-typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
-typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
-
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
- * @{
- */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
- * @{
- */
-#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
-#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
-#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
- * @{
- */
-#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
-#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
-#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
-/**
- * @}
- */
-
-/** @defgroup RNG_Error_Definition RNG Error Definition
- * @{
- */
-#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
-#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
-#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
-#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
- * @{
- */
-
-/** @brief Reset RNG handle state
- * @param __HANDLE__ RNG Handle
- * @retval None
- */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_RNG_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
- * @brief Enables the RNG peripheral.
- * @param __HANDLE__ RNG Handle
- * @retval None
- */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
-
-/**
- * @brief Disables the RNG peripheral.
- * @param __HANDLE__ RNG Handle
- * @retval None
- */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
- * @brief Check the selected RNG flag status.
- * @param __HANDLE__ RNG Handle
- * @param __FLAG__ RNG flag
- * This parameter can be one of the following values:
- * @arg RNG_FLAG_DRDY: Data ready
- * @arg RNG_FLAG_CECS: Clock error current status
- * @arg RNG_FLAG_SECS: Seed error current status
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clears the selected RNG flag status.
- * @param __HANDLE__ RNG handle
- * @param __FLAG__ RNG flag to clear
- * @note WARNING: This is a dummy macro for HAL code alignment,
- * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
- * @retval None
- */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
-
-/**
- * @brief Enables the RNG interrupts.
- * @param __HANDLE__ RNG Handle
- * @retval None
- */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
-
-/**
- * @brief Disables the RNG interrupts.
- * @param __HANDLE__ RNG Handle
- * @retval None
- */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
- * @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param __HANDLE__ RNG Handle
- * @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
- * This parameter can be one of the following values:
- * @arg RNG_IT_DRDY: Data ready interrupt
- * @arg RNG_IT_CEI: Clock error interrupt
- * @arg RNG_IT_SEI: Seed error interrupt
- * @retval The new state of __INTERRUPT__ (SET or RESET).
- */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clear the RNG interrupt status flags.
- * @param __HANDLE__ RNG Handle
- * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
- * This parameter can be one of the following values:
- * @arg RNG_IT_CEI: Clock error interrupt
- * @arg RNG_IT_SEI: Seed error interrupt
- * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
- * @retval None
- */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
- * @{
- */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
- * @{
- */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
- pRNG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef
- *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */
-uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef
- *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
-
-/**
- * @}
- */
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
- * @{
- */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
- ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* RNG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h
deleted file mode 100644
index 06f790ad66..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc.h
+++ /dev/null
@@ -1,801 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_RTC_H
-#define __STM32F2xx_HAL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
-} HAL_RTCStateTypeDef;
-
-/**
- * @brief RTC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
- uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FFF */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTC_Output_selection_Definitions */
-
- uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
- This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
- uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
- This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-} RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
- uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
-
- uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
-
-} RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t Date; /*!< Specifies the RTC Date.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-} RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
- uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
- If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint32_t Alarm; /*!< Specifies the alarm .
- This parameter can be a value of @ref RTC_Alarms_Definitions */
-} RTC_AlarmTypeDef;
-
-/**
- * @brief RTC Handle Structure definition
- */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-typedef struct __RTC_HandleTypeDef
-#else
-typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-{
- RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
-
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
-
- void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
-
- void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
-
- void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
-
- void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
-
- void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
-
- void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
-
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-} RTC_HandleTypeDef;
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL RTC Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
- HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
- HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
- HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
- HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
- HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
- HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
-} HAL_RTC_CallbackIDTypeDef;
-
-/**
- * @brief HAL RTC Callback pointer definition
- */
-typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
- * @{
- */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
- * @{
- */
-#define RTC_HOURFORMAT_24 0x00000000U
-#define RTC_HOURFORMAT_12 0x00000040U
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
- * @{
- */
-#define RTC_OUTPUT_DISABLE 0x00000000U
-#define RTC_OUTPUT_ALARMA 0x00200000U
-#define RTC_OUTPUT_ALARMB 0x00400000U
-#define RTC_OUTPUT_WAKEUP 0x00600000U
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
- * @{
- */
-#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
-#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
- * @{
- */
-#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
-#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
- * @{
- */
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
- * @{
- */
-#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
-#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
-#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
- * @{
- */
-#define RTC_STOREOPERATION_RESET 0x00000000U
-#define RTC_STOREOPERATION_SET 0x00040000U
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
- * @{
- */
-#define RTC_FORMAT_BIN 0x00000000U
-#define RTC_FORMAT_BCD 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
- * @{
- */
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
-#define RTC_MONTH_MARCH ((uint8_t)0x03)
-#define RTC_MONTH_APRIL ((uint8_t)0x04)
-#define RTC_MONTH_MAY ((uint8_t)0x05)
-#define RTC_MONTH_JUNE ((uint8_t)0x06)
-#define RTC_MONTH_JULY ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
- * @{
- */
-#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
- * @{
- */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
- * @{
- */
-#define RTC_ALARMMASK_NONE 0x00000000U
-#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL 0x80808080U
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
- * @{
- */
-#define RTC_ALARM_A RTC_CR_ALRAE
-#define RTC_ALARM_B RTC_CR_ALRBE
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
- * @{
- */
-#define RTC_IT_TS 0x00008000U
-#define RTC_IT_WUT 0x00004000U
-#define RTC_IT_ALRB 0x00002000U
-#define RTC_IT_ALRA 0x00001000U
-#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 0x00020000U
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
- * @{
- */
-#define RTC_FLAG_TAMP1F 0x00002000U
-#define RTC_FLAG_TSOVF 0x00001000U
-#define RTC_FLAG_TSF 0x00000800U
-#define RTC_FLAG_WUTF 0x00000400U
-#define RTC_FLAG_ALRBF 0x00000200U
-#define RTC_FLAG_ALRAF 0x00000100U
-#define RTC_FLAG_INITF 0x00000040U
-#define RTC_FLAG_RSF 0x00000020U
-#define RTC_FLAG_INITS 0x00000010U
-#define RTC_FLAG_WUTWF 0x00000004U
-#define RTC_FLAG_ALRBWF 0x00000002U
-#define RTC_FLAG_ALRAWF 0x00000001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @brief Reset RTC handle state
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0u)
-#else
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
- } while(0U)
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0U)
-
-/**
- * @brief Enable the RTC ALARMA peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
- * @brief Disable the RTC ALARMA peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
- * @brief Enable the RTC ALARMB peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
- * @brief Disable the RTC ALARMB peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
- * @brief Enable the RTC Alarm interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Alarm interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag to check.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @arg RTC_FLAG_ALRAWF
- * @arg RTC_FLAG_ALRBWF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable event on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();\
- __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Clear the RTC Alarm associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
-/**
- * @}
- */
-
-/* Include RTC HAL Extension module */
-#include "stm32f2xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RTC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group2
- * @{
- */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-/* RTC Daylight Saving Time functions *****************************************/
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group3
- * @{
- */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTC_Exported_Functions_Group5
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
- * @{
- */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK 0x007F7F7FU
-#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
-#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F))
-
-#define RTC_TIMEOUT_VALUE 1000U
-
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
- * @{
- */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
- * @{
- */
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFFU)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
- * @{
- */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h
deleted file mode 100644
index 4b7dbe2448..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_rtc_ex.h
+++ /dev/null
@@ -1,790 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_rtc_ex.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_RTC_EX_H
-#define __STM32F2xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTC Exported Types
- * @{
- */
-
-/** @brief RTC Tamper structure definition
- */
-typedef struct
-{
- uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
-
- uint32_t PinSelection; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
-
- uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
-} RTC_TamperTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTC Exported Constants
- * @{
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
- * @{
- */
-#define RTC_BKP_DR0 0x00000000U
-#define RTC_BKP_DR1 0x00000001U
-#define RTC_BKP_DR2 0x00000002U
-#define RTC_BKP_DR3 0x00000003U
-#define RTC_BKP_DR4 0x00000004U
-#define RTC_BKP_DR5 0x00000005U
-#define RTC_BKP_DR6 0x00000006U
-#define RTC_BKP_DR7 0x00000007U
-#define RTC_BKP_DR8 0x00000008U
-#define RTC_BKP_DR9 0x00000009U
-#define RTC_BKP_DR10 0x0000000AU
-#define RTC_BKP_DR11 0x0000000BU
-#define RTC_BKP_DR12 0x0000000CU
-#define RTC_BKP_DR13 0x0000000DU
-#define RTC_BKP_DR14 0x0000000EU
-#define RTC_BKP_DR15 0x0000000FU
-#define RTC_BKP_DR16 0x00000010U
-#define RTC_BKP_DR17 0x00000011U
-#define RTC_BKP_DR18 0x00000012U
-#define RTC_BKP_DR19 0x00000013U
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
- * @{
- */
-#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
-#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
- * @{
- */
-#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
- * @{
- */
-#define RTC_TAMPERPIN_DEFAULT 0x00000000U
-#define RTC_TAMPERPIN_POS1 0x00010000U
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
- * @{
- */
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
-#define RTC_TIMESTAMPPIN_POS1 0x00020000U
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
- * @{
- */
-#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
-#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
- * @{
- */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
- * @{
- */
-#define RTC_CALIBSIGN_POSITIVE 0x00000000U
-#define RTC_CALIBSIGN_NEGATIVE 0x00000080U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
- * @{
- */
-
-/**
- * @brief Enable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
- * @brief Disable the RTC Wake-up Timer peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
- * @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable event on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable event on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Clear the RTC Wake-up Timer associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-
-/**
- * @}
- */
-
-/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
- * @{
- */
-
-/**
- * @brief Enable the RTC TimeStamp peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
- * @brief Disable the RTC TimeStamp peripheral.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC TimeStamp flag to check.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @}
- */
-
-/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Tamper
- * @{
- */
-
-/**
- * @brief Enable the RTC Tamper1 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
-
-/**
- * @brief Disable the RTC Tamper1 input detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP1
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
- * This parameter can be:
- * @arg RTC_IT_TAMP: Tamper interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-/**
- * @}
- */
-
-/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
- * @{
- */
-
-/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
- * @retval None
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
-
-/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do{ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
- }while(0U)
-
-/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
- * @retval Line Status.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-
-/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
- * @retval None.
- */
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
-/**
- * @}
- */
-
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
- * @{
- */
-
-/**
- * @brief Enable the Coarse calibration process.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
-
-/**
- * @brief Disable the Coarse calibration process.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
-
-/**
- * @brief Enable the RTC calibration output.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
- * @brief Disable the calibration output.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
- * @brief Enable the clock reference detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
- * @brief Disable the clock reference detection.
- * @param __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @{
- */
-/* RTC TimeStamp and Tamper functions *****************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @{
- */
-/* RTC Wake-up functions ******************************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
- * @{
- */
-/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/** @addtogroup RTCEx_Exported_Functions_Group4
- * @{
- */
-/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTC Private Constants
- * @{
- */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTC Private Macros
- * @{
- */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
- * @{
- */
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
- ((PIN) == RTC_TAMPERPIN_POS1))
-
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
- ((PIN) == RTC_TIMESTAMPPIN_POS1))
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
- ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20U)
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~(RTC_TAFCR_TAMP1E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
deleted file mode 100644
index b1b3cf9615..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sd.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_sd.h
- * @author MCD Application Team
- * @brief Header file of SD HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SD_H
-#define STM32F2xx_HAL_SD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(SDIO)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SD SD
- * @brief SD HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SD_Exported_Types SD Exported Types
- * @{
- */
-
-/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
- HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
- HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
- HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
- HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */
- HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */
- HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
-}HAL_SD_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
- * @{
- */
-typedef uint32_t HAL_SD_CardStateTypeDef;
-
-#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */
-#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */
-#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */
-#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */
-#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */
-#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */
-#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */
-#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */
-#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
- * @{
- */
-#define SD_InitTypeDef SDIO_InitTypeDef
-#define SD_TypeDef SDIO_TypeDef
-
-/**
- * @brief SD Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t CardVersion; /*!< Specifies the card version */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_SD_CardInfoTypeDef;
-
-/**
- * @brief SD handle Structure definition
- */
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-typedef struct __SD_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-{
- SD_TypeDef *Instance; /*!< SD registers base address */
-
- SD_InitTypeDef Init; /*!< SD required parameters */
-
- HAL_LockTypeDef Lock; /*!< SD locking object */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< SD Tx Transfer size */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< SD Rx Transfer size */
-
- __IO uint32_t Context; /*!< SD transfer context */
-
- __IO HAL_SD_StateTypeDef State; /*!< SD card State */
-
- __IO uint32_t ErrorCode; /*!< SD Card Error codes */
-
- DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
-
- HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
-
- uint32_t CSD[4]; /*!< SD card specific data table */
-
- uint32_t CID[4]; /*!< SD card identification number table */
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
- void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
- void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
-
- void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
- void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-}SD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGroup; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-}HAL_SD_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_SD_CardCIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_SD_CardStatusTypeDef;
-/**
- * @}
- */
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
- * @{
- */
-typedef enum
-{
- HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
- HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
- HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
- HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
-
- HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
- HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
-}HAL_SD_CallbackIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
- * @{
- */
-typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
- * @{
- */
-
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
- * @{
- */
-#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
- * @{
- */
-#define SD_CONTEXT_NONE 0x00000000U /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
- * @{
- */
-#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */
-#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
-#define CARD_SECURED 0x00000003U
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
- * @{
- */
-#define CARD_V1_X 0x00000000U
-#define CARD_V2_X 0x00000001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-/** @brief Reset SD handle state.
- * @param __HANDLE__ : SD handle.
- * @retval None
- */
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_SD_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the SD device.
- * @retval None
- */
-#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SD device.
- * @retval None
- */
-#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
- * @retval The new state of SD FLAG (SET or RESET).
- */
-#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the SD's pending flags.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
- * @retval None
- */
-#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval The new state of SD IT (SET or RESET).
- */
-#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
- * @{
- */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-
-#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
-/* SD callback registering/unregistering */
-HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);
-#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group4 SD card related functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* SDIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h
deleted file mode 100644
index 8f79f7228e..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_smartcard.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_smartcard.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_SMARTCARD_H
-#define __STM32F2xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
- * @{
- */
-
-/**
- * @brief SMARTCARD Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (hsc->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref SMARTCARD_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref SMARTCARD_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref SMARTCARD_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits).*/
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref SMARTCARD_Mode */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
- to provide the smartcard clock. The value given in the register (5 significant bits)
- is multiplied by 2 to give the division factor of the source clock frequency.
- This parameter can be a value of @ref SMARTCARD_Prescaler */
-
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-
- uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
- This parameter can be a value of @ref SMARTCARD_NACK_State */
-}SMARTCARD_InitTypeDef;
-
-/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
- * - gState contains SMARTCARD state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initialization status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL SMARTCARD Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initialization status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
-
-/**
- * @brief SMARTCARD handle Structure definition
- */
-typedef struct __SMARTCARD_HandleTypeDef
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< SmartCard Error code */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
- void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Tx Complete Callback */
-
- void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Rx Complete Callback */
-
- void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Error Callback */
-
- void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Complete Callback */
-
- void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Transmit Complete Callback */
-
- void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Abort Receive Complete Callback */
-
- void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp Init callback */
-
- void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsc); /*!< SMARTCARD Msp DeInit callback */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-} SMARTCARD_HandleTypeDef;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL SMARTCARD Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
- HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
- HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
- HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
- HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
- HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
-
- HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
- HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
-
-} HAL_SMARTCARD_CallbackIDTypeDef;
-
-/**
- * @brief HAL SMARTCARD Callback pointer definition
- */
-typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsc); /*!< pointer to an SMARTCARD callback function */
-
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
- * @{
- */
-
-/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
- * @{
- */
-#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
- * @{
- */
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
- * @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
- * @{
- */
-#define SMARTCARD_POLARITY_LOW 0x00000000U
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
- * @{
- */
-#define SMARTCARD_PHASE_1EDGE 0x00000000U
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
- * @{
- */
-#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
- * @{
- */
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
- * @{
- */
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
- * @{
- */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
-/**
- * @}
- */
-
-/** @defgroup SmartCard_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the Y register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 11: CR3 register
- * @{
- */
-#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
- * @{
- */
-
-/** @brief Reset SMARTCARD handle gstate & RxState
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- } while(0U)
-#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/** @brief Flush the Smartcard DR register
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Check whether the specified Smartcard flag is set or not.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
- * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
- * @arg SMARTCARD_FLAG_ORE: Overrun Error flag
- * @arg SMARTCARD_FLAG_NE: Noise Error flag
- * @arg SMARTCARD_FLAG_FE: Framing Error flag
- * @arg SMARTCARD_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified Smartcard pending flags.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (Overrun
- * error) flags are cleared by software sequence: a read operation to
- * USART_SR register followed by a read operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified SmartCard interrupt.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief Disable the specified SmartCard interrupt.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__ specifies the SmartCard Handle.
- * @param __IT__ specifies the SMARTCARD interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-
-/** @brief Macro to enable the SMARTCARD's one bit sample method
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Macro to disable the SMARTCARD's one bit sample method
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief Enable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__ specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief Macros to enable the SmartCard DMA request.
- * @param __HANDLE__ specifies the SmartCard Handle.
- * @param __REQUEST__ specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
- * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- * @retval None
- */
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-
-/** @brief Macros to disable the SmartCard DMA request.
- * @param __HANDLE__ specifies the SmartCard Handle.
- * @param __REQUEST__ specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
- * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- * @retval None
- */
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
- * @{
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-/**
- * @}
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
-
-/** @brief SMARTCARD interruptions flag mask
- *
- */
-#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR3_EIE )
-
-#define SMARTCARD_CR1_REG_INDEX 1U
-#define SMARTCARD_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
- * @{
- */
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
- ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U)
-/* SMARTCARD BRR = mantissa + overflow + fraction
- = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
-#define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \
- (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0xF0U)) + \
- (SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0FU))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h
deleted file mode 100644
index 118b37ae66..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_spi.h
+++ /dev/null
@@ -1,730 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SPI_H
-#define STM32F2xx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-} SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum
-{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
- HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
-} HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
- void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
- void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
- void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
- void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
- void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
- void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
- void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
- void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
- void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
- void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
- * @brief HAL SPI Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
- HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
- HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
- HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
- HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
- HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
- HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
- HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
- HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
- HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
- * @brief HAL SPI Callback pointer definition
- */
-typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_Error_Code SPI Error Code
- * @{
- */
-#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */
-#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE (0x00000000U)
-#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_8BIT (0x00000000U)
-#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW (0x00000000U)
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE (0x00000000U)
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB (0x00000000U)
-#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE (0x00000000U)
-#define SPI_TIMODE_ENABLE SPI_CR2_FRF
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_CR2_TXEIE
-#define SPI_IT_RXNE SPI_CR2_RXNEIE
-#define SPI_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
-#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
- | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__ specifies the SPI handle.
- * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
- & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0U)
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while(0U)
-
-/** @brief Clear the SPI FRE pending flag.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
- }while(0U)
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__ specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of SPI SR register.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
- * @retval SET or RESET.
- */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
- ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of SPI CR2 register.
- * @param __INTERRUPT__ specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval SET or RESET.
- */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
- (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks if SPI Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Mode.
- * This parameter can be a value of @ref SPI_Mode
- * @retval None
- */
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
- ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief Checks if SPI Direction Mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI Direction Mode.
- * This parameter can be a value of @ref SPI_Direction
- * @retval None
- */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Direction Mode parameter is 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
- * @param __MODE__ specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Data Size parameter is in allowed range.
- * @param __DATASIZE__ specifies the SPI Data Size.
- * This parameter can be a value of @ref SPI_Data_Size
- * @retval None
- */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
- * @param __CPOL__ specifies the SPI serial clock steady state.
- * This parameter can be a value of @ref SPI_Clock_Polarity
- * @retval None
- */
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
- ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief Checks if SPI Clock Phase parameter is in allowed range.
- * @param __CPHA__ specifies the SPI Clock Phase.
- * This parameter can be a value of @ref SPI_Clock_Phase
- * @retval None
- */
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
- ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief Checks if SPI Slave Select parameter is in allowed range.
- * @param __NSS__ specifies the SPI Slave Select management parameter.
- * This parameter can be a value of @ref SPI_Slave_Select_management
- * @retval None
- */
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
- ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
- * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
- * This parameter can be a value of @ref SPI_BaudRate_Prescaler
- * @retval None
- */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
- * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
- * This parameter can be a value of @ref SPI_MSB_LSB_transmission
- * @retval None
- */
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
- ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief Checks if SPI TI mode parameter is in allowed range.
- * @param __MODE__ specifies the SPI TI mode.
- * This parameter can be a value of @ref SPI_TI_mode
- * @retval None
- */
-#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
- ((__MODE__) == SPI_TIMODE_ENABLE))
-
-/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
- * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
- * This parameter can be a value of @ref SPI_CRC_Calculation
- * @retval None
- */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
- ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
- * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
- * @retval None
- */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
- ((__POLYNOMIAL__) <= 0xFFFFU) && \
- (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief Checks if DMA handle is valid.
- * @param __HANDLE__ specifies a DMA Handle.
- * @retval None
- */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
- uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
- uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h
deleted file mode 100644
index f95c53dccf..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_sram.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_sram.h
- * @author MCD Application Team
- * @brief Header file of SRAM HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_SRAM_H
-#define STM32F2xx_HAL_SRAM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_ll_fsmc.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-/** @addtogroup SRAM
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
- * @{
- */
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
- HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
-
-} HAL_SRAM_StateTypeDef;
-
-/**
- * @brief SRAM handle Structure definition
- */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-typedef struct __SRAM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-{
- FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< SRAM locking object */
-
- __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
-
- DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
- void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
- void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-} SRAM_HandleTypeDef;
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL SRAM Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
- HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
- HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
- HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
-} HAL_SRAM_CallbackIDTypeDef;
-
-/**
- * @brief HAL SRAM Callback pointer definition
- */
-typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
-typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
-
-/** @brief Reset SRAM handle state
- * @param __HANDLE__ SRAM handle
- * @retval None
- */
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
- * @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
- FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
- uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
- uint32_t BufferSize);
-
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
-/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
- pSRAM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
- pSRAM_DmaCallbackTypeDef pCallback);
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
-
-/* SRAM Control functions ****************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* SRAM State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h
deleted file mode 100644
index a6db7470ec..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim.h
+++ /dev/null
@@ -1,2129 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_TIM_H
-#define STM32F2xx_HAL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and
- Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
- Max_Data = 0xFFFF. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for timer instances supporting break feature. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-/**
- * @brief Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter must be 0: When OCRef clear feature is used with ETR source,
- ETR prescaler must be off */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct
-{
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode
- @note When the Master/slave mode is enabled, the effect of
- an event on the trigger input (TRGI) is delayed to allow a
- perfect synchronization between the current timer and its
- slaves (through TRGO). It is not mandatory in case of timer
- synchronization mode. */
-} TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct
-{
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-} TIM_SlaveConfigTypeDef;
-
-/**
- * @brief TIM Break input(s) and Dead time configuration Structure definition
- * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
- * filter and polarity.
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
-
- uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
- uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-
-} TIM_BreakDeadTimeConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_TIM_StateTypeDef;
-
-/**
- * @brief TIM Channel States definition
- */
-typedef enum
-{
- HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
- HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
- HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
-} HAL_TIM_ChannelStateTypeDef;
-
-/**
- * @brief DMA Burst States definition
- */
-typedef enum
-{
- HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
- HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
- HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
-} HAL_TIM_DMABurstStateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-} HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-typedef struct __TIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
- __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
- __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
- void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
- void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
- void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
- void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
- void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
- void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
- void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
- void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
- void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
- void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
- void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
- void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
- void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
- void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
- void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
- void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
- void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
- void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
- void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
- void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
- void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
- void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
- void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
- void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
- void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
- void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
- void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-} TIM_HandleTypeDef;
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL TIM Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
- , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
-} HAL_TIM_CallbackIDTypeDef;
-
-/**
- * @brief HAL TIM Callback pointer definition
- */
-typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
-
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_DCR 0x00000012U
-#define TIM_DMABASE_DMAR 0x00000013U
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
-#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
-#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
-#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
-#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
-#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
-#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
-#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
-#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
-#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
- * @{
- */
-#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
-#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
-#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
-#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
-#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
-#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
-#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
-#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
-#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
-#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
-#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
-#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
-#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
-#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
-#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
-#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
-#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
-#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
-#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
-#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
-#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
-#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
-#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
-#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
-#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
-#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
-#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
-#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
-#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
-#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
-#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
-#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
-#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
-#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
-#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
-#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
-/**
- * @}
- */
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
-#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
- * @{
- */
-#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
-#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
-#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
-#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
-#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
-#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
-#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
-#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
-#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
-#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
-#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
-#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
- * @{
- */
-#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
-#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
-#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
-#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
-#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
-#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
-#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
-#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
-#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
-#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
-#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
-#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
-#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
-/**
- * @}
- */
-
-/** @defgroup DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
-#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
-#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
-#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state.
- * @param __HANDLE__ TIM handle.
- * @retval None
- */
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- (__HANDLE__)->Base_MspInitCallback = NULL; \
- (__HANDLE__)->Base_MspDeInitCallback = NULL; \
- (__HANDLE__)->IC_MspInitCallback = NULL; \
- (__HANDLE__)->IC_MspDeInitCallback = NULL; \
- (__HANDLE__)->OC_MspInitCallback = NULL; \
- (__HANDLE__)->OC_MspDeInitCallback = NULL; \
- (__HANDLE__)->PWM_MspInitCallback = NULL; \
- (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
- (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspInitCallback = NULL; \
- (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
- (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
- } while(0)
-#else
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
- (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
- (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
- (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
- } while(0)
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__ TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
- * disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__ TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled unconditionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/** @brief Enable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/** @brief Disable the specified DMA request.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __DMA__ specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__ specifies the TIM Handle.
- * @param __FLAG__ specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
- == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__ TIM handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__ TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
- * or Encoder mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the Prescaler new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Set the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __COUNTER__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Get the TIM Counter Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __AUTORELOAD__ specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Autoreload Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
- * @param __HANDLE__ TIM handle.
- * @param __CKD__ specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
-
-/**
- * @brief Get the TIM Clock Division value on runtime.
- * @param __HANDLE__ TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
- * function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
-
-/**
- * @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
- ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
-
-/**
- * @brief Get the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
- ((__HANDLE__)->Instance->CCR4))
-
-/**
- * @brief Set the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
- * @brief Reset the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
-
-/**
- * @brief Enable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @note When fast mode is enabled an active edge on the trigger input acts
- * like a compare match on CCx output. Delay to sample the trigger
- * input and to activate CCx output is reduced to 3 clock cycles.
- * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
-
-/**
- * @brief Disable fast mode for a given channel.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @note When fast mode is disabled CCx output behaves normally depending
- * on counter and CCRx values even when the trigger is ON. The minimum
- * delay to activate CCx output when an active edge occurs on the
- * trigger input is 5 clock cycles.
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
- * @param __HANDLE__ TIM handle.
- * @note When the URS bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * _ Counter overflow underflow
- * _ Setting the UG bit
- * _ Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
-
-/**
- * @brief Set the TIM Capture x input polarity on runtime.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
-
-/**
- * @}
- */
-/* End of exported macros ----------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-/* End of private constants --------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
-
-#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
- ((__BASE__) == TIM_DMABASE_CR2) || \
- ((__BASE__) == TIM_DMABASE_SMCR) || \
- ((__BASE__) == TIM_DMABASE_DIER) || \
- ((__BASE__) == TIM_DMABASE_SR) || \
- ((__BASE__) == TIM_DMABASE_EGR) || \
- ((__BASE__) == TIM_DMABASE_CCMR1) || \
- ((__BASE__) == TIM_DMABASE_CCMR2) || \
- ((__BASE__) == TIM_DMABASE_CCER) || \
- ((__BASE__) == TIM_DMABASE_CNT) || \
- ((__BASE__) == TIM_DMABASE_PSC) || \
- ((__BASE__) == TIM_DMABASE_ARR) || \
- ((__BASE__) == TIM_DMABASE_RCR) || \
- ((__BASE__) == TIM_DMABASE_CCR1) || \
- ((__BASE__) == TIM_DMABASE_CCR2) || \
- ((__BASE__) == TIM_DMABASE_CCR3) || \
- ((__BASE__) == TIM_DMABASE_CCR4) || \
- ((__BASE__) == TIM_DMABASE_BDTR))
-
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
- ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
- ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
- ((__STATE__) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
- ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
- ((__STATE__) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
-
-#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
- ((__SELECTION__) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
- ((__PRESCALER__) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
- ((__MODE__) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
- ((__MODE__) == TIM_ENCODERMODE_TI2) || \
- ((__MODE__) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-
-#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3) || \
- ((__CHANNEL__) == TIM_CHANNEL_4) || \
- ((__CHANNEL__) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
- ((__CHANNEL__) == TIM_CHANNEL_2) || \
- ((__CHANNEL__) == TIM_CHANNEL_3))
-
-#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
- ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
- ((__STATE__) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
- ((__STATE__) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
- ((__LEVEL__) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
-
-#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
- ((__STATE__) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
- ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
- ((__SOURCE__) == TIM_TRGO_ENABLE) || \
- ((__SOURCE__) == TIM_TRGO_UPDATE) || \
- ((__SOURCE__) == TIM_TRGO_OC1) || \
- ((__SOURCE__) == TIM_TRGO_OC1REF) || \
- ((__SOURCE__) == TIM_TRGO_OC2REF) || \
- ((__SOURCE__) == TIM_TRGO_OC3REF) || \
- ((__SOURCE__) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
- ((__MODE__) == TIM_SLAVEMODE_RESET) || \
- ((__MODE__) == TIM_SLAVEMODE_GATED) || \
- ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
- ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
- ((__MODE__) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
- ((__MODE__) == TIM_OCMODE_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_INACTIVE) || \
- ((__MODE__) == TIM_OCMODE_TOGGLE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
- ((__SELECTION__) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
- ((__SELECTION__) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
- ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
-
-#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
-
-#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
-
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
- (__HANDLE__)->ChannelState[3])
-
-#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
- } while(0)
-
-#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
- (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
- (__HANDLE__)->ChannelNState[3])
-
-#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
- ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
-
-#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
- (__HANDLE__)->ChannelNState[0] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[1] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[2] = \
- (__CHANNEL_STATE__); \
- (__HANDLE__)->ChannelNState[3] = \
- (__CHANNEL_STATE__); \
- } while(0)
-
-/**
- * @}
- */
-/* End of private macros -----------------------------------------------------*/
-
-/* Include TIM HAL Extended module */
-#include "stm32f2xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
- * @brief Time Base functions
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
- * @brief TIM Output Compare functions
- * @{
- */
-/* Timer Output Compare functions *********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
- * @brief TIM PWM functions
- * @{
- */
-/* Timer PWM functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
- * @brief TIM Input Capture functions
- * @{
- */
-/* Timer Input Capture functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
- * @brief TIM One Pulse functions
- * @{
- */
-/* Timer One Pulse functions **************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
- * @brief TIM Encoder functions
- * @{
- */
-/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
- uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- * @{
- */
-/* Interrupt Handler functions ***********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
- uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
- uint32_t BurstLength, uint32_t DataLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
- pTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
- * @brief Peripheral State functions
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/* Peripheral Channel state functions ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
- uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
-
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-void TIM_ResetCallback(TIM_HandleTypeDef *htim);
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h
deleted file mode 100644
index 1debb7088e..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_tim_ex.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_TIM_EX_H
-#define STM32F2xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
- * @{
- */
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-/**
- * @}
- */
-/* End of exported types -----------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Remap TIM Extended Remapping
- * @{
- */
-#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */
-#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */
-#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */
-#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */
-
-#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */
-#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */
-#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */
-#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
-
-#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */
-#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported constants -------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-/* End of exported macro -----------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
- * @{
- */
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
- ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
- ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
- ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
- (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
- ((TIM_REMAP) == TIM_TIM5_LSI) || \
- ((TIM_REMAP) == TIM_TIM5_LSE) || \
- ((TIM_REMAP) == TIM_TIM5_RTC))) || \
- (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
- ((TIM_REMAP) == TIM_TIM11_HSE))))
-
-/**
- * @}
- */
-/* End of private macro ------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
-/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
- uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
- TIM_MasterConfigTypeDef *sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
- TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
- * @brief Extended Callbacks functions
- * @{
- */
-/* Extended Callback **********************************************************/
-void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
- * @brief Extended Peripheral State functions
- * @{
- */
-/* Extended Peripheral State functions ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h
deleted file mode 100644
index aa37d9dc2a..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_uart.h
+++ /dev/null
@@ -1,881 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_uart.h
- * @author MCD Application Team
- * @brief Header file of UART HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_UART_H
-#define __STM32F2xx_HAL_UART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
- * @{
- */
-
-/**
- * @brief UART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
- Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UART_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode */
-
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling */
-} UART_InitTypeDef;
-
-/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
- * - gState contains UART state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 Peripheral initialization status
- * 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral initialized. HAL UART Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (Peripheral busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 Peripheral initialization status
- * 0 : Reset (Peripheral not initialized)
- * 1 : Init done (Peripheral initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-} HAL_UART_StateTypeDef;
-
-/**
- * @brief HAL UART Reception type definition
- * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
- * HAL_UART_RECEPTION_STANDARD = 0x00U,
- * HAL_UART_RECEPTION_TOIDLE = 0x01U,
- */
-typedef uint32_t HAL_UART_RxTypeTypeDef;
-
-/**
- * @brief UART handle Structure definition
- */
-typedef struct __UART_HandleTypeDef
-{
- USART_TypeDef *Instance; /*!< UART registers base address */
-
- UART_InitTypeDef Init; /*!< UART communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
-
- __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
-
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< UART Error code */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
- void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
- void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
- void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
- void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
- void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
- void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
- void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
- void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
- void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
-
- void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
- void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL UART Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
- HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
- HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
- HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
- HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
- HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
- HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
- HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
- HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
-
- HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
- HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
- * @brief HAL UART Callback pointer definition
- */
-typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
-typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
- * @{
- */
-
-/** @defgroup UART_Error_Code UART Error Code
- * @{
- */
-#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup UART_Word_Length UART Word Length
- * @{
- */
-#define UART_WORDLENGTH_8B 0x00000000U
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
- * @{
- */
-#define UART_STOPBITS_1 0x00000000U
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-/**
- * @}
- */
-
-/** @defgroup UART_Parity UART Parity
- * @{
- */
-#define UART_PARITY_NONE 0x00000000U
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
- * @{
- */
-#define UART_HWCONTROL_NONE 0x00000000U
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
- * @}
- */
-
-/** @defgroup UART_Mode UART Transfer Mode
- * @{
- */
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup UART_State UART State
- * @{
- */
-#define UART_STATE_DISABLE 0x00000000U
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
-/**
- * @}
- */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
- * @{
- */
-#define UART_OVERSAMPLING_16 0x00000000U
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
-/**
- * @}
- */
-
-/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_functions UART Wakeup Functions
- * @{
- */
-#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
-/**
- * @}
- */
-
-/** @defgroup UART_Flags UART FLags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask (16 bits) in the Y register
- * - Y : Interrupt source register (2bits)
- * - 0001: CR1 register
- * - 0010: CR2 register
- * - 0011: CR3 register
- * @{
- */
-
-#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
- * @{
- */
-#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
-#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
- * @{
- */
-
-/** @brief Reset UART handle gstate & RxState
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief Flushes the UART DR register
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Checks whether the specified UART flag is set or not.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TXE: Transmit data register empty flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_RXNE: Receive data register not empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: Overrun Error flag
- * @arg UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the specified UART pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg UART_FLAG_LBD: LIN Break detection flag.
- * @arg UART_FLAG_TC: Transmission Complete flag.
- * @arg UART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- *
- * @retval None
- */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clears the UART PE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clears the UART FE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART NE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART ORE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART IDLE pending flag.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__ specifies the UART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__ specifies the UART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief Checks whether the specified UART interrupt source is enabled or not.
- * @param __HANDLE__ specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __IT__ specifies the UART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ERR: Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief Enable CTS flow control
- * @note This macro allows to enable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0U)
-
-/** @brief Disable CTS flow control
- * @note This macro allows to disable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0U)
-
-/** @brief Enable RTS flow control
- * This macro allows to enable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0U)
-
-/** @brief Disable RTS flow control
- * This macro allows to disable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__ specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0U)
-
-/** @brief Macro to enable the UART's one bit sample method
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief Macro to disable the UART's one bit sample method
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief Enable UART
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
-
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
- * @{
- */
-/** @brief UART interruptions flag mask
- *
- */
-#define UART_IT_MASK 0x0000FFFFU
-
-#define UART_CR1_REG_INDEX 1U
-#define UART_CR2_REG_INDEX 2U
-#define UART_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
- ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
- (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h
deleted file mode 100644
index 2d046e4d5f..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_usart.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_usart.h
- * @author MCD Application Team
- * @brief Header file of USART HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_HAL_USART_H
-#define __STM32F2xx_HAL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-} HAL_USART_StateTypeDef;
-
-/**
- * @brief USART handle Structure definition
- */
-typedef struct __USART_HandleTypeDef
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- USART_InitTypeDef Init; /*!< Usart communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< Usart Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< Usart Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code */
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
- void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
- void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
- void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
- void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
- void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
- void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
- void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
-
- void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
- void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-} USART_HandleTypeDef;
-
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL USART Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
- HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
- HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
- HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
- HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
- HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
- HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
-
- HAL_USART_MSPINIT_CB_ID = 0x07U, /*!< USART MspInit callback ID */
- HAL_USART_MSPDEINIT_CB_ID = 0x08U /*!< USART MspDeInit callback ID */
-
-} HAL_USART_CallbackIDTypeDef;
-
-/**
- * @brief HAL USART Callback pointer definition
- */
-typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
-
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_Error_Code USART Error Code
- * @brief USART Error Code
- * @{
- */
-#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define HAL_USART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/** @defgroup USART_Word_Length USART Word Length
- * @{
- */
-#define USART_WORDLENGTH_8B 0x00000000U
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
- * @{
- */
-#define USART_STOPBITS_1 0x00000000U
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity USART Parity
- * @{
- */
-#define USART_PARITY_NONE 0x00000000U
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode USART Mode
- * @{
- */
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock USART Clock
- * @{
- */
-#define USART_CLOCK_DISABLE 0x00000000U
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
- * @{
- */
-#define USART_POLARITY_LOW 0x00000000U
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
- * @{
- */
-#define USART_PHASE_1EDGE 0x00000000U
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit USART Last Bit
- * @{
- */
-#define USART_LASTBIT_DISABLE 0x00000000U
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-/**
- * @}
- */
-
-/** @defgroup USART_NACK_State USART NACK State
- * @{
- */
-#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * @{
- */
-#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @brief Reset USART handle state
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_USART_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0U)
-#else
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/** @brief Check whether the specified USART flag is set or not.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: Overrun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified USART pending flags.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- *
- * @retval None
- */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the USART PE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the USART FE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART NE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART ORE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART IDLE pending flag.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enables or disables the specified USART interrupts.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__ specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
- */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __IT__ specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ERR: Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-
-/** @brief Macro to enable the USART's one bit sample method
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 |= USART_CR3_ONEBIT)
-
-/** @brief Macro to disable the USART's one bit sample method
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief Enable USART
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable USART
- * @param __HANDLE__ specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
- * @{
- */
-/** @brief USART interruptions flag mask
- *
- */
-#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-#define USART_CR1_REG_INDEX 1U
-#define USART_CR2_REG_INDEX 2U
-#define USART_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
- ((NACK) == USART_NACK_DISABLE))
-
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || \
- ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || \
- ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
- ((CLOCK) == USART_CLOCK_ENABLE))
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00U))
-
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 7500000U)
-
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
-
-#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
-
- /* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-
-#define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
- (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h
deleted file mode 100644
index 8378987b04..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal_wwdg.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_HAL_WWDG_H
-#define STM32F2xx_HAL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
- * @{
- */
-
-/**
- * @brief WWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
- This parameter can be a value of @ref WWDG_Prescaler */
-
- uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
- This parameter can be a value of @ref WWDG_EWI_Mode */
-
-} WWDG_InitTypeDef;
-
-/**
- * @brief WWDG handle Structure definition
- */
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-typedef struct __WWDG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-{
- WWDG_TypeDef *Instance; /*!< Register base address */
-
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
- void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
-
- void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-} WWDG_HandleTypeDef;
-
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-/**
- * @brief HAL WWDG common Callback ID enumeration definition
- */
-typedef enum
-{
- HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
- HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
-} HAL_WWDG_CallbackIDTypeDef;
-
-/**
- * @brief HAL WWDG Callback pointer definition
- */
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
-
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
- * @{
- */
-#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
- * @brief WWDG Flag definition
- * @{
- */
-#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
- * @{
- */
-#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
- * @}
- */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
- * @{
- */
-#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
-#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
- * @{
- */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
- ((__MODE__) == WWDG_EWI_DISABLE))
-/**
- * @}
- */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the WWDG peripheral.
- * @param __HANDLE__ WWDG handle
- * @retval None
- */
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
- * @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__ specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
- * @brief Check whether the selected WWDG interrupt has occurred or not.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the it to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief Clear the WWDG interrupt pending bits.
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified WWDG flag is set or not.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the WWDG's pending flags.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval None
- */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Check whether the specified WWDG interrupt source is enabled or not.
- * @param __HANDLE__ WWDG Handle.
- * @param __INTERRUPT__ specifies the WWDG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early Wakeup Interrupt
- * @retval state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
- & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/* Callbacks Register/UnRegister functions ***********************************/
-#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
- pWWDG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
-
-/**
- * @}
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_adc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_adc.h
deleted file mode 100644
index bab62e4a34..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_adc.h
+++ /dev/null
@@ -1,4622 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_ADC_H
-#define __STM32F2xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (ADC1) || defined (ADC2) || defined (ADC3)
-
-/** @defgroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Internal mask for ADC group regular sequencer: */
-/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
-/* - sequencer register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group regular sequencer configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET 0x00000000U
-#define ADC_SQR2_REGOFFSET 0x00000100U
-#define ADC_SQR3_REGOFFSET 0x00000200U
-#define ADC_SQR4_REGOFFSET 0x00000300U
-
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
-#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group regular sequencer bits information to be inserted */
-/* into ADC group regular sequencer ranks literals definition. */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
-
-/* Internal mask for ADC group injected sequencer: */
-/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
-/* - data register offset */
-/* - offset register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group injected data register */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET 0x00000000U
-#define ADC_JDR2_REGOFFSET 0x00000100U
-#define ADC_JDR3_REGOFFSET 0x00000200U
-#define ADC_JDR4_REGOFFSET 0x00000300U
-
-/* Internal register offset for ADC group injected offset configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JOFR1_REGOFFSET 0x00000000U
-#define ADC_JOFR2_REGOFFSET 0x00001000U
-#define ADC_JOFR3_REGOFFSET 0x00002000U
-#define ADC_JOFR4_REGOFFSET 0x00003000U
-
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
-#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
-#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Internal mask for ADC group regular trigger: */
-/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
-/* - regular trigger source */
-/* - regular trigger edge */
-#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
- ((ADC_CR2_EXTSEL) >> (4U * 3U)))
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
- ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
-
-/* Definition of ADC group regular trigger bits information. */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
-
-
-
-/* Internal mask for ADC group injected trigger: */
-/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
-/* - injected trigger source */
-/* - injected trigger edge */
-#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
-
-/* Mask containing trigger source masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
- ((ADC_CR2_JEXTSEL) >> (4U * 3U)))
-
-/* Mask containing trigger edge masks for each of possible */
-/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
-/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
-#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
- ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)))
-
-/* Definition of ADC group injected trigger bits information. */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
-
-/* Internal mask for ADC channel: */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
-/* - channel identifier defined by number */
-/* - channel differentiation between external channels (connected to */
-/* GPIO pins) and internal channels (connected to internal paths) */
-/* - channel sampling time defined by SMPRx register offset */
-/* and SMPx bits positions into SMPRx register */
-#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
-#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
-
-/* Internal register offset for ADC channel sampling time configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET 0x00000000U
-#define ADC_SMPR2_REGOFFSET 0x02000000U
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
-
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
-
-/* Definition of channels ID number information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_NUMBER 0x00000000U
-#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
-
-/* Definition of channels sampling time information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
-#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
-#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
-#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
-#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
-#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
-#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
-#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
-#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
-#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
-#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
-#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
-#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
-#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
-#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
-#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
-#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
-#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
-#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
-
-/* Internal mask for ADC analog watchdog: */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
-/* (concatenation of multiple bits used in different analog watchdogs, */
-/* (feature of several watchdogs not available on all STM32 families)). */
-/* - analog watchdog 1: monitored channel defined by number, */
-/* selection of ADC group (ADC groups regular and-or injected). */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET 0x00000000U
-
-#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
-#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
-#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
-
-/* ADC registers bits positions */
-#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
-#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
- */
-#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
- */
-#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of ADC common parameters
- * and multimode
- * (all ADC instances belonging to the same ADC common instance).
- * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
- * is conditioned to ADC instances state (all ADC instances
- * sharing the same ADC common instance):
- * All ADC instances sharing the same ADC common instance must be
- * disabled.
- */
-typedef struct
-{
- uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
- This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
-
- uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
- This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
-
- uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
- This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
-
- uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
- This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
-
-} LL_ADC_CommonInitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t Resolution; /*!< Set ADC resolution.
- This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
-
- uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
- This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
-
- uint32_t SequencersScanMode; /*!< Set ADC scan selection.
- This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 series, setting of external trigger edge is performed
- using function @ref LL_ADC_REG_StartConversionExtTrig().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
- @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group regular sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
- This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
- Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
- This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 series, setting of external trigger edge is performed
- using function @ref LL_ADC_INJ_StartConversionExtTrig().
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
- @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group injected sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
-
- uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
- Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
-
-} LL_ADC_INJ_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
- * @brief Flags defines which can be used with LL_ADC_ReadReg function
- * @{
- */
-#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
-#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
-#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
-#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
-#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
-#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
-#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
-#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
-#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
-#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
- * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
- * @{
- */
-#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
-#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
-#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
- * @{
- */
-/* List of ADC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
-#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
- * @{
- */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
-#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
- * @{
- */
-/* Note: Other measurement paths to internal channels may be available */
-/* (connections to other peripherals). */
-/* If they are not listed below, they do not require any specific */
-/* path enable. In this case, Access to measurement path is done */
-/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
-#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
- * @{
- */
-#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
-#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
-#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
-#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
- * @{
- */
-#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
- * @{
- */
-#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
-#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
- * @{
- */
-#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
- * @{
- */
-#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
-#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F2, ADC channel available only on ADC instance: ADC1. */
-#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F2, ADC channel available only on ADC instance: ADC1. */
-#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F2, ADC channel available only on ADC instance: ADC1. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
- * @{
- */
-#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
- * @{
- */
-#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
-* @{
-*/
-#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
- * @{
- */
-#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
- * @{
- */
-#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */
-#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
- * @{
- */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
-#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- * @{
- */
-#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
-#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
-#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
-#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
-#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
-#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
-#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
-#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
-#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
-#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
-#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
-#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
-#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
-#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
-#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
-#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
- * @{
- */
-#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
- * @{
- */
-#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
-#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
-#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
-* @{
-*/
-#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
-#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
-/**
- * @}
- */
-
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
- * @{
- */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
-#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- * @{
- */
-#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
-#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
-#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
-#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- * @{
- */
-#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- * @{
- */
-#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
- * @{
- */
-#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
-#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
-#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
-#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
-#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
- * @{
- */
-#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
-#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
-#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
-#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
-#if defined(ADC3)
-#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
-#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
-#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
-#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
-#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
-#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
- * @{
- */
-#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
-#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
-#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
- * @{
- */
-#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
-#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
-#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
- * @{
- */
-#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
-#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
-#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
-/**
- * @}
- */
-
-
-
-/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
- * @note Only ADC IP HW delays are defined in ADC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
-/* not timeout values. */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 series: */
-/* - ADC enable time: maximum delay is 2us */
-/* (refer to device datasheet, parameter "tSTAB") */
-/* - ADC conversion time: duration depending on ADC clock and ADC */
-/* configuration. */
-/* (refer to device reference manual, section "Timing") */
-
-/* Delay for internal voltage reference stabilization time. */
-/* Delay set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay for temperature sensor stabilization time. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get ADC channel number in decimal format
- * from literals LL_ADC_CHANNEL_x.
- * @note Example:
- * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
- * will return decimal number "4".
- * @note The input can be a value from functions where a channel
- * number is returned, either defined with number
- * or with bitfield (only one bit must be set).
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- * @retval Value between Min_Data=0 and Max_Data=18
- */
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
-
-/**
- * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
- * from number in decimal format.
- * @note Example:
- * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- * will return a data equivalent to "LL_ADC_CHANNEL_4".
- * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9U) \
- ? ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- : \
- ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- )
-
-/**
- * @brief Helper macro to determine whether the selected channel
- * corresponds to literal definitions of driver.
- * @note The different literal definitions of ADC channels are:
- * - ADC internal channel:
- * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
- * - ADC external channel (channel connected to a GPIO pin):
- * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
- * @note The channel parameter must be a value defined from literal
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
- * must not be a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
- * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
-
-/**
- * @brief Helper macro to convert a channel defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * to its equivalent parameter definition of a ADC external channel
- * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
- * @note The channel parameter can be, additionally to a value
- * defined from parameter definition of a ADC internal channel
- * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is returned
- * from ADC registers.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
- * @brief Helper macro to determine whether the internal channel
- * selected is available on the ADC instance selected.
- * @note The channel parameter must be a value defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * must not be a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __ADC_INSTANCE__ ADC instance
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.
- * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
- * Value "1" if the internal channel selected is available on the ADC instance selected.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
- )
-/**
- * @brief Helper macro to define ADC analog watchdog parameter:
- * define a single channel to monitor with analog watchdog
- * from sequencer channel and groups definition.
- * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
- * Example:
- * LL_ADC_SetAnalogWDMonitChannels(
- * ADC1, LL_ADC_AWD1,
- * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_18
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- * @arg @ref LL_ADC_CHANNEL_VBAT (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- * @param __GROUP__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_GROUP_REGULAR
- * @arg @ref LL_ADC_GROUP_INJECTED
- * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
- *
- * (1) On STM32F2, parameter available only on ADC instance: ADC1.\n
- */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
- (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
- : \
- ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
- : \
- (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
- )
-
-/**
- * @brief Helper macro to set the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to set the value of
- * analog watchdog threshold high (on 8 bits):
- * LL_ADC_SetAnalogWDThresholds
- * (< ADCx param >,
- * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_BUS_H
-#define __STM32F2xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- * @{
- */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- * @{
- */
-#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
-#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
-#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
-#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
-#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
-#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
-#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
-#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
-#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
-#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
-#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
-#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
-#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
-#if defined(ETH)
-#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
-#endif /* ETH */
-#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
-#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
-#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
-#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
-#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
- * @{
- */
-#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#if defined(DCMI)
-#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
-#endif /* DCMI */
-#if defined(CRYP)
-#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
-#endif /* CRYP */
-#if defined(HASH)
-#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
-#endif /* HASH */
-#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
-#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
- * @{
- */
-#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- * @{
- */
-#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
-#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
-#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
-#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
-#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
-#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
-#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
-#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
-#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
-#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
-#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
-#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
-#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
-#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
-#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
-#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
-#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
-#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
-#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
-#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
-#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- * @{
- */
-#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
-#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
-#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
-#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
-#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
-#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
-#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
-#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
-#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
-#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
-#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
-#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
-#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- * @{
- */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
- * @{
- */
-
-/**
- * @brief Enable AHB1 peripherals clock.
- * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
- * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB1 peripheral clock is enabled or not
- * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB1 peripherals clock.
- * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
- * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB1ENR, Periphs);
-}
-
-/**
- * @brief Force AHB1 peripherals reset.
- * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
- * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB1 peripherals reset.
- * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
- * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB1 peripheral clocks in low-power mode
- * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
- * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB1LPENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB1 peripheral clocks in low-power mode
- * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
- * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
- * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB1LPENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_AHB2 AHB2
- * @{
- */
-
-/**
- * @brief Enable AHB2 peripherals clock.
- * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
- * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB2 peripheral clock is enabled or not
- * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
- * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB2 peripherals clock.
- * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
- * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB2ENR, Periphs);
-}
-
-/**
- * @brief Force AHB2 peripherals reset.
- * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
- * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB2 peripherals reset.
- * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
- * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB2 peripheral clocks in low-power mode
- * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
- * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
- * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
- * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
- * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB2LPENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB2 peripheral clocks in low-power mode
- * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
- * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
- * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
- * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
- * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
- * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
- * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB2LPENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_AHB3 AHB3
- * @{
- */
-
-/**
- * @brief Enable AHB3 peripherals clock.
- * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB3ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB3 peripheral clock is enabled or not
- * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB3 peripherals clock.
- * @rmtoll AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB3ENR, Periphs);
-}
-
-/**
- * @brief Force AHB3 peripherals reset.
- * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
- * @brief Release AHB3 peripherals reset.
- * @rmtoll AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
- * @brief Enable AHB3 peripheral clocks in low-power mode
- * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHB3LPENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable AHB3 peripheral clocks in low-power mode
- * @rmtoll AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHB3LPENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
- * @{
- */
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @brief Enable APB1 peripheral clocks in low-power mode
- * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
- * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1LPENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable APB1 peripheral clocks in low-power mode
- * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
- * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1LPENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
- * @{
- */
-
-/**
- * @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
- * @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Enable APB2 peripheral clocks in low-power mode
- * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
- * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2LPENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Disable APB2 peripheral clocks in low-power mode
- * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
- * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- * @arg @ref LL_APB2_GRP1_PERIPH_USART6
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
- * @arg @ref LL_APB2_GRP1_PERIPH_SDIO
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2LPENR, Periphs);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_cortex.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_cortex.h
deleted file mode 100644
index ac38900454..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_cortex.h
+++ /dev/null
@@ -1,640 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL CORTEX driver contains a set of generic APIs that can be
- used by user:
- (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
- functions
- (+) Low power mode configuration (SCB register of Cortex-MCU)
- (+) MPU API to configure and enable regions
- (MPU services provided only on some devices)
- (+) API to access to MCU info (CPUID register)
- (+) API to enable fault handler (SHCSR accesses)
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_CORTEX_H
-#define __STM32F2xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-/** @defgroup CORTEX_LL CORTEX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
- * @{
- */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
- * @{
- */
-#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
- * @{
- */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
- * @{
- */
-#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
- * @{
- */
-#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
- * @{
- */
-#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
- * @{
- */
-#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
- * @{
- */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
- * @{
- */
-#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
- * @{
- */
-#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
- * @{
- */
-#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
- * @{
- */
-
-/**
- * @brief This function checks if the Systick counter flag is active or not.
- * @note It can be used in timeout function on application side.
- * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
- return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
- * @brief Configures the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
- if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
- {
- SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
- else
- {
- CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
-}
-
-/**
- * @brief Get the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
- return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Disable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Checks if the SYSTICK interrupt is enabled or disabled.
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
- return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
- * @{
- */
-
-/**
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Processor uses deep sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
- * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
- * empty main application.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Do not sleep when returning to Thread mode.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
- * processor.
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
- /* Set SEVEONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
- * excluded
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
- /* Clear SEVEONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
- * @{
- */
-
-/**
- * @brief Enable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
- /* Enable the system handler fault */
- SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @brief Disable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
- /* Disable the system handler fault */
- CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
- * @{
- */
-
-/**
- * @brief Get Implementer code
- * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
- * @retval Value should be equal to 0x41 for ARM
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
- * @brief Get Variant number (The r value in the rnpn product revision identifier)
- * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
- * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
- * @brief Get Constant number
- * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
- * @retval Value should be equal to 0xF for Cortex-M3 devices
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
- * @brief Get Part number
- * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
- * @retval Value should be equal to 0xC23 for Cortex-M3
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
- * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
- * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
- * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
- * @{
- */
-
-/**
- * @brief Enable MPU with input options
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
- * @param Options This parameter can be one of the following values:
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
- * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
- * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
- /* Enable the MPU*/
- WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
- /* Ensure MPU settings take effects */
- __DSB();
- /* Sequence instruction fetches using update settings */
- __ISB();
-}
-
-/**
- * @brief Disable MPU
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
- /* Disable MPU*/
- WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
- * @brief Check if MPU is enabled or not
- * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
- return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
- * @brief Enable a MPU region
- * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Enable the MPU region */
- SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @brief Configure and enable a region
- * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
- * MPU_RASR XN LL_MPU_ConfigRegion\n
- * MPU_RASR AP LL_MPU_ConfigRegion\n
- * MPU_RASR S LL_MPU_ConfigRegion\n
- * MPU_RASR C LL_MPU_ConfigRegion\n
- * MPU_RASR B LL_MPU_ConfigRegion\n
- * MPU_RASR SIZE LL_MPU_ConfigRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @param Address Value of region base address
- * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
- * @param Attributes This parameter can be a combination of the following values:
- * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
- * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
- * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
- * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
- * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
- * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
- * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
- * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
- * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
- * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
- * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
- * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Set base address */
- WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
- /* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
- * @brief Disable a region
- * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
- * MPU_RASR ENABLE LL_MPU_DisableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Disable the MPU region */
- CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @}
- */
-
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_crc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_crc.h
deleted file mode 100644
index a49710b550..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_crc.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_CRC_H
-#define STM32F2xx_LL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(CRC)
-
-/** @defgroup CRC_LL CRC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
-
-/**
- * @brief Read a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
- * @{
- */
-
-/**
- * @brief Reset the CRC calculation unit.
- * @note If Programmable Initial CRC value feature
- * is available, also set the Data Register to the value stored in the
- * CRC_INIT register, otherwise, reset Data Register to its default value.
- * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
- * @param CRCx CRC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
-{
- SET_BIT(CRCx->CR, CRC_CR_RESET);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Write given 32-bit data to the CRC calculator
- * @rmtoll DR DR LL_CRC_FeedData32
- * @param CRCx CRC Instance
- * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
-{
- WRITE_REG(CRCx->DR, InData);
-}
-
-/**
- * @brief Return current CRC calculation result. 32 bits value is returned.
- * @rmtoll DR DR LL_CRC_ReadData32
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
- */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->DR));
-}
-
-/**
- * @brief Return data stored in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Read_IDR
- * @param CRCx CRC Instance
- * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
- */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->IDR));
-}
-
-/**
- * @brief Store data in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Write_IDR
- * @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
-{
- *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
-}
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(CRC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dac.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dac.h
deleted file mode 100644
index 9ae810395d..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dac.h
+++ /dev/null
@@ -1,1339 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_DAC_H
-#define STM32F2xx_LL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(DAC)
-
-/** @defgroup DAC_LL DAC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Constants DAC Private Constants
- * @{
- */
-
-/* Internal masks for DAC channels definition */
-/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
-/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
-/* - channel bits position into register SWTRIG */
-/* - channel register offset of data holding register DHRx */
-/* - channel register offset of data output register DORx */
-#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
- CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
- CR, MCR, CCR, SHHR, SHRR of channel 2 */
-#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
-
-#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
-#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
-#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
-
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
- DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
- DHR12Rx channel 1 (shifted left of 24 bits) */
-
-#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
- DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
- DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
- DHR12Rx channel 1 (shifted left of 24 bits) */
-
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
- | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-
-#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
-
-#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
- DORx channel 2 (shifted left of 28 bits) */
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
-
-
-#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
- DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
-#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
- to position 0 */
-#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
- to position 0 */
-
-#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
- channel 1 or 2 versus DHR12Rx channel 1
- (shifted left of 16 bits) */
-#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
- channel 1 or 2 versus DHR12Rx channel 1
- (shifted left of 20 bits) */
-#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
- channel 1 or 2 versus DHR12Rx channel 1
- (shifted left of 24 bits) */
-#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
- channel 1 or 2 versus DORx channel 1
- (shifted left of 28 bits) */
-
-/* DAC registers bits positions */
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
-
-/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
- bits (voltage range determined by analog voltage
- references Vref+ and Vref-, refer to reference manual) */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Macros DAC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
- */
-#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of DAC instance.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
- internal (SW start) or from external peripheral
- (timer event, external interrupt line).
- This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
- This feature can be modified afterwards using unitary
- function @ref LL_DAC_SetTriggerSource(). */
-
- uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
- This feature can be modified afterwards using unitary
- function @ref LL_DAC_SetWaveAutoGeneration(). */
-
- uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter
- can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle,
- this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled,
- this parameter is discarded.
-
- This feature can be modified afterwards using unitary
- function @ref LL_DAC_SetWaveNoiseLFSR(),
- @ref LL_DAC_SetWaveTriangleAmplitude()
- depending on the wave automatic generation selected. */
-
- uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
- This feature can be modified afterwards using unitary
- function @ref LL_DAC_SetOutputBuffer(). */
-} LL_DAC_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
- * @brief Flags defines which can be used with LL_DAC_ReadReg function
- * @{
- */
-/* DAC channel 1 flags */
-#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
-
-/* DAC channel 2 flags */
-#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_IT DAC interruptions
- * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
- * @{
- */
-#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
-
-#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_CHANNEL DAC channels
- * @{
- */
-#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
-
-#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
- * @{
- */
-#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
- * @{
- */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
- * @{
- */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
- * @{
- */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
- * @{
- */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
-#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
- * @{
- */
-#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
- * @{
- */
-/* List of DAC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Delay for DAC channel voltage settling time from DAC channel startup */
-/* (transition from disable to enable). */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm (min), 50pF (max) */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tWAKEUP"). */
-/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
-/* Delay for DAC channel voltage settling time. */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm min, 50pF max */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSETTLING"). */
-/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
- * @{
- */
-
-/**
- * @brief Write a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get DAC channel number in decimal format
- * from literals LL_DAC_CHANNEL_x.
- * Example:
- * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
- * will return decimal number "1".
- * @note The input can be a value from functions where a channel
- * number is returned.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval 1...2
- */
-#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
-
-/**
- * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
- * from number in decimal format.
- * Example:
- * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
- * will return a data equivalent to "LL_DAC_CHANNEL_1".
- * @note If the input parameter does not correspond to a DAC channel,
- * this macro returns value '0'.
- * @param __DECIMAL_NB__ 1...2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- */
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
- (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
-
-/**
- * @brief Helper macro to define the DAC conversion data full-scale digital
- * value corresponding to the selected DAC resolution.
- * @note DAC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
-
-/**
- * @brief Helper macro to calculate the DAC conversion data (unit: digital
- * value) corresponding to a voltage (unit: mVolt).
- * @note This helper macro is intended to provide input data in voltage
- * rather than digital value,
- * to be used with LL DAC functions such as
- * @ref LL_DAC_ConvertData12RightAligned().
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
- * (unit: mVolt).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval DAC conversion data (unit: digital value)
- */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
- __DAC_VOLTAGE__,\
- __DAC_RESOLUTION__) \
-((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
-)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
- * @{
- */
-/**
- * @brief Set the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note To set conversion trigger source, DAC channel must be disabled.
- * Otherwise, the setting is discarded.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
- * CR TSEL2 LL_DAC_SetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
- * CR TSEL2 LL_DAC_GetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_SetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param WaveAutoGeneration This parameter can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_GetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param NoiseLFSRMask This parameter can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param TriangleAmplitude This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
- uint32_t TriangleAmplitude)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the output buffer for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
- * CR BOFF2 LL_DAC_SetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param OutputBuffer This parameter can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the output buffer state for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
- * CR BOFF2 LL_DAC_GetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
- * CR DMAEN2 LL_DAC_EnableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
- * CR DMAEN2 LL_DAC_DisableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC DMA transfer request state of the selected channel.
- * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
- * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
- * CR DMAEN2 LL_DAC_IsDMAReqEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return ((READ_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
- * @brief Function to help to configure DMA transfer to DAC: retrieve the
- * DAC register address from DAC instance and a list of DAC registers
- * intended to be used (most commonly) with DMA transfer.
- * @note These DAC registers are data holding registers:
- * when DAC conversion is requested, DAC generates a DMA transfer
- * request to have data available in DAC data holding registers.
- * @note This macro is intended to be used with LL DMA driver, refer to
- * function "LL_DMA_ConfigAddresses()".
- * Example:
- * LL_DMA_ConfigAddresses(DMA1,
- * LL_DMA_CHANNEL_1,
- * (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
- * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Register This parameter can be one of the following values:
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
- * @retval DAC register address
- */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
-{
- /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
- /* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
- & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
- * @{
- */
-
-/**
- * @brief Enable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Enable\n
- * CR EN2 LL_DAC_Enable
- * @note After enable from off state, DAC channel requires a delay
- * for output voltage to reach accuracy +/- 1 LSB.
- * Refer to device datasheet, parameter "tWAKEUP".
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Disable\n
- * CR EN2 LL_DAC_Disable
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC enable state of the selected channel.
- * (0: DAC channel is disabled, 1: DAC channel is enabled)
- * @rmtoll CR EN1 LL_DAC_IsEnabled\n
- * CR EN2 LL_DAC_IsEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return ((READ_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable DAC trigger of the selected channel.
- * @note - If DAC trigger is disabled, DAC conversion is performed
- * automatically once the data holding register is updated,
- * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...
- * - If DAC trigger is enabled, DAC conversion is performed
- * only when a hardware of software trigger event is occurring.
- * Select trigger source using
- * function @ref LL_DAC_SetTriggerSource().
- * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
- * CR TEN2 LL_DAC_EnableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC trigger of the selected channel.
- * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
- * CR TEN2 LL_DAC_DisableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC trigger state of the selected channel.
- * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
- * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
- * CR TEN2 LL_DAC_IsTriggerEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return ((READ_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
-}
-
-/**
- * @brief Trig DAC conversion by software for the selected DAC channel.
- * @note Preliminarily, DAC trigger must be set to software trigger
- * using function
- * @ref LL_DAC_Init()
- * @ref LL_DAC_SetTriggerSource()
- * with parameter "LL_DAC_TRIGGER_SOFTWARE".
- * and DAC trigger must be enabled using
- * function @ref LL_DAC_EnableTrigger().
- * @note For devices featuring DAC with 2 channels: this function
- * can perform a SW start of both DAC channels simultaneously.
- * Two channels can be selected as parameter.
- * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
- * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
- * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can a combination of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->SWTRIGR,
- (DAC_Channel & DAC_SWTR_CHX_MASK));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
- * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
- & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
- MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for the selected DAC channel.
- * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
- * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
- & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
- MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
- * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
- & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
-
- MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
-}
-
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
- * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
- uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR12RD,
- (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for both DAC channels.
- * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
- * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
- uint32_t DataChannel2)
-{
- /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
- /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
- /* the 4 LSB must be taken into account for the shift value. */
- MODIFY_REG(DACx->DHR12LD,
- (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
- ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
- * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
- * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
- uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR8RD,
- (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-
-/**
- * @brief Retrieve output data currently generated for the selected DAC channel.
- * @note Whatever alignment and resolution settings
- * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...),
- * output data format is 12 bits right aligned (LSB aligned on bit 0).
- * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
- * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
- & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
-
- return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Get DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
-}
-
-
-/**
- * @brief Get DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
-}
-
-
-/**
- * @brief Clear DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
-}
-
-
-/**
- * @brief Clear DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_IT_Management IT management
- * @{
- */
-
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-
-
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-
-
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-
-
-/**
- * @brief Get DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
-}
-
-
-/**
- * @brief Get DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
-}
-
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
-void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dma.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dma.h
deleted file mode 100644
index 8a45b4b92c..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_dma.h
+++ /dev/null
@@ -1,2860 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_DMA_H
-#define __STM32F2xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
- * @{
- */
-/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
-static const uint8_t STREAM_OFFSET_TAB[] =
-{
- (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
-};
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Constants DMA Private Constants
- * @{
- */
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- or as Source base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Stream
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
- uint32_t Channel; /*!< Specifies the peripheral channel.
- This parameter can be a value of @ref DMA_LL_EC_CHANNEL
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
-
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
-
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
- This parameter can be a value of @ref DMA_LL_FIFOMODE
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected stream
-
- This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
-
- uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
-
- uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_LL_EC_MBURST
- @note The burst mode is possible only if the address Increment mode is enabled.
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
-
- uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_LL_EC_PBURST
- @note The burst mode is possible only if the address Increment mode is enabled.
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
-
-} LL_DMA_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_LL_EC_STREAM STREAM
- * @{
- */
-#define LL_DMA_STREAM_0 0x00000000U
-#define LL_DMA_STREAM_1 0x00000001U
-#define LL_DMA_STREAM_2 0x00000002U
-#define LL_DMA_STREAM_3 0x00000003U
-#define LL_DMA_STREAM_4 0x00000004U
-#define LL_DMA_STREAM_5 0x00000005U
-#define LL_DMA_STREAM_6 0x00000006U
-#define LL_DMA_STREAM_7 0x00000007U
-#define LL_DMA_STREAM_ALL 0xFFFF0000U
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
- * @{
- */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MODE MODE
- * @{
- */
-#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
-#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
-#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
- * @{
- */
-#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
-#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PERIPH PERIPH
- * @{
- */
-#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
-#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MEMORY MEMORY
- * @{
- */
-#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
-#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
- * @{
- */
-#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
-#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
- * @{
- */
-#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
- * @{
- */
-#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
-#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
- * @{
- */
-#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
-#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
-#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- * @{
- */
-#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
-#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
-#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
-#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
-#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
-#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
-#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
-#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MBURST MBURST
- * @{
- */
-#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
-#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
-#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
-#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PBURST PBURST
- * @{
- */
-#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
-#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
-#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
-#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
- * @{
- */
-#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
-#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
- * @{
- */
-#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
-#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
-#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
-#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
-#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
-#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
- * @{
- */
-#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
-#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
-#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
-#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
- * @{
- */
-#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
-#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
- * @{
- */
-/**
- * @brief Convert DMAx_Streamy into DMAx
- * @param __STREAM_INSTANCE__ DMAx_Streamy
- * @retval DMAx
- */
-#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
-(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
-
-/**
- * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
- * @param __STREAM_INSTANCE__ DMAx_Streamy
- * @retval LL_DMA_CHANNEL_y
- */
-#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
-(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
- LL_DMA_STREAM_7)
-
-/**
- * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
- * @param __DMA_INSTANCE__ DMAx
- * @param __STREAM__ LL_DMA_STREAM_y
- * @retval DMAx_Streamy
- */
-#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
- DMA2_Stream7)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
- /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable DMA stream.
- * @rmtoll CR EN LL_DMA_EnableStream
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
-}
-
-/**
- * @brief Disable DMA stream.
- * @rmtoll CR EN LL_DMA_DisableStream
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
-}
-
-/**
- * @brief Check if DMA stream is enabled or disabled.
- * @rmtoll CR EN LL_DMA_IsEnabledStream
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
-}
-
-/**
- * @brief Configure all parameters linked to DMA transfer.
- * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
- * CR CIRC LL_DMA_ConfigTransfer\n
- * CR PINC LL_DMA_ConfigTransfer\n
- * CR MINC LL_DMA_ConfigTransfer\n
- * CR PSIZE LL_DMA_ConfigTransfer\n
- * CR MSIZE LL_DMA_ConfigTransfer\n
- * CR PL LL_DMA_ConfigTransfer\n
- * CR PFCTRL LL_DMA_ConfigTransfer
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
- * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
- * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
- * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
- *@retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
-{
- MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
- DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
- Configuration);
-}
-
-/**
- * @brief Set Data transfer direction (read from peripheral or from memory).
- * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
-}
-
-/**
- * @brief Get Data transfer direction (read from peripheral or from memory).
- * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
-}
-
-/**
- * @brief Set DMA mode normal, circular or peripheral flow control.
- * @rmtoll CR CIRC LL_DMA_SetMode\n
- * CR PFCTRL LL_DMA_SetMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_MODE_PFCTRL
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
-}
-
-/**
- * @brief Get DMA mode normal, circular or peripheral flow control.
- * @rmtoll CR CIRC LL_DMA_GetMode\n
- * CR PFCTRL LL_DMA_GetMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_MODE_PFCTRL
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
-}
-
-/**
- * @brief Set Peripheral increment mode.
- * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param IncrementMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
-}
-
-/**
- * @brief Get Peripheral increment mode.
- * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
-}
-
-/**
- * @brief Set Memory increment mode.
- * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param IncrementMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
-}
-
-/**
- * @brief Get Memory increment mode.
- * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
-}
-
-/**
- * @brief Set Peripheral size.
- * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Size This parameter can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
-}
-
-/**
- * @brief Get Peripheral size.
- * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
-}
-
-/**
- * @brief Set Memory size.
- * @rmtoll CR MSIZE LL_DMA_SetMemorySize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Size This parameter can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
-}
-
-/**
- * @brief Get Memory size.
- * @rmtoll CR MSIZE LL_DMA_GetMemorySize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
-}
-
-/**
- * @brief Set Peripheral increment offset size.
- * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param OffsetSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
- * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
-}
-
-/**
- * @brief Get Peripheral increment offset size.
- * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
- * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
- */
-__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
-}
-
-/**
- * @brief Set Stream priority level.
- * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Priority This parameter can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
-}
-
-/**
- * @brief Get Stream priority level.
- * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- */
-__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
-}
-
-/**
- * @brief Set Number of data to transfer.
- * @rmtoll NDTR NDT LL_DMA_SetDataLength
- * @note This action has no effect if
- * stream is enabled.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param NbData Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
-}
-
-/**
- * @brief Get Number of data to transfer.
- * @rmtoll NDTR NDT LL_DMA_GetDataLength
- * @note Once the stream is enabled, the return value indicate the
- * remaining bytes to be transmitted.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
-}
-
-/**
- * @brief Select Channel number associated to the Stream.
- * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_0
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
-}
-
-/**
- * @brief Get the Channel number associated to the Stream.
- * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_0
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
-}
-
-/**
- * @brief Set Memory burst transfer configuration.
- * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Mburst This parameter can be one of the following values:
- * @arg @ref LL_DMA_MBURST_SINGLE
- * @arg @ref LL_DMA_MBURST_INC4
- * @arg @ref LL_DMA_MBURST_INC8
- * @arg @ref LL_DMA_MBURST_INC16
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
-}
-
-/**
- * @brief Get Memory burst transfer configuration.
- * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MBURST_SINGLE
- * @arg @ref LL_DMA_MBURST_INC4
- * @arg @ref LL_DMA_MBURST_INC8
- * @arg @ref LL_DMA_MBURST_INC16
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
-}
-
-/**
- * @brief Set Peripheral burst transfer configuration.
- * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Pburst This parameter can be one of the following values:
- * @arg @ref LL_DMA_PBURST_SINGLE
- * @arg @ref LL_DMA_PBURST_INC4
- * @arg @ref LL_DMA_PBURST_INC8
- * @arg @ref LL_DMA_PBURST_INC16
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
-}
-
-/**
- * @brief Get Peripheral burst transfer configuration.
- * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PBURST_SINGLE
- * @arg @ref LL_DMA_PBURST_INC4
- * @arg @ref LL_DMA_PBURST_INC8
- * @arg @ref LL_DMA_PBURST_INC16
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
-}
-
-/**
- * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
- * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param CurrentMemory This parameter can be one of the following values:
- * @arg @ref LL_DMA_CURRENTTARGETMEM0
- * @arg @ref LL_DMA_CURRENTTARGETMEM1
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
-}
-
-/**
- * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
- * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_CURRENTTARGETMEM0
- * @arg @ref LL_DMA_CURRENTTARGETMEM1
- */
-__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
-}
-
-/**
- * @brief Enable the double buffer mode.
- * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
-}
-
-/**
- * @brief Disable the double buffer mode.
- * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
-}
-
-/**
- * @brief Get FIFO status.
- * @rmtoll FCR FS LL_DMA_GetFIFOStatus
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_FIFOSTATUS_0_25
- * @arg @ref LL_DMA_FIFOSTATUS_25_50
- * @arg @ref LL_DMA_FIFOSTATUS_50_75
- * @arg @ref LL_DMA_FIFOSTATUS_75_100
- * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
- * @arg @ref LL_DMA_FIFOSTATUS_FULL
- */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
-}
-
-/**
- * @brief Disable Fifo mode.
- * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
- * @brief Enable Fifo mode.
- * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
- * @brief Select FIFO threshold.
- * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Threshold This parameter can be one of the following values:
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
- * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
-}
-
-/**
- * @brief Get FIFO threshold.
- * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
- * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
- */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
-}
-
-/**
- * @brief Configure the FIFO .
- * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
- * FCR DMDIS LL_DMA_ConfigFifo
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param FifoMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_FIFOMODE_ENABLE
- * @arg @ref LL_DMA_FIFOMODE_DISABLE
- * @param FifoThreshold This parameter can be one of the following values:
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
- * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
- * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
-}
-
-/**
- * @brief Configure the Source and Destination addresses.
- * @note This API must not be called when the DMA stream is enabled.
- * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
- * PAR PA LL_DMA_ConfigAddresses
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param SrcAddress Between 0 to 0xFFFFFFFF
- * @param DstAddress Between 0 to 0xFFFFFFFF
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
-{
- /* Direction Memory to Periph */
- if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
- {
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
- }
- /* Direction Periph to Memory and Memory to Memory */
- else
- {
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
- }
-}
-
-/**
- * @brief Set the Memory address.
- * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param MemoryAddress Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
-}
-
-/**
- * @brief Set the Peripheral address.
- * @rmtoll PAR PA LL_DMA_SetPeriphAddress
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param PeriphAddress Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
-{
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
-}
-
-/**
- * @brief Get the Memory address.
- * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
- return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
-}
-
-/**
- * @brief Get the Peripheral address.
- * @rmtoll PAR PA LL_DMA_GetPeriphAddress
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
- return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
-}
-
-/**
- * @brief Set the Memory to Memory Source address.
- * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param MemoryAddress Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Memory to Memory Destination address.
- * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param MemoryAddress Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
- {
- WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
- }
-
-/**
- * @brief Get the Memory to Memory Source address.
- * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
- {
- return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
- }
-
-/**
- * @brief Get the Memory to Memory Destination address.
- * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
- return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
-}
-
-/**
- * @brief Set Memory 1 address (used in case of Double buffer mode).
- * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @param Address Between 0 to 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
-{
- MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
-}
-
-/**
- * @brief Get Memory 1 address (used in case of Double buffer mode).
- * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval Between 0 to 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Stream 0 half transfer flag.
- * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
-}
-
-/**
- * @brief Get Stream 1 half transfer flag.
- * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
-}
-
-/**
- * @brief Get Stream 2 half transfer flag.
- * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
-}
-
-/**
- * @brief Get Stream 3 half transfer flag.
- * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
-}
-
-/**
- * @brief Get Stream 4 half transfer flag.
- * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
-}
-
-/**
- * @brief Get Stream 5 half transfer flag.
- * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
-}
-
-/**
- * @brief Get Stream 6 half transfer flag.
- * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
-}
-
-/**
- * @brief Get Stream 7 half transfer flag.
- * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
-}
-
-/**
- * @brief Get Stream 0 transfer complete flag.
- * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
-}
-
-/**
- * @brief Get Stream 1 transfer complete flag.
- * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
-}
-
-/**
- * @brief Get Stream 2 transfer complete flag.
- * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
-}
-
-/**
- * @brief Get Stream 3 transfer complete flag.
- * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
-}
-
-/**
- * @brief Get Stream 4 transfer complete flag.
- * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
-}
-
-/**
- * @brief Get Stream 5 transfer complete flag.
- * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
-}
-
-/**
- * @brief Get Stream 6 transfer complete flag.
- * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
-}
-
-/**
- * @brief Get Stream 7 transfer complete flag.
- * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
-}
-
-/**
- * @brief Get Stream 0 transfer error flag.
- * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
-}
-
-/**
- * @brief Get Stream 1 transfer error flag.
- * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
-}
-
-/**
- * @brief Get Stream 2 transfer error flag.
- * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
-}
-
-/**
- * @brief Get Stream 3 transfer error flag.
- * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
-}
-
-/**
- * @brief Get Stream 4 transfer error flag.
- * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
-}
-
-/**
- * @brief Get Stream 5 transfer error flag.
- * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
-}
-
-/**
- * @brief Get Stream 6 transfer error flag.
- * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
-}
-
-/**
- * @brief Get Stream 7 transfer error flag.
- * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
-}
-
-/**
- * @brief Get Stream 0 direct mode error flag.
- * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
-}
-
-/**
- * @brief Get Stream 1 direct mode error flag.
- * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
-}
-
-/**
- * @brief Get Stream 2 direct mode error flag.
- * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
-}
-
-/**
- * @brief Get Stream 3 direct mode error flag.
- * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
-}
-
-/**
- * @brief Get Stream 4 direct mode error flag.
- * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
-}
-
-/**
- * @brief Get Stream 5 direct mode error flag.
- * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
-}
-
-/**
- * @brief Get Stream 6 direct mode error flag.
- * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
-}
-
-/**
- * @brief Get Stream 7 direct mode error flag.
- * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
-}
-
-/**
- * @brief Get Stream 0 FIFO error flag.
- * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
-}
-
-/**
- * @brief Get Stream 1 FIFO error flag.
- * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
-}
-
-/**
- * @brief Get Stream 2 FIFO error flag.
- * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
-}
-
-/**
- * @brief Get Stream 3 FIFO error flag.
- * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
-}
-
-/**
- * @brief Get Stream 4 FIFO error flag.
- * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
-}
-
-/**
- * @brief Get Stream 5 FIFO error flag.
- * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
-}
-
-/**
- * @brief Get Stream 6 FIFO error flag.
- * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
-}
-
-/**
- * @brief Get Stream 7 FIFO error flag.
- * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
-}
-
-/**
- * @brief Clear Stream 0 half transfer flag.
- * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
-}
-
-/**
- * @brief Clear Stream 1 half transfer flag.
- * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
-}
-
-/**
- * @brief Clear Stream 2 half transfer flag.
- * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
-}
-
-/**
- * @brief Clear Stream 3 half transfer flag.
- * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
-}
-
-/**
- * @brief Clear Stream 4 half transfer flag.
- * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
-}
-
-/**
- * @brief Clear Stream 5 half transfer flag.
- * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
-}
-
-/**
- * @brief Clear Stream 6 half transfer flag.
- * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
-}
-
-/**
- * @brief Clear Stream 7 half transfer flag.
- * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
-}
-
-/**
- * @brief Clear Stream 0 transfer complete flag.
- * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
-}
-
-/**
- * @brief Clear Stream 1 transfer complete flag.
- * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
-}
-
-/**
- * @brief Clear Stream 2 transfer complete flag.
- * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
-}
-
-/**
- * @brief Clear Stream 3 transfer complete flag.
- * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
-}
-
-/**
- * @brief Clear Stream 4 transfer complete flag.
- * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
-}
-
-/**
- * @brief Clear Stream 5 transfer complete flag.
- * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
-}
-
-/**
- * @brief Clear Stream 6 transfer complete flag.
- * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
-}
-
-/**
- * @brief Clear Stream 7 transfer complete flag.
- * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
-}
-
-/**
- * @brief Clear Stream 0 transfer error flag.
- * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
-}
-
-/**
- * @brief Clear Stream 1 transfer error flag.
- * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
-}
-
-/**
- * @brief Clear Stream 2 transfer error flag.
- * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
-}
-
-/**
- * @brief Clear Stream 3 transfer error flag.
- * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
-}
-
-/**
- * @brief Clear Stream 4 transfer error flag.
- * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
-}
-
-/**
- * @brief Clear Stream 5 transfer error flag.
- * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
-}
-
-/**
- * @brief Clear Stream 6 transfer error flag.
- * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
-}
-
-/**
- * @brief Clear Stream 7 transfer error flag.
- * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
-}
-
-/**
- * @brief Clear Stream 0 direct mode error flag.
- * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
-}
-
-/**
- * @brief Clear Stream 1 direct mode error flag.
- * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
-}
-
-/**
- * @brief Clear Stream 2 direct mode error flag.
- * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
-}
-
-/**
- * @brief Clear Stream 3 direct mode error flag.
- * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
-}
-
-/**
- * @brief Clear Stream 4 direct mode error flag.
- * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
-}
-
-/**
- * @brief Clear Stream 5 direct mode error flag.
- * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
-}
-
-/**
- * @brief Clear Stream 6 direct mode error flag.
- * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
-}
-
-/**
- * @brief Clear Stream 7 direct mode error flag.
- * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
-}
-
-/**
- * @brief Clear Stream 0 FIFO error flag.
- * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
-}
-
-/**
- * @brief Clear Stream 1 FIFO error flag.
- * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
-}
-
-/**
- * @brief Clear Stream 2 FIFO error flag.
- * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
-}
-
-/**
- * @brief Clear Stream 3 FIFO error flag.
- * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
-}
-
-/**
- * @brief Clear Stream 4 FIFO error flag.
- * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
-}
-
-/**
- * @brief Clear Stream 5 FIFO error flag.
- * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
-}
-
-/**
- * @brief Clear Stream 6 FIFO error flag.
- * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
-}
-
-/**
- * @brief Clear Stream 7 FIFO error flag.
- * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Half transfer interrupt.
- * @rmtoll CR HTIE LL_DMA_EnableIT_HT
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
-}
-
-/**
- * @brief Enable Transfer error interrupt.
- * @rmtoll CR TEIE LL_DMA_EnableIT_TE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
-}
-
-/**
- * @brief Enable Transfer complete interrupt.
- * @rmtoll CR TCIE LL_DMA_EnableIT_TC
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
-}
-
-/**
- * @brief Enable Direct mode error interrupt.
- * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
- * @brief Enable FIFO error interrupt.
- * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
- * @brief Disable Half transfer interrupt.
- * @rmtoll CR HTIE LL_DMA_DisableIT_HT
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
-}
-
-/**
- * @brief Disable Transfer error interrupt.
- * @rmtoll CR TEIE LL_DMA_DisableIT_TE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
-}
-
-/**
- * @brief Disable Transfer complete interrupt.
- * @rmtoll CR TCIE LL_DMA_DisableIT_TC
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
-}
-
-/**
- * @brief Disable Direct mode error interrupt.
- * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
- * @brief Disable FIFO error interrupt.
- * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
- * @brief Check if Half transfer interrup is enabled.
- * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
-}
-
-/**
- * @brief Check if Transfer error nterrup is enabled.
- * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
-}
-
-/**
- * @brief Check if Transfer complete interrup is enabled.
- * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
-}
-
-/**
- * @brief Check if Direct mode error interrupt is enabled.
- * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
-}
-
-/**
- * @brief Check if FIFO error interrup is enabled.
- * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
- * @param DMAx DMAx Instance
- * @param Stream This parameter can be one of the following values:
- * @arg @ref LL_DMA_STREAM_0
- * @arg @ref LL_DMA_STREAM_1
- * @arg @ref LL_DMA_STREAM_2
- * @arg @ref LL_DMA_STREAM_3
- * @arg @ref LL_DMA_STREAM_4
- * @arg @ref LL_DMA_STREAM_5
- * @arg @ref LL_DMA_STREAM_6
- * @arg @ref LL_DMA_STREAM_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
- return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_exti.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_exti.h
deleted file mode 100644
index 1eddc6a432..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_exti.h
+++ /dev/null
@@ -1,934 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_EXTI_H
-#define __STM32F2xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
- * @{
- */
-typedef struct
-{
-
- uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
- This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
- FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-
- uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
- uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
- * @{
- */
-#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
-#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
-#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
-#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
-#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
-#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
-#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
-#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
-#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
-#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
-#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
-#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
-#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
-#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
-#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
-#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
-#endif
-#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
-#endif
-#if defined(EXTI_IMR_IM23)
-#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
-#endif
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
- * @{
- */
-#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
- * @{
- */
-#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
- * @}
- */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in EXTI register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in EXTI register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt line.
- * In this case, both generate a trigger condition.
- * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
- * @{
- */
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 0 to 31
- * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
- * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
- * @{
- */
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval @note This bit is set when the selected edge event arrives on the interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
- return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_20
- * @arg @ref LL_EXTI_LINE_21
- * @arg @ref LL_EXTI_LINE_22
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
- WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* EXTI */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h
deleted file mode 100644
index 444504d10b..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_fsmc.h
+++ /dev/null
@@ -1,893 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_fsmc.h
- * @author MCD Application Team
- * @brief Header file of FSMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_FSMC_H
-#define STM32F2xx_LL_FSMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FSMC_LL
- * @{
- */
-
-/** @addtogroup FSMC_LL_Private_Macros
- * @{
- */
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
- ((__BANK__) == FSMC_NORSRAM_BANK2) || \
- ((__BANK__) == FSMC_NORSRAM_BANK3) || \
- ((__BANK__) == FSMC_NORSRAM_BANK4))
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
- ((__MODE__) == FSMC_ACCESS_MODE_B) || \
- ((__MODE__) == FSMC_ACCESS_MODE_C) || \
- ((__MODE__) == FSMC_ACCESS_MODE_D))
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
-#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
-#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-
-#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
-#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
-#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
-#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
-#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
-#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
-#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
-#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
-
-#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
-
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
- * @{
- */
-
-#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
-
-/**
- * @brief FSMC NORSRAM Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory device.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
-
- uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
-} FSMC_NORSRAM_InitTypeDef;
-
-/**
- * @brief FSMC NORSRAM Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
-
- uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and
- Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
-
- uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17
- in NOR Flash memories with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-} FSMC_NORSRAM_TimingTypeDef;
-
-/**
- * @brief FSMC NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_NAND_Data_Width */
-
- uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-} FSMC_NAND_InitTypeDef;
-
-/**
- * @brief FSMC NAND Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-
- uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
-} FSMC_NAND_PCC_TimingTypeDef;
-
-/**
- * @brief FSMC PCCARD Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-}FSMC_PCCARD_InitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
- * @{
- */
-
-/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
- * @{
- */
-#define FSMC_NORSRAM_BANK1 (0x00000000U)
-#define FSMC_NORSRAM_BANK2 (0x00000002U)
-#define FSMC_NORSRAM_BANK3 (0x00000004U)
-#define FSMC_NORSRAM_BANK4 (0x00000006U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
- * @{
- */
-#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type FSMC Memory Type
- * @{
- */
-#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
-#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
-#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
- * @{
- */
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
- * @{
- */
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
- * @{
- */
-#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
-#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
- * @{
- */
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
- * @{
- */
-#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
-#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
- * @{
- */
-#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
-#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation FSMC Write Operation
- * @{
- */
-#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
-#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
- * @{
- */
-#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
-#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
- * @{
- */
-#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
-#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
- * @{
- */
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst FSMC Write Burst
- * @{
- */
-#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
-#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
- * @{
- */
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
-#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
- * @{
- */
-#define FSMC_ACCESS_MODE_A (0x00000000U)
-#define FSMC_ACCESS_MODE_B (0x10000000U)
-#define FSMC_ACCESS_MODE_C (0x20000000U)
-#define FSMC_ACCESS_MODE_D (0x30000000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
- * @{
- */
-/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
- * @{
- */
-#define FSMC_NAND_BANK2 (0x00000010U)
-#define FSMC_NAND_BANK3 (0x00000100U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_feature FSMC Wait feature
- * @{
- */
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
- * @{
- */
-#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
-#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
- * @{
- */
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC FSMC ECC
- * @{
- */
-#define FSMC_NAND_ECC_DISABLE (0x00000000U)
-#define FSMC_NAND_ECC_ENABLE (0x00000040U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
- * @{
- */
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
-#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
- * @{
- */
-#define FSMC_IT_RISING_EDGE (0x00000008U)
-#define FSMC_IT_LEVEL (0x00000010U)
-#define FSMC_IT_FALLING_EDGE (0x00000020U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
- * @{
- */
-#define FSMC_FLAG_RISING_EDGE (0x00000001U)
-#define FSMC_FLAG_LEVEL (0x00000002U)
-#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
-#define FSMC_FLAG_FEMPT (0x00000040U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
- * @{
- */
-/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
-
-/**
- * @brief Enable the NORSRAM device access.
- * @param __INSTANCE__ FSMC_NORSRAM Instance
- * @param __BANK__ FSMC_NORSRAM Bank
- * @retval None
- */
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- |= FSMC_BCR1_MBKEN)
-
-/**
- * @brief Disable the NORSRAM device access.
- * @param __INSTANCE__ FSMC_NORSRAM Instance
- * @param __BANK__ FSMC_NORSRAM Bank
- * @retval None
- */
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
- &= ~FSMC_BCR1_MBKEN)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
-
-/**
- * @brief Enable the NAND device access.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @retval None
- */
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
-
-/**
- * @brief Disable the NAND device access.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @retval None
- */
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
- * @brief macros to handle PCCARD read/write operations
- * @{
- */
-/**
- * @brief Enable the PCCARD device access.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @retval None
- */
-#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
-
-/**
- * @brief Disable the PCCARD device access.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @retval None
- */
-#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
- * @brief macros to handle NAND interrupts
- * @{
- */
-
-/**
- * @brief Enable the NAND device interrupt.
- * @param __INSTANCE__ FSMC_NAND instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __INTERRUPT__ FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
-
-/**
- * @brief Disable the NAND device interrupt.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __INTERRUPT__ FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
-
-/**
- * @brief Get flag status of the NAND device.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __FLAG__ FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-
-/**
- * @brief Clear flag status of the NAND device.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __FLAG__ FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
- * @brief macros to handle PCCARD interrupts
- * @{
- */
-
-/**
- * @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__ FSMC_PCCARD instance
- * @param __INTERRUPT__ FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
-
-/**
- * @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__ FSMC_PCCARD instance
- * @param __INTERRUPT__ FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
-
-/**
- * @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__ FSMC_PCCARD instance
- * @param __FLAG__ FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__ FSMC_PCCARD instance
- * @param __FLAG__ FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
- * @{
- */
-
-/** @defgroup FSMC_LL_NORSRAM NOR SRAM
- * @{
- */
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
- FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
- uint32_t ExtendedMode);
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
- FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
- * @{
- */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_NAND NAND
- * @{
- */
-/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
- * @{
- */
-HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
- uint32_t Timeout);
-/**
- * @}
- */
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_PCCARD PCCARD
- * @{
- */
-/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
- * @{
- */
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
- FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
-/**
- * @}
- */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_FSMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_gpio.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_gpio.h
deleted file mode 100644
index d60287f4bd..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_gpio.h
+++ /dev/null
@@ -1,983 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_GPIO_H
-#define __STM32F2xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)
-
-/** @defgroup GPIO_LL GPIO
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- * @{
- */
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- * @{
- */
-
-/**
- * @brief LL GPIO Init Structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
- uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
- uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
- uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_AF.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
- * @{
- */
-#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
- GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
- GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
- GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
- GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
- GPIO_BSRR_BS_15) /*!< Select all pins */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
- * @{
- */
-#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
- * @{
- */
-#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
- * @{
- */
-#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
-#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- * @{
- */
-#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
- * @{
- */
-#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- * @{
- */
-
-/**
- * @brief Configure gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_SetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
- MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll MODER MODEy LL_GPIO_GetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @arg @ref LL_GPIO_MODE_ANALOG
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->MODER,
- (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @param OutputType This parameter can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
- MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
- * @brief Return gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
-}
-
-/**
- * @brief Configure gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Speed This parameter can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
-{
- MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
- (Speed << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
- (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Pull This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
- MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
- * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_PULL_NO
- * @arg @ref LL_GPIO_PULL_UP
- * @arg @ref LL_GPIO_PULL_DOWN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->PUPDR,
- (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
- MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
- (Alternate << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
- * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->AFR[0],
- (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Alternate This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
- MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
- (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
-}
-
-/**
- * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
- * @note Possible values are from AF0 to AF15 depending on target.
- * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_0
- * @arg @ref LL_GPIO_AF_1
- * @arg @ref LL_GPIO_AF_2
- * @arg @ref LL_GPIO_AF_3
- * @arg @ref LL_GPIO_AF_4
- * @arg @ref LL_GPIO_AF_5
- * @arg @ref LL_GPIO_AF_6
- * @arg @ref LL_GPIO_AF_7
- * @arg @ref LL_GPIO_AF_8
- * @arg @ref LL_GPIO_AF_9
- * @arg @ref LL_GPIO_AF_10
- * @arg @ref LL_GPIO_AF_11
- * @arg @ref LL_GPIO_AF_12
- * @arg @ref LL_GPIO_AF_13
- * @arg @ref LL_GPIO_AF_14
- * @arg @ref LL_GPIO_AF_15
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (uint32_t)(READ_BIT(GPIOx->AFR[1],
- (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
-}
-
-
-/**
- * @brief Lock configuration of several pins for a dedicated port.
- * @note When the lock sequence has been applied on a port bit, the
- * value of this port bit can no longer be modified until the
- * next reset.
- * @note Each lock bit freezes a specific configuration register
- * (control and alternate function registers).
- * @rmtoll LCKR LCKK LL_GPIO_LockPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- __IO uint32_t temp;
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- WRITE_REG(GPIOx->LCKR, PinMask);
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
- temp = READ_REG(GPIOx->LCKR);
- (void) temp;
-}
-
-/**
- * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
- * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
- * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- * @param GPIOx GPIO Port
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
- return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
- * @{
- */
-
-/**
- * @brief Return full input data register value for a dedicated port.
- * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- * @param GPIOx GPIO Port
- * @retval Input data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Write output data register for the port.
- * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- * @param GPIOx GPIO Port
- * @param PortValue Level value for each pin of the port
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
- WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
- * @brief Return full output data register value for a dedicated port.
- * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- * @param GPIOx GPIO Port
- * @retval Output data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
-}
-
-/**
- * @brief Set several pins to high level on dedicated gpio port.
- * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
- * @brief Set several pins to low level on dedicated gpio port.
- * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BSRR, (PinMask << 16));
-}
-
-/**
- * @brief Toggle data value for several pin of dedicated port.
- * @rmtoll ODR ODy LL_GPIO_TogglePin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- uint32_t odr = READ_REG(GPIOx->ODR);
- WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_i2c.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_i2c.h
deleted file mode 100644
index 72f374928e..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_i2c.h
+++ /dev/null
@@ -1,1784 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_I2C_H
-#define __STM32F2xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (I2C1) || defined (I2C2) || defined (I2C3)
-
-/** @defgroup I2C_LL I2C
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
- * @{
- */
-
-/* Defines used to perform compute and check in the macros */
-#define LL_I2C_MAX_SPEED_STANDARD 100000U
-#define LL_I2C_MAX_SPEED_FAST 400000U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
- This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
-
- uint32_t ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz (in Hz)
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
- or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
-
- uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
-
- uint32_t OwnAddress1; /*!< Specifies the device own address 1.
- This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-
- uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
-
- uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
- This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2C_ReadReg function
- * @{
- */
-#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
-#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
- Address matched flag (slave mode) */
-#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
-#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
-#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
-#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
-#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
-#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
-#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
-#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
-#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
-#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
-#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
-#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
-#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
-#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
-#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
-#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
-#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
- * @{
- */
-#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
-#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
-#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
- * @{
- */
-#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
- * @{
- */
-#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
-#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
- * @{
- */
-#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
-#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
- * @{
- */
-#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
-#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
- * @{
- */
-#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
- * @{
- */
-#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
-#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Convert Peripheral Clock Frequency in Mhz.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @retval Value of peripheral clock (in Mhz)
- */
-#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
-
-/**
- * @brief Convert Peripheral Clock Frequency in Hz.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
- * @retval Value of peripheral clock (in Hz)
- */
-#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
-
-/**
- * @brief Compute I2C Clock rising time.
- * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
- * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
- * @retval Value between Min_Data=0x02 and Max_Data=0x3F
- */
-#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-
-/**
- * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
- * @param __DUTYCYCLE__ This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- */
-#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
- (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
- (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
-
-/**
- * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
- */
-#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
-
-/**
- * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
- * @param __DUTYCYCLE__ This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
- */
-#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
- (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
- (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
-
-/**
- * @brief Get the Least significant bits of a 10-Bits address.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-/**
- * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
- */
-#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-
-/**
- * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
- */
-#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable I2C peripheral (PE = 1).
- * @rmtoll CR1 PE LL_I2C_Enable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Disable I2C peripheral (PE = 0).
- * @rmtoll CR1 PE LL_I2C_Disable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Check if the I2C peripheral is enabled or disabled.
- * @rmtoll CR1 PE LL_I2C_IsEnabled
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
-}
-
-
-/**
- * @brief Enable DMA transmission requests.
- * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Disable DMA transmission requests.
- * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Check if DMA transmission requests are enabled or disabled.
- * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
- * @brief Enable DMA reception requests.
- * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Disable DMA reception requests.
- * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Check if DMA reception requests are enabled or disabled.
- * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer.
- * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
- * @param I2Cx I2C Instance.
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
-{
- return (uint32_t) & (I2Cx->DR);
-}
-
-/**
- * @brief Enable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Disable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Check if Clock stretching is enabled or disabled.
- * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
-}
-
-/**
- * @brief Enable General Call.
- * @note When enabled the Address 0x00 is ACKed.
- * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
- * @brief Disable General Call.
- * @note When disabled the Address 0x00 is NACKed.
- * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
- * @brief Check if General Call is enabled or disabled.
- * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
-}
-
-/**
- * @brief Set the Own Address1.
- * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
- * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
- * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
- * OAR1 ADDMODE LL_I2C_SetOwnAddress1
- * @param I2Cx I2C Instance.
- * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
- * @param OwnAddrSize This parameter can be one of the following values:
- * @arg @ref LL_I2C_OWNADDRESS1_7BIT
- * @arg @ref LL_I2C_OWNADDRESS1_10BIT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
- MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
- * @brief Set the 7bits Own Address2.
- * @note This action has no effect if own address2 is enabled.
- * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
- * @param I2Cx I2C Instance.
- * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
-{
- MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
-}
-
-/**
- * @brief Enable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
- * @brief Disable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
- * @brief Check if Own Address1 acknowledge is enabled or disabled.
- * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
-}
-
-/**
- * @brief Configure the Peripheral clock frequency.
- * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
- * @param I2Cx I2C Instance.
- * @param PeriphClock Peripheral Clock (in Hz)
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
-}
-
-/**
- * @brief Get the Peripheral clock frequency.
- * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
- * @param I2Cx I2C Instance.
- * @retval Value of Peripheral Clock (in Hz)
- */
-__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
-}
-
-/**
- * @brief Configure the Duty cycle (Fast mode only).
- * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
- * @param I2Cx I2C Instance.
- * @param DutyCycle This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
-}
-
-/**
- * @brief Get the Duty cycle (Fast mode only).
- * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- */
-__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
-}
-
-/**
- * @brief Configure the I2C master clock speed mode.
- * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
- * @param I2Cx I2C Instance.
- * @param ClockSpeedMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
- * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
-}
-
-/**
- * @brief Get the the I2C master speed mode.
- * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
- * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
-}
-
-/**
- * @brief Configure the SCL, SDA rising time.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
- * @param I2Cx I2C Instance.
- * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
-{
- MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
-}
-
-/**
- * @brief Get the SCL, SDA rising time.
- * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x02 and Max_Data=0x3F
- */
-__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
-}
-
-/**
- * @brief Configure the SCL high and low period.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CCR CCR LL_I2C_SetClockPeriod
- * @param I2Cx I2C Instance.
- * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
-}
-
-/**
- * @brief Get the SCL high and low period.
- * @rmtoll CCR CCR LL_I2C_GetClockPeriod
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
-}
-
-/**
- * @brief Configure the SCL speed.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
- * TRISE TRISE LL_I2C_ConfigSpeed\n
- * CCR FS LL_I2C_ConfigSpeed\n
- * CCR DUTY LL_I2C_ConfigSpeed\n
- * CCR CCR LL_I2C_ConfigSpeed
- * @param I2Cx I2C Instance.
- * @param PeriphClock Peripheral Clock (in Hz)
- * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
- * @param DutyCycle This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
- uint32_t DutyCycle)
-{
- uint32_t freqrange = 0x0U;
- uint32_t clockconfig = 0x0U;
-
- /* Compute frequency range */
- freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
-
- /* Configure I2Cx: Frequency range register */
- MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
-
- /* Configure I2Cx: Rise Time register */
- MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
-
- /* Configure Speed mode, Duty Cycle and Clock control register value */
- if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
- {
- /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
- clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
- __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
- DutyCycle;
- }
- else
- {
- /* Set Speed mode at standard for Clock Speed request in standard clock range */
- clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
- __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
- }
-
- /* Configure I2Cx: Clock control register */
- MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
-}
-
-/**
- * @brief Configure peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
- * CR1 SMBTYPE LL_I2C_SetMode\n
- * CR1 ENARP LL_I2C_SetMode
- * @param I2Cx I2C Instance.
- * @param PeripheralMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
-}
-
-/**
- * @brief Get peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
- * CR1 SMBTYPE LL_I2C_GetMode\n
- * CR1 ENARP LL_I2C_GetMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
-}
-
-/**
- * @brief Enable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is drived low and
- * Alert Response Address Header acknowledge is enabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is supported.
- * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
- * @brief Disable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
- * Alert Response Address Header acknowledge is disabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is not supported.
- * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
- * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
-}
-
-/**
- * @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
- * @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
- * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable TXE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
- * CR2 ITBUFEN LL_I2C_EnableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable TXE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
- * CR2 ITBUFEN LL_I2C_DisableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if the TXE Interrupt is enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
- * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable RXNE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
- * CR2 ITBUFEN LL_I2C_EnableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable RXNE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
- * CR2 ITBUFEN LL_I2C_DisableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if the RXNE Interrupt is enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
- * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable Events interrupts.
- * @note Any of these events will generate interrupt :
- * Start Bit (SB)
- * Address sent, Address matched (ADDR)
- * 10-bit header sent (ADD10)
- * Stop detection (STOPF)
- * Byte transfer finished (BTF)
- *
- * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
- * @brief Disable Events interrupts.
- * @note Any of these events will generate interrupt :
- * Start Bit (SB)
- * Address sent, Address matched (ADDR)
- * 10-bit header sent (ADD10)
- * Stop detection (STOPF)
- * Byte transfer finished (BTF)
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
- * @brief Check if Events interrupts are enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
-}
-
-/**
- * @brief Enable Buffer interrupts.
- * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable Buffer interrupts.
- * @note Any of these Buffer events will generate interrupt :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if Buffer interrupts are enabled or disabled.
- * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Bus Error detection (BERR)
- * Arbitration Loss (ARLO)
- * Acknowledge Failure(AF)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (SMBALERT)
- * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
- * @brief Disable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Bus Error detection (BERR)
- * Arbitration Loss (ARLO)
- * Acknowledge Failure(AF)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (SMBALERT)
- * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
- * @brief Check if Error interrupts are enabled or disabled.
- * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
- * @{
- */
-
-/**
- * @brief Indicate the status of Transmit data register empty flag.
- * @note RESET: When next data is written in Transmit data register.
- * SET: When Transmit data register is empty.
- * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
-}
-
-/**
- * @brief Indicate the status of Byte Transfer Finished flag.
- * RESET: When Data byte transfer not done.
- * SET: When Data byte transfer succeeded.
- * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
-}
-
-/**
- * @brief Indicate the status of Receive data register not empty flag.
- * @note RESET: When Receive data register is read.
- * SET: When the received data is copied in Receive data register.
- * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
-}
-
-/**
- * @brief Indicate the status of Start Bit (master mode).
- * @note RESET: When No Start condition.
- * SET: When Start condition is generated.
- * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
-}
-
-/**
- * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
- * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
-}
-
-/**
- * @brief Indicate the status of 10-bit header sent (master mode).
- * @note RESET: When no ADD10 event occurred.
- * SET: When the master has sent the first address byte (header).
- * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
-}
-
-/**
- * @brief Indicate the status of Acknowledge failure flag.
- * @note RESET: No acknowledge failure.
- * SET: When an acknowledge failure is received after a byte transmission.
- * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
-}
-
-/**
- * @brief Indicate the status of Stop detection flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When a Stop condition is detected.
- * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
-}
-
-/**
- * @brief Indicate the status of Bus error flag.
- * @note RESET: Clear default value.
- * SET: When a misplaced Start or Stop condition is detected.
- * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
-}
-
-/**
- * @brief Indicate the status of Arbitration lost flag.
- * @note RESET: Clear default value.
- * SET: When arbitration lost.
- * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
-}
-
-/**
- * @brief Indicate the status of Overrun/Underrun flag.
- * @note RESET: Clear default value.
- * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
- * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
-}
-
-/**
- * @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
-}
-
-/**
- * @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
-}
-
-/**
- * @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
-}
-
-/**
- * @brief Indicate the status of Bus Busy flag.
- * @note RESET: Clear default value.
- * SET: When a Start condition is detected.
- * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
-}
-
-/**
- * @brief Indicate the status of Dual flag.
- * @note RESET: Received address matched with OAR1.
- * SET: Received address matched with OAR2.
- * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
-}
-
-/**
- * @brief Indicate the status of SMBus Host address reception (Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: No SMBus Host address
- * SET: SMBus Host address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
-}
-
-/**
- * @brief Indicate the status of SMBus Device default address reception (Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: No SMBus Device default address
- * SET: SMBus Device default address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
-}
-
-/**
- * @brief Indicate the status of General call address reception (Slave mode).
- * @note RESET: No General call address
- * SET: General call address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
-}
-
-/**
- * @brief Indicate the status of Master/Slave flag.
- * @note RESET: Slave Mode.
- * SET: Master Mode.
- * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
-}
-
-/**
- * @brief Clear Address Matched flag.
- * @note Clearing this flag is done by a read access to the I2Cx_SR1
- * register followed by a read access to the I2Cx_SR2 register.
- * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- __IO uint32_t tmpreg;
- tmpreg = I2Cx->SR1;
- (void) tmpreg;
- tmpreg = I2Cx->SR2;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Acknowledge failure flag.
- * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
-}
-
-/**
- * @brief Clear Stop detection flag.
- * @note Clearing this flag is done by a read access to the I2Cx_SR1
- * register followed by a write access to I2Cx_CR1 register.
- * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
- * CR1 PE LL_I2C_ClearFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
- __IO uint32_t tmpreg;
- tmpreg = I2Cx->SR1;
- (void) tmpreg;
- SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Clear Bus error flag.
- * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
-}
-
-/**
- * @brief Clear Arbitration lost flag.
- * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
-}
-
-/**
- * @brief Clear Overrun/Underrun flag.
- * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
-}
-
-/**
- * @brief Clear SMBus PEC error flag.
- * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
-}
-
-/**
- * @brief Clear SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
-}
-
-/**
- * @brief Clear SMBus Alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Enable Reset of I2C peripheral.
- * @rmtoll CR1 SWRST LL_I2C_EnableReset
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
- * @brief Disable Reset of I2C peripheral.
- * @rmtoll CR1 SWRST LL_I2C_DisableReset
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
- * @brief Check if the I2C peripheral is under reset state or not.
- * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
-}
-
-/**
- * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- * @note Usage in Slave or Master mode.
- * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
- * @param I2Cx I2C Instance.
- * @param TypeAcknowledge This parameter can be one of the following values:
- * @arg @ref LL_I2C_ACK
- * @arg @ref LL_I2C_NACK
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
-}
-
-/**
- * @brief Generate a START or RESTART condition
- * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
- * This action has no effect when RELOAD is set.
- * @rmtoll CR1 START LL_I2C_GenerateStartCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_START);
-}
-
-/**
- * @brief Generate a STOP condition after the current byte transfer (master mode).
- * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
-}
-
-/**
- * @brief Enable bit POS (master/host mode).
- * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
- * @rmtoll CR1 POS LL_I2C_EnableBitPOS
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
- * @brief Disable bit POS (master/host mode).
- * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
- * @rmtoll CR1 POS LL_I2C_DisableBitPOS
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
- * @brief Check if bit POS is enabled or disabled.
- * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
-}
-
-/**
- * @brief Indicate the value of transfer direction.
- * @note RESET: Bus is in read transfer (peripheral point of view).
- * SET: Bus is in write transfer (peripheral point of view).
- * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_DIRECTION_WRITE
- * @arg @ref LL_I2C_DIRECTION_READ
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
-}
-
-/**
- * @brief Enable DMA last transfer.
- * @note This action mean that next DMA EOT is the last transfer.
- * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
- * @brief Disable DMA last transfer.
- * @note This action mean that next DMA EOT is not the last transfer.
- * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
- * @brief Check if DMA last transfer is enabled or disabled.
- * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
-}
-
-/**
- * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
- * or by a START or STOP condition, it is also cleared by software.
- * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
- * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
- * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
-}
-
-/**
- * @brief Get the SMBus Packet Error byte calculated.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
-}
-
-/**
- * @brief Read Receive Data register.
- * @rmtoll DR DR LL_I2C_ReceiveData8
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
- return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
-}
-
-/**
- * @brief Write in Transmit Data Register .
- * @rmtoll DR DR LL_I2C_TransmitData8
- * @param I2Cx I2C Instance.
- * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
- MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* I2C1 || I2C2 || I2C3 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_iwdg.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_iwdg.h
deleted file mode 100644
index e79fa26bb5..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_iwdg.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_IWDG_H
-#define STM32F2xx_LL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(IWDG)
-
-/** @defgroup IWDG_LL IWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
- * @{
- */
-#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_IWDG_ReadReg function
- * @{
- */
-#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
-#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
- * @{
- */
-#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
-#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
-#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
-#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
-#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
-#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
-#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
- * @{
- */
-/** @defgroup IWDG_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Start the Independent Watchdog
- * @note Except if the hardware watchdog option is selected
- * @rmtoll KR KEY LL_IWDG_Enable
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * @rmtoll KR KEY LL_IWDG_ReloadCounter
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
-}
-
-/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
-}
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
-}
-
-/**
- * @brief Select the prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_SetPrescaler
- * @param IWDGx IWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
-{
- WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
-}
-
-/**
- * @brief Get the selected prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_GetPrescaler
- * @param IWDGx IWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
-{
- return (READ_REG(IWDGx->PR));
-}
-
-/**
- * @brief Specify the IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_SetReloadCounter
- * @param IWDGx IWDG Instance
- * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
-{
- WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
-}
-
-/**
- * @brief Get the specified IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_GetReloadCounter
- * @param IWDGx IWDG Instance
- * @retval Value between Min_Data=0 and Max_Data=0x0FFF
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
-{
- return (READ_REG(IWDGx->RLR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if flag Prescaler Value Update is set or not
- * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
-{
- return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if flag Reload Value Update is set or not
- * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
-{
- return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if flags Prescaler & Reload Value Update are reset or not
- * @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
- * @param IWDGx IWDG Instance
- * @retval State of bits (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
-{
- return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* IWDG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_pwr.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_pwr.h
deleted file mode 100644
index 363f087b5f..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_pwr.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_PWR_H
-#define __STM32F2xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_PWR_WriteReg function
- * @{
- */
-#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_PWR_ReadReg function
- * @{
- */
-#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
-#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
-#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
- * @{
- */
-#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power regulator ON) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
- * @{
- */
-#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
-#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
-#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
-#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
-#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
-/**
- * @}
- */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
- * @{
- */
-#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in PWR register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in PWR register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable the Flash Power Down in Stop Mode
- * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
-{
- SET_BIT(PWR->CR, PWR_CR_FPDS);
-}
-
-/**
- * @brief Disable the Flash Power Down in Stop Mode
- * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
-}
-
-/**
- * @brief Check if the Flash Power Down in Stop Mode is enabled
- * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
-}
-
-/**
- * @brief Enable access to the backup domain
- * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Check if the backup domain is enabled
- * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-/**
- * @brief Enable the backup regulator
- * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
- * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
- * The LL_PWR_EnableBkUpAccess() must be called before using this API.
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
-{
- SET_BIT(PWR->CSR, PWR_CSR_BRE);
-}
-
-/**
- * @brief Disable the backup Regulator
- * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
- * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
- * The LL_PWR_EnableBkUpAccess() must be called before using this API.
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
-{
- CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
-}
-
-/**
- * @brief Check if the backup Regulator is enabled
- * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
-}
-
-/**
- * @brief Set voltage regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
- * @param RegulMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
- * @brief Get voltage regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-
-/**
- * @brief Set power down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_SetPowerMode
- * @param PDMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
- MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
-}
-
-/**
- * @brief Get power down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_GetPowerMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
-}
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector
- * @rmtoll CR PLS LL_PWR_SetPVDLevel
- * @param PVDLevel This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
- MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
- * @brief Get the voltage threshold detection
- * @rmtoll CR PLS LL_PWR_GetPVDLevel
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
- * @brief Enable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_EnablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Disable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_DisablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Check if Power Voltage Detector is enabled
- * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-
-/**
- * @brief Enable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
- SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
- CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Check if the WakeUp PINx functionality is enabled
- * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
- return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Wake-up Flag
- * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
- * @brief Get Standby Flag
- * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-/**
- * @brief Get Backup regulator ready Flag
- * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
-}
-/**
- * @brief Indicate whether VDD voltage is below the selected PVD threshold
- * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-
-/**
- * @brief Clear Standby Flag
- * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
- * @brief Clear Wake-up Flags
- * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_PWR_DeInit(void);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(PWR) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rcc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rcc.h
deleted file mode 100644
index 5caa0a7fd6..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rcc.h
+++ /dev/null
@@ -1,2440 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_RCC_H
-#define __STM32F2xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
- * @{
- */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- * @{
- */
-
-/**
- * @brief RCC Clocks Frequency Structure
- */
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- * @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
- * HW set-up.
- * @{
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-
-#if !defined (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
-#endif /* EXTERNAL_CLOCK_VALUE */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_RCC_WriteReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
-#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RCC_ReadReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
-#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
- * @{
- */
-#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- * @{
- */
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- * @{
- */
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- * @{
- */
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
- * @{
- */
-#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
-#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
- * @{
- */
-#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
-#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
-#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
-#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
-#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
-#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
-#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
-#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
-#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
-#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
- * @{
- */
-#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
-#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
-#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
-#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
-#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
-#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
-#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
-#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
-#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
-#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
-#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
-#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
-#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
-#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
-#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
-#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
-#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
-#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
-#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
-#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
-#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
-#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
-#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
-#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
-#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
-#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
-#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
-#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
-#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
-#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
-#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- * @{
- */
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
-#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
- * @{
- */
-#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- * @{
- */
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source
- * @{
- */
-#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor
- * @{
- */
-#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 2 */
-#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 3 */
-#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 4 */
-#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 5 */
-#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 6 */
-#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 7 */
-#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 8 */
-#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 9 */
-#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 10 */
-#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 11 */
-#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 12 */
-#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 13 */
-#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 14 */
-#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 15 */
-#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 16 */
-#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 17 */
-#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 18 */
-#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 19 */
-#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 20 */
-#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 21 */
-#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 22 */
-#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 23 */
-#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 24 */
-#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 25 */
-#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 26 */
-#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 27 */
-#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 28 */
-#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 29 */
-#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 30 */
-#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 31 */
-#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL and PLLI2S division factor by 32 */
-#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 33 */
-#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 34 */
-#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 35 */
-#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 36 */
-#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 37 */
-#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 38 */
-#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 39 */
-#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 40 */
-#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 41 */
-#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 42 */
-#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 43 */
-#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 44 */
-#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 45 */
-#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 46 */
-#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 47 */
-#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 48 */
-#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 49 */
-#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 50 */
-#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 51 */
-#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 52 */
-#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 53 */
-#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 54 */
-#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 55 */
-#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 56 */
-#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 57 */
-#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 58 */
-#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 59 */
-#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 60 */
-#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 61 */
-#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 62 */
-#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 63 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
- * @{
- */
-#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
- * @{
- */
-#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
-#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
-#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
-#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
-#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
-#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
-#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
-#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
-#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
-#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
-#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
-#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
-#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
-#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
- * @{
- */
-#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
-#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
- * @{
- */
-#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
-#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
-#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
-#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
-#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
-#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RCC register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RCC register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- * @{
- */
-
-/**
- * @brief Helper macro to calculate the PLLCLK frequency on system domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- * @param __PLLN__ Between 192 and 432
- * @param __PLLP__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
- ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
-
-/**
- * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- * @param __PLLN__ Between 192 and 432
- * @param __PLLQ__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_3
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_5
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_7
- * @arg @ref LL_RCC_PLLQ_DIV_8
- * @arg @ref LL_RCC_PLLQ_DIV_9
- * @arg @ref LL_RCC_PLLQ_DIV_10
- * @arg @ref LL_RCC_PLLQ_DIV_11
- * @arg @ref LL_RCC_PLLQ_DIV_12
- * @arg @ref LL_RCC_PLLQ_DIV_13
- * @arg @ref LL_RCC_PLLQ_DIV_14
- * @arg @ref LL_RCC_PLLQ_DIV_15
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
- ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
-
-/**
- * @retval PLLI2S clock frequency (in Hz)
- */
-
-/**
- * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
- * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
- * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
- * @param __PLLM__ This parameter can be one of the following values:
- * @param __PLLI2SN__ Between 192 and 432
- * @param __PLLI2SR__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2SR_DIV_2
- * @arg @ref LL_RCC_PLLI2SR_DIV_3
- * @arg @ref LL_RCC_PLLI2SR_DIV_4
- * @arg @ref LL_RCC_PLLI2SR_DIV_5
- * @arg @ref LL_RCC_PLLI2SR_DIV_6
- * @arg @ref LL_RCC_PLLI2SR_DIV_7
- * @retval PLLI2S clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
- ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
-
-/**
- * @brief Helper macro to calculate the HCLK frequency
- * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- * @param __AHBPRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval HCLK clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB1PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval PCLK1 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB2PRESCALER__ This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval PCLK2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_LL_EF_HSE HSE
- * @{
- */
-
-/**
- * @brief Enable the Clock Security System.
- * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Enable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Disable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Check if HSE oscillator Ready
- * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI HSI
- * @{
- */
-
-/**
- * @brief Enable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Disable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Check if HSI clock is ready
- * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
-}
-
-/**
- * @brief Get HSI Calibration value
- * @note When HSITRIM is written, HSICAL is updated with the sum of
- * HSITRIM and the factory trim value
- * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
-}
-
-/**
- * @brief Set HSI Calibration trimming
- * @note user-programmable trimming value that is added to the HSICAL
- * @note Default value is 16, which, when added to the HSICAL value,
- * should trim the HSI to 16 MHz +/- 1 %
- * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Value Between Min_Data = 0 and Max_Data = 31
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @brief Get HSI Calibration trimming
- * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
- * @retval Between Min_Data = 0 and Max_Data = 31
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSE LSE
- * @{
- */
-
-/**
- * @brief Enable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Disable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Enable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Disable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Check if LSE oscillator Ready
- * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSI LSI
- * @{
- */
-
-/**
- * @brief Enable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Disable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
- CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Check if LSI is Ready
- * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_System System
- * @{
- */
-
-/**
- * @brief Configure the system clock source
- * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
- * @brief Get the system clock source
- * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
- * @brief Set AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
- * @brief Set APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
- * @brief Set APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
- * @brief Get AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
- * @brief Get APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
- * @brief Get APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_MCO MCO
- * @{
- */
-
-/**
- * @brief Configure MCOx
- * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
- * CFGR MCO1PRE LL_RCC_ConfigMCO\n
- * CFGR MCO2 LL_RCC_ConfigMCO\n
- * CFGR MCO2PRE LL_RCC_ConfigMCO
- * @param MCOxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1SOURCE_HSI
- * @arg @ref LL_RCC_MCO1SOURCE_LSE
- * @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
- * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
- * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
- * @arg @ref LL_RCC_MCO2SOURCE_HSE
- * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
- * @param MCOxPrescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1_DIV_1
- * @arg @ref LL_RCC_MCO1_DIV_2
- * @arg @ref LL_RCC_MCO1_DIV_3
- * @arg @ref LL_RCC_MCO1_DIV_4
- * @arg @ref LL_RCC_MCO1_DIV_5
- * @arg @ref LL_RCC_MCO2_DIV_1
- * @arg @ref LL_RCC_MCO2_DIV_2
- * @arg @ref LL_RCC_MCO2_DIV_3
- * @arg @ref LL_RCC_MCO2_DIV_4
- * @arg @ref LL_RCC_MCO2_DIV_5
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
- MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- * @{
- */
-
-/**
- * @brief Configure I2S clock source
- * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
- * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
-}
-
-/**
- * @brief Get I2S Clock Source
- * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S1_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
- * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_RTC RTC
- * @{
- */
-
-/**
- * @brief Set RTC Clock Source
- * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
- * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
- * set). The BDRST bit can be used to reset them.
- * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
- * @brief Get RTC Clock Source
- * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
- * @brief Enable RTC
- * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Disable RTC
- * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Check if RTC has been enabled or not
- * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
-}
-
-/**
- * @brief Force the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Release the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Set HSE Prescalers for RTC Clock
- * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_NOCLOCK
- * @arg @ref LL_RCC_RTC_HSE_DIV_2
- * @arg @ref LL_RCC_RTC_HSE_DIV_3
- * @arg @ref LL_RCC_RTC_HSE_DIV_4
- * @arg @ref LL_RCC_RTC_HSE_DIV_5
- * @arg @ref LL_RCC_RTC_HSE_DIV_6
- * @arg @ref LL_RCC_RTC_HSE_DIV_7
- * @arg @ref LL_RCC_RTC_HSE_DIV_8
- * @arg @ref LL_RCC_RTC_HSE_DIV_9
- * @arg @ref LL_RCC_RTC_HSE_DIV_10
- * @arg @ref LL_RCC_RTC_HSE_DIV_11
- * @arg @ref LL_RCC_RTC_HSE_DIV_12
- * @arg @ref LL_RCC_RTC_HSE_DIV_13
- * @arg @ref LL_RCC_RTC_HSE_DIV_14
- * @arg @ref LL_RCC_RTC_HSE_DIV_15
- * @arg @ref LL_RCC_RTC_HSE_DIV_16
- * @arg @ref LL_RCC_RTC_HSE_DIV_17
- * @arg @ref LL_RCC_RTC_HSE_DIV_18
- * @arg @ref LL_RCC_RTC_HSE_DIV_19
- * @arg @ref LL_RCC_RTC_HSE_DIV_20
- * @arg @ref LL_RCC_RTC_HSE_DIV_21
- * @arg @ref LL_RCC_RTC_HSE_DIV_22
- * @arg @ref LL_RCC_RTC_HSE_DIV_23
- * @arg @ref LL_RCC_RTC_HSE_DIV_24
- * @arg @ref LL_RCC_RTC_HSE_DIV_25
- * @arg @ref LL_RCC_RTC_HSE_DIV_26
- * @arg @ref LL_RCC_RTC_HSE_DIV_27
- * @arg @ref LL_RCC_RTC_HSE_DIV_28
- * @arg @ref LL_RCC_RTC_HSE_DIV_29
- * @arg @ref LL_RCC_RTC_HSE_DIV_30
- * @arg @ref LL_RCC_RTC_HSE_DIV_31
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
-}
-
-/**
- * @brief Get HSE Prescalers for RTC Clock
- * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_NOCLOCK
- * @arg @ref LL_RCC_RTC_HSE_DIV_2
- * @arg @ref LL_RCC_RTC_HSE_DIV_3
- * @arg @ref LL_RCC_RTC_HSE_DIV_4
- * @arg @ref LL_RCC_RTC_HSE_DIV_5
- * @arg @ref LL_RCC_RTC_HSE_DIV_6
- * @arg @ref LL_RCC_RTC_HSE_DIV_7
- * @arg @ref LL_RCC_RTC_HSE_DIV_8
- * @arg @ref LL_RCC_RTC_HSE_DIV_9
- * @arg @ref LL_RCC_RTC_HSE_DIV_10
- * @arg @ref LL_RCC_RTC_HSE_DIV_11
- * @arg @ref LL_RCC_RTC_HSE_DIV_12
- * @arg @ref LL_RCC_RTC_HSE_DIV_13
- * @arg @ref LL_RCC_RTC_HSE_DIV_14
- * @arg @ref LL_RCC_RTC_HSE_DIV_15
- * @arg @ref LL_RCC_RTC_HSE_DIV_16
- * @arg @ref LL_RCC_RTC_HSE_DIV_17
- * @arg @ref LL_RCC_RTC_HSE_DIV_18
- * @arg @ref LL_RCC_RTC_HSE_DIV_19
- * @arg @ref LL_RCC_RTC_HSE_DIV_20
- * @arg @ref LL_RCC_RTC_HSE_DIV_21
- * @arg @ref LL_RCC_RTC_HSE_DIV_22
- * @arg @ref LL_RCC_RTC_HSE_DIV_23
- * @arg @ref LL_RCC_RTC_HSE_DIV_24
- * @arg @ref LL_RCC_RTC_HSE_DIV_25
- * @arg @ref LL_RCC_RTC_HSE_DIV_26
- * @arg @ref LL_RCC_RTC_HSE_DIV_27
- * @arg @ref LL_RCC_RTC_HSE_DIV_28
- * @arg @ref LL_RCC_RTC_HSE_DIV_29
- * @arg @ref LL_RCC_RTC_HSE_DIV_30
- * @arg @ref LL_RCC_RTC_HSE_DIV_31
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLL PLL
- * @{
- */
-
-/**
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Disable PLL
- * @note Cannot be disabled if the PLL clock is used as the system clock
- * @rmtoll CR PLLON LL_RCC_PLL_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
-}
-
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLI2S are disabled
- * @note PLLN/PLLP can be written only when PLL is disabled
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
- * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- * @param PLLN Between 192 and 432
- * @param PLLP This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
- Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
-}
-
-/**
- * @brief Configure PLL used for 48Mhz domain clock
- * @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLI2S are disabled
- * @note PLLN/PLLQ can be written only when PLL is disabled
- * @note This can be selected for USB, RNG, SDIO
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
- * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- * @param PLLN Between 192 and 432
- * @param PLLQ This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_3
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_5
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_7
- * @arg @ref LL_RCC_PLLQ_DIV_8
- * @arg @ref LL_RCC_PLLQ_DIV_9
- * @arg @ref LL_RCC_PLLQ_DIV_10
- * @arg @ref LL_RCC_PLLQ_DIV_11
- * @arg @ref LL_RCC_PLLQ_DIV_12
- * @arg @ref LL_RCC_PLLQ_DIV_13
- * @arg @ref LL_RCC_PLLQ_DIV_14
- * @arg @ref LL_RCC_PLLQ_DIV_15
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
- Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
-}
-
-/**
- * @brief Get Main PLL multiplication factor for VCO
- * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
- * @retval Between 192 and 432
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
-}
-
-/**
- * @brief Get Main PLL division factor for PLLP
- * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLP_DIV_2
- * @arg @ref LL_RCC_PLLP_DIV_4
- * @arg @ref LL_RCC_PLLP_DIV_6
- * @arg @ref LL_RCC_PLLP_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
-}
-
-/**
- * @brief Get Main PLL division factor for PLLQ
- * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
- * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLQ_DIV_2
- * @arg @ref LL_RCC_PLLQ_DIV_3
- * @arg @ref LL_RCC_PLLQ_DIV_4
- * @arg @ref LL_RCC_PLLQ_DIV_5
- * @arg @ref LL_RCC_PLLQ_DIV_6
- * @arg @ref LL_RCC_PLLQ_DIV_7
- * @arg @ref LL_RCC_PLLQ_DIV_8
- * @arg @ref LL_RCC_PLLQ_DIV_9
- * @arg @ref LL_RCC_PLLQ_DIV_10
- * @arg @ref LL_RCC_PLLQ_DIV_11
- * @arg @ref LL_RCC_PLLQ_DIV_12
- * @arg @ref LL_RCC_PLLQ_DIV_13
- * @arg @ref LL_RCC_PLLQ_DIV_14
- * @arg @ref LL_RCC_PLLQ_DIV_15
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
-}
-
-/**
- * @brief Configure PLL clock source
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
- * @param PLLSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
-}
-
-/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
- * @brief Get Division factor for the main PLL and other PLL
- * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-}
-
-/**
- * @brief Configure Spread Spectrum used for PLL
- * @note These bits must be written before enabling PLL
- * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
- * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
- * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
- * @param Mod Between Min_Data=0 and Max_Data=8191
- * @param Inc Between Min_Data=0 and Max_Data=32767
- * @param Sel This parameter can be one of the following values:
- * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
- * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
-{
- MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
-}
-
-/**
- * @brief Get Spread Spectrum Modulation Period for PLL
- * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
- * @retval Between Min_Data=0 and Max_Data=8191
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
-{
- return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
-}
-
-/**
- * @brief Get Spread Spectrum Incrementation Step for PLL
- * @note Must be written before enabling PLL
- * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
- * @retval Between Min_Data=0 and Max_Data=32767
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
-{
- return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
-}
-
-/**
- * @brief Get Spread Spectrum Selection for PLL
- * @note Must be written before enabling PLL
- * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
- * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
-{
- return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
-}
-
-/**
- * @brief Enable Spread Spectrum for PLL.
- * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
-{
- SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
-}
-
-/**
- * @brief Disable Spread Spectrum for PLL.
- * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
-{
- CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
- * @{
- */
-
-/**
- * @brief Enable PLLI2S
- * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
-}
-
-/**
- * @brief Disable PLLI2S
- * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
-}
-
-/**
- * @brief Check if PLLI2S Ready
- * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
-}
-
-/**
- * @brief Configure PLLI2S used for I2S1 domain clock
- * @note PLL Source and PLLM Divider can be written only when PLL,
- * PLLI2S are disabled
- * @note PLLN/PLLR can be written only when PLLI2S is disabled
- * @note This can be selected for I2S
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
- * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
- * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
- * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @param PLLM This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLM_DIV_2
- * @arg @ref LL_RCC_PLLM_DIV_3
- * @arg @ref LL_RCC_PLLM_DIV_4
- * @arg @ref LL_RCC_PLLM_DIV_5
- * @arg @ref LL_RCC_PLLM_DIV_6
- * @arg @ref LL_RCC_PLLM_DIV_7
- * @arg @ref LL_RCC_PLLM_DIV_8
- * @arg @ref LL_RCC_PLLM_DIV_9
- * @arg @ref LL_RCC_PLLM_DIV_10
- * @arg @ref LL_RCC_PLLM_DIV_11
- * @arg @ref LL_RCC_PLLM_DIV_12
- * @arg @ref LL_RCC_PLLM_DIV_13
- * @arg @ref LL_RCC_PLLM_DIV_14
- * @arg @ref LL_RCC_PLLM_DIV_15
- * @arg @ref LL_RCC_PLLM_DIV_16
- * @arg @ref LL_RCC_PLLM_DIV_17
- * @arg @ref LL_RCC_PLLM_DIV_18
- * @arg @ref LL_RCC_PLLM_DIV_19
- * @arg @ref LL_RCC_PLLM_DIV_20
- * @arg @ref LL_RCC_PLLM_DIV_21
- * @arg @ref LL_RCC_PLLM_DIV_22
- * @arg @ref LL_RCC_PLLM_DIV_23
- * @arg @ref LL_RCC_PLLM_DIV_24
- * @arg @ref LL_RCC_PLLM_DIV_25
- * @arg @ref LL_RCC_PLLM_DIV_26
- * @arg @ref LL_RCC_PLLM_DIV_27
- * @arg @ref LL_RCC_PLLM_DIV_28
- * @arg @ref LL_RCC_PLLM_DIV_29
- * @arg @ref LL_RCC_PLLM_DIV_30
- * @arg @ref LL_RCC_PLLM_DIV_31
- * @arg @ref LL_RCC_PLLM_DIV_32
- * @arg @ref LL_RCC_PLLM_DIV_33
- * @arg @ref LL_RCC_PLLM_DIV_34
- * @arg @ref LL_RCC_PLLM_DIV_35
- * @arg @ref LL_RCC_PLLM_DIV_36
- * @arg @ref LL_RCC_PLLM_DIV_37
- * @arg @ref LL_RCC_PLLM_DIV_38
- * @arg @ref LL_RCC_PLLM_DIV_39
- * @arg @ref LL_RCC_PLLM_DIV_40
- * @arg @ref LL_RCC_PLLM_DIV_41
- * @arg @ref LL_RCC_PLLM_DIV_42
- * @arg @ref LL_RCC_PLLM_DIV_43
- * @arg @ref LL_RCC_PLLM_DIV_44
- * @arg @ref LL_RCC_PLLM_DIV_45
- * @arg @ref LL_RCC_PLLM_DIV_46
- * @arg @ref LL_RCC_PLLM_DIV_47
- * @arg @ref LL_RCC_PLLM_DIV_48
- * @arg @ref LL_RCC_PLLM_DIV_49
- * @arg @ref LL_RCC_PLLM_DIV_50
- * @arg @ref LL_RCC_PLLM_DIV_51
- * @arg @ref LL_RCC_PLLM_DIV_52
- * @arg @ref LL_RCC_PLLM_DIV_53
- * @arg @ref LL_RCC_PLLM_DIV_54
- * @arg @ref LL_RCC_PLLM_DIV_55
- * @arg @ref LL_RCC_PLLM_DIV_56
- * @arg @ref LL_RCC_PLLM_DIV_57
- * @arg @ref LL_RCC_PLLM_DIV_58
- * @arg @ref LL_RCC_PLLM_DIV_59
- * @arg @ref LL_RCC_PLLM_DIV_60
- * @arg @ref LL_RCC_PLLM_DIV_61
- * @arg @ref LL_RCC_PLLM_DIV_62
- * @arg @ref LL_RCC_PLLM_DIV_63
- * @param PLLN Between 192 and 432
- * @param PLLR This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2SR_DIV_2
- * @arg @ref LL_RCC_PLLI2SR_DIV_3
- * @arg @ref LL_RCC_PLLI2SR_DIV_4
- * @arg @ref LL_RCC_PLLI2SR_DIV_5
- * @arg @ref LL_RCC_PLLI2SR_DIV_6
- * @arg @ref LL_RCC_PLLI2SR_DIV_7
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
- MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
-}
-
-/**
- * @brief Get I2SPLL multiplication factor for VCO
- * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
- * @retval Between 192 and 432
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-}
-
-/**
- * @brief Get I2SPLL division factor for PLLI2SR
- * @note used for PLLI2SCLK (I2S clock)
- * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLI2SR_DIV_2
- * @arg @ref LL_RCC_PLLI2SR_DIV_3
- * @arg @ref LL_RCC_PLLI2SR_DIV_4
- * @arg @ref LL_RCC_PLLI2SR_DIV_5
- * @arg @ref LL_RCC_PLLI2SR_DIV_6
- * @arg @ref LL_RCC_PLLI2SR_DIV_7
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Clear LSI ready interrupt flag
- * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
- * @brief Clear LSE ready interrupt flag
- * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
- * @brief Clear HSI ready interrupt flag
- * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
- * @brief Clear HSE ready interrupt flag
- * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
- * @brief Clear PLL ready interrupt flag
- * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-/**
- * @brief Clear PLLI2S ready interrupt flag
- * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
-}
-
-/**
- * @brief Clear Clock security system interrupt flag
- * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-/**
- * @brief Check if LSI ready interrupt occurred or not
- * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
-}
-
-/**
- * @brief Check if LSE ready interrupt occurred or not
- * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
-}
-
-/**
- * @brief Check if HSI ready interrupt occurred or not
- * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
-}
-
-/**
- * @brief Check if HSE ready interrupt occurred or not
- * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
-}
-
-/**
- * @brief Check if PLL ready interrupt occurred or not
- * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
-}
-
-/**
- * @brief Check if PLLI2S ready interrupt occurred or not
- * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
-}
-
-/**
- * @brief Check if Clock security system interrupt occurred or not
- * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
-}
-
-/**
- * @brief Check if RCC flag Independent Watchdog reset is set or not.
- * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
-}
-
-/**
- * @brief Check if RCC flag Low Power reset is set or not.
- * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
-}
-
-/**
- * @brief Check if RCC flag Pin reset is set or not.
- * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
-}
-
-/**
- * @brief Check if RCC flag POR/PDR reset is set or not.
- * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
-}
-
-/**
- * @brief Check if RCC flag Software reset is set or not.
- * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
-}
-
-/**
- * @brief Check if RCC flag Window Watchdog reset is set or not.
- * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
-}
-
-/**
- * @brief Check if RCC flag BOR reset is set or not.
- * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
-}
-
-/**
- * @brief Set RMVF bit to clear the reset flags.
- * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Enable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Enable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Enable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Enable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-/**
- * @brief Enable PLLI2S ready interrupt
- * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
-}
-
-/**
- * @brief Disable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Disable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Disable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Disable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Disable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-/**
- * @brief Disable PLLI2S ready interrupt
- * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
-}
-
-/**
- * @brief Checks if LSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
-}
-
-/**
- * @brief Checks if LSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
-}
-
-/**
- * @brief Checks if HSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
-}
-
-/**
- * @brief Checks if HSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
-}
-
-/**
- * @brief Checks if PLL ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
-}
-
-/**
- * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_RCC_DeInit(void);
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
- * @{
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rng.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rng.h
deleted file mode 100644
index 0c21c1a96e..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rng.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_rng.h
- * @author MCD Application Team
- * @brief Header file of RNG LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_RNG_H
-#define STM32F2xx_LL_RNG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (RNG)
-
-/** @defgroup RNG_LL RNG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
- * @{
- */
-
-
-/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RNG_ReadReg function
- * @{
- */
-#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
-#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
-#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
-#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
-#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
-/**
- * @}
- */
-
-/** @defgroup RNG_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
- * @{
- */
-#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
- * @{
- */
-
-/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RNG register
- * @param __INSTANCE__ RNG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RNG register
- * @param __INSTANCE__ RNG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
- * @{
- */
-/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
- * @{
- */
-
-/**
- * @brief Enable Random Number Generation
- * @rmtoll CR RNGEN LL_RNG_Enable
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
-{
- SET_BIT(RNGx->CR, RNG_CR_RNGEN);
-}
-
-/**
- * @brief Disable Random Number Generation
- * @rmtoll CR RNGEN LL_RNG_Disable
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
-{
- CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
-}
-
-/**
- * @brief Check if Random Number Generator is enabled
- * @rmtoll CR RNGEN LL_RNG_IsEnabled
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Indicate if the RNG Data ready Flag is set or not
- * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if the Clock Error Current Status Flag is set or not
- * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if the Seed Error Current Status Flag is set or not
- * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
- * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
- * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear Clock Error interrupt Status (CEIS) Flag
- * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
-{
- WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
-}
-
-/**
- * @brief Clear Seed Error interrupt Status (SEIS) Flag
- * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
-{
- WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RNG_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable Random Number Generator Interrupt
- * (applies for either Seed error, Clock Error or Data ready interrupts)
- * @rmtoll CR IE LL_RNG_EnableIT
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
-{
- SET_BIT(RNGx->CR, RNG_CR_IE);
-}
-
-/**
- * @brief Disable Random Number Generator Interrupt
- * (applies for either Seed error, Clock Error or Data ready interrupts)
- * @rmtoll CR IE LL_RNG_DisableIT
- * @param RNGx RNG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
-{
- CLEAR_BIT(RNGx->CR, RNG_CR_IE);
-}
-
-/**
- * @brief Check if Random Number Generator Interrupt is enabled
- * (applies for either Seed error, Clock Error or Data ready interrupts)
- * @rmtoll CR IE LL_RNG_IsEnabledIT
- * @param RNGx RNG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
-{
- return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RNG_LL_EF_Data_Management Data Management
- * @{
- */
-
-/**
- * @brief Return32-bit Random Number value
- * @rmtoll DR RNDATA LL_RNG_ReadRandData32
- * @param RNGx RNG Instance
- * @retval Generated 32-bit random value
- */
-__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
-{
- return (uint32_t)(READ_REG(RNGx->DR));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* RNG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rtc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rtc.h
deleted file mode 100644
index 730493631a..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_rtc.h
+++ /dev/null
@@ -1,3360 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_RTC_H
-#define __STM32F2xx_LL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined(RTC)
-
-/** @defgroup RTC_LL RTC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_LL_Private_Constants RTC Private Constants
- * @{
- */
-/* Masks Definition */
-#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-
-/* Write protection defines */
-#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
-#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
-#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
-
-/* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY 24U
-#define RTC_OFFSET_DAY 16U
-#define RTC_OFFSET_MONTH 8U
-#define RTC_OFFSET_HOUR 16U
-#define RTC_OFFSET_MINUTE 8U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_Private_Macros RTC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
- * @{
- */
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
- This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetHourFormat(). */
-
- uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetAsynchPrescaler(). */
-
- uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetSynchPrescaler(). */
-} LL_RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
-
- uint8_t Hours; /*!< Specifies the RTC Time Hours.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
-} LL_RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
-
- uint8_t Month; /*!< Specifies the RTC Date Month.
- This parameter can be a value of @ref RTC_LL_EC_MONTH
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
-
- uint8_t Day; /*!< Specifies the RTC Date Day.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
-} LL_RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
- or @ref LL_RTC_ALMB_SetMask() for ALARM B
- */
-
- uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
- This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
- for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
- */
-
- uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
- If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
- for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
-
- If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
-
- This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
- for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
- */
-} LL_RTC_AlarmTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
- * @{
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EC_FORMAT FORMAT
- * @{
- */
-#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
- * @{
- */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
- * @{
- */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RTC_ReadReg function
- * @{
- */
-#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
-#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
-#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
-#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
-#define LL_RTC_ISR_TSF RTC_ISR_TSF
-#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
-#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
-#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
-#define LL_RTC_ISR_INITF RTC_ISR_INITF
-#define LL_RTC_ISR_RSF RTC_ISR_RSF
-#define LL_RTC_ISR_INITS RTC_ISR_INITS
-#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
-#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
-#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
-#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
- * @{
- */
-#define LL_RTC_CR_TSIE RTC_CR_TSIE
-#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
-#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
-#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
-#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
- * @{
- */
-#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */
-#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
-#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */
-#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */
-#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */
-#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
-#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_MONTH MONTH
- * @{
- */
-#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */
-#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */
-#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */
-#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */
-#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */
-#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */
-#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */
-#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */
-#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */
-#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */
-#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */
-#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
- * @{
- */
-#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
-#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
- * @{
- */
-#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
-#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
-#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
-#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
- * @{
- */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
-#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
- * @{
- */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
-#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
- * @{
- */
-#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
-/**
- * @}
- */
-
-
-/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
- * @{
- */
-#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
-#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
-#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
- * @{
- */
-#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
- * @{
- */
-#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
-#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
- * @{
- */
-#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
- * @{
- */
-#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
- * @{
- */
-#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
-#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER TAMPER
- * @{
- */
-#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
- * @{
- */
-#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
- * @{
- */
-#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-/**
- * @}
- */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
- * @{
- */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
-#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
-#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
- * @{
- */
-#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
-#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
- * @{
- */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
-/**
- * @}
- */
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
- * @{
- */
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
- * @{
- */
-#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */
-#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_BKP BACKUP
- * @{
- */
-#define LL_RTC_BKP_DR0 0x00000000U
-#define LL_RTC_BKP_DR1 0x00000001U
-#define LL_RTC_BKP_DR2 0x00000002U
-#define LL_RTC_BKP_DR3 0x00000003U
-#define LL_RTC_BKP_DR4 0x00000004U
-#if RTC_BKP_NUMBER > 5
-#define LL_RTC_BKP_DR5 0x00000005U
-#define LL_RTC_BKP_DR6 0x00000006U
-#define LL_RTC_BKP_DR7 0x00000007U
-#define LL_RTC_BKP_DR8 0x00000008U
-#define LL_RTC_BKP_DR9 0x00000009U
-#define LL_RTC_BKP_DR10 0x0000000AU
-#define LL_RTC_BKP_DR11 0x0000000BU
-#define LL_RTC_BKP_DR12 0x0000000CU
-#define LL_RTC_BKP_DR13 0x0000000DU
-#define LL_RTC_BKP_DR14 0x0000000EU
-#define LL_RTC_BKP_DR15 0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5 */
-
-#if RTC_BKP_NUMBER > 16
-#define LL_RTC_BKP_DR16 0x00000010U
-#define LL_RTC_BKP_DR17 0x00000011U
-#define LL_RTC_BKP_DR18 0x00000012U
-#define LL_RTC_BKP_DR19 0x00000013U
-#endif /* RTC_BKP_NUMBER > 16 */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
- * @{
- */
-#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_SIGN Coarse digital calibration sign
- * @{
- */
-#define LL_RTC_CALIB_SIGN_POSITIVE 0x00000000U /*!< Positive calibration: calendar update frequency is increased */
-#define LL_RTC_CALIB_SIGN_NEGATIVE RTC_CALIBR_DCS /*!< Negative calibration: calendar update frequency is decreased */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
- * @{
- */
-#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
-#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
- * @{
- */
-#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
-#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TSINSEL TIMESTAMP mapping
- * @{
- */
-#define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */
-#define LL_RTC_TimeStampPin_Pos1 RTC_TAFCR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMP1INSEL TAMPER1 mapping
- * @{
- */
-#define LL_RTC_TamperPin_Default 0x00000000U /*!< Use RTC_AF1 as TAMPER1 */
-#define LL_RTC_TamperPin_Pos1 RTC_TAFCR_TAMP1INSEL /*!< Use RTC_AF2 as TAMPER1 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Convert Convert helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
- * @param __VALUE__ Byte to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
-
-/**
- * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
- * @param __VALUE__ BCD value to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Date Date helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to retrieve weekday.
- * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Year in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Year in BCD format (0x00 . . . 0x99)
- */
-#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Month in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve Day in BCD format
- * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
- * @retval Day in BCD format (0x01 . . . 0x31)
- */
-#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Time Time helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to retrieve hour in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
- */
-#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve minute in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Minutes in BCD format (0x00. . .0x59)
- */
-#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
-
-/**
- * @brief Helper macro to retrieve second in BCD format
- * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
- * @retval Seconds in format (0x00. . .0x59)
- */
-#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Set Hours format (24 hour/day or AM/PM hour format)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR FMT LL_RTC_SetHourFormat
- * @param RTCx RTC Instance
- * @param HourFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_HOURFORMAT_24HOUR
- * @arg @ref LL_RTC_HOURFORMAT_AMPM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
-}
-
-/**
- * @brief Get Hours format (24 hour/day or AM/PM hour format)
- * @rmtoll CR FMT LL_RTC_GetHourFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_HOURFORMAT_24HOUR
- * @arg @ref LL_RTC_HOURFORMAT_AMPM
- */
-__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
-}
-
-/**
- * @brief Select the flag to be routed to RTC_ALARM output
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent
- * @param RTCx RTC Instance
- * @param AlarmOutput This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALARMOUT_DISABLE
- * @arg @ref LL_RTC_ALARMOUT_ALMA
- * @arg @ref LL_RTC_ALARMOUT_ALMB
- * @arg @ref LL_RTC_ALARMOUT_WAKEUP
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
-}
-
-/**
- * @brief Get the flag to be routed to RTC_ALARM output
- * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALARMOUT_DISABLE
- * @arg @ref LL_RTC_ALARMOUT_ALMA
- * @arg @ref LL_RTC_ALARMOUT_ALMB
- * @arg @ref LL_RTC_ALARMOUT_WAKEUP
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
-}
-
-/**
- * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
- * @note Used only when RTC_ALARM is mapped on PC13
- * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
- * @param RTCx RTC Instance
- * @param Output This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
-}
-
-/**
- * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
- * @note used only when RTC_ALARM is mapped on PC13
- * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
- * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
-}
-
-/**
- * @brief Enable initialization mode
- * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
- * and prescaler register (RTC_PRER).
- * Counters are stopped and start counting from the new value when INIT is reset.
- * @rmtoll ISR INIT LL_RTC_EnableInitMode
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
-{
- /* Set the Initialization mode */
- WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
-}
-
-/**
- * @brief Disable initialization mode (Free running mode)
- * @rmtoll ISR INIT LL_RTC_DisableInitMode
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
-{
- /* Exit Initialization mode */
- WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
-}
-
-/**
- * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR POL LL_RTC_SetOutputPolarity
- * @param RTCx RTC Instance
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
-}
-
-/**
- * @brief Get Output polarity
- * @rmtoll CR POL LL_RTC_GetOutputPolarity
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
- * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
- */
-__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
-}
-
-/**
- * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR REFCKON LL_RTC_EnableRefClock
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
- * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR REFCKON LL_RTC_DisableRefClock
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
-}
-
-/**
- * @brief Set Asynchronous prescaler factor
- * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler
- * @param RTCx RTC Instance
- * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
-{
- MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
- * @brief Set Synchronous prescaler factor
- * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler
- * @param RTCx RTC Instance
- * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
-{
- MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
-}
-
-/**
- * @brief Get Asynchronous prescaler factor
- * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0x7F
- */
-__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
-}
-
-/**
- * @brief Get Synchronous prescaler factor
- * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
- */
-__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
-}
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @rmtoll WPR KEY LL_RTC_EnableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
-}
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @rmtoll WPR KEY LL_RTC_DisableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
- WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Time Time
- * @{
- */
-
-/**
- * @brief Set time format (AM/24-hour or PM notation)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll TR PM LL_RTC_TIME_SetFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
-}
-
-/**
- * @brief Get time format (AM or PM notation)
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @rmtoll TR PM LL_RTC_TIME_GetFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
-}
-
-/**
- * @brief Set Hours in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
- * @rmtoll TR HT LL_RTC_TIME_SetHour\n
- * TR HU LL_RTC_TIME_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
-}
-
-/**
- * @brief Get Hours in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
- * Binary format
- * @rmtoll TR HT LL_RTC_TIME_GetHour\n
- * TR HU LL_RTC_TIME_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
-}
-
-/**
- * @brief Set Minutes in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n
- * TR MNU LL_RTC_TIME_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
- (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
-}
-
-/**
- * @brief Get Minutes in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
- * to Binary format
- * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n
- * TR MNU LL_RTC_TIME_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
-}
-
-/**
- * @brief Set Seconds in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll TR ST LL_RTC_TIME_SetSecond\n
- * TR SU LL_RTC_TIME_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
-}
-
-/**
- * @brief Get Seconds in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
- * to Binary format
- * @rmtoll TR ST LL_RTC_TIME_GetSecond\n
- * TR SU LL_RTC_TIME_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
-}
-
-/**
- * @brief Set time (hour, minute and second) in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @note TimeFormat and Hours should follow the same format
- * @rmtoll TR PM LL_RTC_TIME_Config\n
- * TR HT LL_RTC_TIME_Config\n
- * TR HU LL_RTC_TIME_Config\n
- * TR MNT LL_RTC_TIME_Config\n
- * TR MNU LL_RTC_TIME_Config\n
- * TR ST LL_RTC_TIME_Config\n
- * TR SU LL_RTC_TIME_Config
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
- * @arg @ref LL_RTC_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | \
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
- MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
-}
-
-/**
- * @brief Get time (hour, minute and second) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
- * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll TR HT LL_RTC_TIME_Get\n
- * TR HU LL_RTC_TIME_Get\n
- * TR MNT LL_RTC_TIME_Get\n
- * TR MNU LL_RTC_TIME_Get\n
- * TR ST LL_RTC_TIME_Get\n
- * TR SU LL_RTC_TIME_Get
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
- (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
- ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
-}
-
-/**
- * @brief Memorize whether the daylight saving time change has been performed
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
- * @brief Disable memorization whether the daylight saving time change has been performed.
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
-}
-
-/**
- * @brief Check if RTC Day Light Saving stored operation has been enabled or not
- * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
-}
-
-/**
- * @brief Subtract 1 hour (winter time change)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR SUB1H LL_RTC_TIME_DecHour
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_SUB1H);
-}
-
-/**
- * @brief Add 1 hour (summer time change)
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ADD1H LL_RTC_TIME_IncHour
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ADD1H);
-}
-
-
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Date Date
- * @{
- */
-
-/**
- * @brief Set Year in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
- * @rmtoll DR YT LL_RTC_DATE_SetYear\n
- * DR YU LL_RTC_DATE_SetYear
- * @param RTCx RTC Instance
- * @param Year Value between Min_Data=0x00 and Max_Data=0x99
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
-}
-
-/**
- * @brief Get Year in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
- * @rmtoll DR YT LL_RTC_DATE_GetYear\n
- * DR YU LL_RTC_DATE_GetYear
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x99
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
-}
-
-/**
- * @brief Set Week day
- * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
-}
-
-/**
- * @brief Get Week day
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
-}
-
-/**
- * @brief Set Month in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
- * @rmtoll DR MT LL_RTC_DATE_SetMonth\n
- * DR MU LL_RTC_DATE_SetMonth
- * @param RTCx RTC Instance
- * @param Month This parameter can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
- (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
-}
-
-/**
- * @brief Get Month in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
- * @rmtoll DR MT LL_RTC_DATE_GetMonth\n
- * DR MU LL_RTC_DATE_GetMonth
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
-}
-
-/**
- * @brief Set Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll DR DT LL_RTC_DATE_SetDay\n
- * DR DU LL_RTC_DATE_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
-}
-
-/**
- * @brief Get Day in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll DR DT LL_RTC_DATE_GetDay\n
- * DR DU LL_RTC_DATE_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
-}
-
-/**
- * @brief Set date (WeekDay, Day, Month and Year) in BCD format
- * @rmtoll DR WDU LL_RTC_DATE_Config\n
- * DR MT LL_RTC_DATE_Config\n
- * DR MU LL_RTC_DATE_Config\n
- * DR DT LL_RTC_DATE_Config\n
- * DR DU LL_RTC_DATE_Config\n
- * DR YT LL_RTC_DATE_Config\n
- * DR YU LL_RTC_DATE_Config
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @param Month This parameter can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- * @param Year Value between Min_Data=0x00 and Max_Data=0x99
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
-{
- register uint32_t temp = 0U;
-
- temp = (WeekDay << RTC_DR_WDU_Pos) | \
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
- (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
-
- MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
-}
-
-/**
- * @brief Get date (WeekDay, Day, Month and Year) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
- * before reading this bit
- * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
- * and __LL_RTC_GET_DAY are available to get independently each parameter.
- * @rmtoll DR WDU LL_RTC_DATE_Get\n
- * DR MT LL_RTC_DATE_Get\n
- * DR MU LL_RTC_DATE_Get\n
- * DR DT LL_RTC_DATE_Get\n
- * DR DU LL_RTC_DATE_Get\n
- * DR YT LL_RTC_DATE_Get\n
- * DR YU LL_RTC_DATE_Get
- * @param RTCx RTC Instance
- * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
- */
-__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
- (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
- (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
- ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_ALARMA ALARMA
- * @{
- */
-
-/**
- * @brief Enable Alarm A
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAE LL_RTC_ALMA_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
- * @brief Disable Alarm A
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAE LL_RTC_ALMA_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
-}
-
-/**
- * @brief Specify the Alarm A masks.
- * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
- * ALRMAR MSK1 LL_RTC_ALMA_SetMask
- * @param RTCx RTC Instance
- * @param Mask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_ALMA_MASK_NONE
- * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMA_MASK_HOURS
- * @arg @ref LL_RTC_ALMA_MASK_MINUTES
- * @arg @ref LL_RTC_ALMA_MASK_SECONDS
- * @arg @ref LL_RTC_ALMA_MASK_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
-}
-
-/**
- * @brief Get the Alarm A masks.
- * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
- * ALRMAR MSK1 LL_RTC_ALMA_GetMask
- * @param RTCx RTC Instance
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_RTC_ALMA_MASK_NONE
- * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMA_MASK_HOURS
- * @arg @ref LL_RTC_ALMA_MASK_MINUTES
- * @arg @ref LL_RTC_ALMA_MASK_SECONDS
- * @arg @ref LL_RTC_ALMA_MASK_ALL
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
-}
-
-/**
- * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
- * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
- * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
- * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
-}
-
-/**
- * @brief Set ALARM A Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n
- * ALRMAR DU LL_RTC_ALMA_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
- (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n
- * ALRMAR DU LL_RTC_ALMA_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
- * @brief Set ALARM A Weekday
- * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
-}
-
-/**
- * @brief Get ALARM A Weekday
- * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
-}
-
-/**
- * @brief Set Alarm A time format (AM/24-hour or PM notation)
- * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
-}
-
-/**
- * @brief Get Alarm A time format (AM or PM notation)
- * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
-}
-
-/**
- * @brief Set ALARM A Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
- * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n
- * ALRMAR HU LL_RTC_ALMA_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
- (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n
- * ALRMAR HU LL_RTC_ALMA_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
-}
-
-/**
- * @brief Set ALARM A Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n
- * ALRMAR MNU LL_RTC_ALMA_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
- (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n
- * ALRMAR MNU LL_RTC_ALMA_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
-}
-
-/**
- * @brief Set ALARM A Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n
- * ALRMAR SU LL_RTC_ALMA_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
-}
-
-/**
- * @brief Get ALARM A Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n
- * ALRMAR SU LL_RTC_ALMA_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
-}
-
-/**
- * @brief Set Alarm A Time (hour, minute and second) in BCD format
- * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n
- * ALRMAR HT LL_RTC_ALMA_ConfigTime\n
- * ALRMAR HU LL_RTC_ALMA_ConfigTime\n
- * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
- * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
- * ALRMAR ST LL_RTC_ALMA_ConfigTime\n
- * ALRMAR SU LL_RTC_ALMA_ConfigTime
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
-
- MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
-}
-
-/**
- * @brief Get Alarm B Time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n
- * ALRMAR HU LL_RTC_ALMA_GetTime\n
- * ALRMAR MNT LL_RTC_ALMA_GetTime\n
- * ALRMAR MNU LL_RTC_ALMA_GetTime\n
- * ALRMAR ST LL_RTC_ALMA_GetTime\n
- * ALRMAR SU LL_RTC_ALMA_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_ALARMB ALARMB
- * @{
- */
-
-/**
- * @brief Enable Alarm B
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBE LL_RTC_ALMB_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
- * @brief Disable Alarm B
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBE LL_RTC_ALMB_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
-}
-
-/**
- * @brief Specify the Alarm B masks.
- * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
- * ALRMBR MSK1 LL_RTC_ALMB_SetMask
- * @param RTCx RTC Instance
- * @param Mask This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_ALMB_MASK_NONE
- * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMB_MASK_HOURS
- * @arg @ref LL_RTC_ALMB_MASK_MINUTES
- * @arg @ref LL_RTC_ALMB_MASK_SECONDS
- * @arg @ref LL_RTC_ALMB_MASK_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
-}
-
-/**
- * @brief Get the Alarm B masks.
- * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
- * ALRMBR MSK1 LL_RTC_ALMB_GetMask
- * @param RTCx RTC Instance
- * @retval Returned value can be can be a combination of the following values:
- * @arg @ref LL_RTC_ALMB_MASK_NONE
- * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
- * @arg @ref LL_RTC_ALMB_MASK_HOURS
- * @arg @ref LL_RTC_ALMB_MASK_MINUTES
- * @arg @ref LL_RTC_ALMB_MASK_SECONDS
- * @arg @ref LL_RTC_ALMB_MASK_ALL
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
-}
-
-/**
- * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
- * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
- * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
- * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
-}
-
-/**
- * @brief Set ALARM B Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
- * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n
- * ALRMBR DU LL_RTC_ALMB_SetDay
- * @param RTCx RTC Instance
- * @param Day Value between Min_Data=0x01 and Max_Data=0x31
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
- (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n
- * ALRMBR DU LL_RTC_ALMB_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
- * @brief Set ALARM B Weekday
- * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay
- * @param RTCx RTC Instance
- * @param WeekDay This parameter can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
-}
-
-/**
- * @brief Get ALARM B Weekday
- * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
-}
-
-/**
- * @brief Set ALARM B time format (AM/24-hour or PM notation)
- * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat
- * @param RTCx RTC Instance
- * @param TimeFormat This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
-{
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
-}
-
-/**
- * @brief Get ALARM B time format (AM or PM notation)
- * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
-}
-
-/**
- * @brief Set ALARM B Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
- * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n
- * ALRMBR HU LL_RTC_ALMB_SetHour
- * @param RTCx RTC Instance
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
- (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n
- * ALRMBR HU LL_RTC_ALMB_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
-}
-
-/**
- * @brief Set ALARM B Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
- * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n
- * ALRMBR MNU LL_RTC_ALMB_SetMinute
- * @param RTCx RTC Instance
- * @param Minutes between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
- (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n
- * ALRMBR MNU LL_RTC_ALMB_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
-}
-
-/**
- * @brief Set ALARM B Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
- * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n
- * ALRMBR SU LL_RTC_ALMB_SetSecond
- * @param RTCx RTC Instance
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
-{
- MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
- (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
-}
-
-/**
- * @brief Get ALARM B Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n
- * ALRMBR SU LL_RTC_ALMB_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
-{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
- return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
-}
-
-/**
- * @brief Set Alarm B Time (hour, minute and second) in BCD format
- * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n
- * ALRMBR HT LL_RTC_ALMB_ConfigTime\n
- * ALRMBR HU LL_RTC_ALMB_ConfigTime\n
- * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
- * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
- * ALRMBR ST LL_RTC_ALMB_ConfigTime\n
- * ALRMBR SU LL_RTC_ALMB_ConfigTime
- * @param RTCx RTC Instance
- * @param Format12_24 This parameter can be one of the following values:
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
- * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
- * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
- * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
-{
- register uint32_t temp = 0U;
-
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
-
- MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
-}
-
-/**
- * @brief Get Alarm B Time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n
- * ALRMBR HU LL_RTC_ALMB_GetTime\n
- * ALRMBR MNT LL_RTC_ALMB_GetTime\n
- * ALRMBR MNU LL_RTC_ALMB_GetTime\n
- * ALRMBR ST LL_RTC_ALMB_GetTime\n
- * ALRMBR SU LL_RTC_ALMB_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Timestamp Timestamp
- * @{
- */
-
-/**
- * @brief Enable Timestamp
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSE LL_RTC_TS_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
- * @brief Disable Timestamp
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSE LL_RTC_TS_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
-}
-
-/**
- * @brief Set Time-stamp event active edge
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
- * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge
- * @param RTCx RTC Instance
- * @param Edge This parameter can be one of the following values:
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
-}
-
-/**
- * @brief Get Time-stamp event active edge
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
- * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
-}
-
-/**
- * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
- * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
- * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
-}
-
-/**
- * @brief Get Timestamp Hours in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
- * @rmtoll TSTR HT LL_RTC_TS_GetHour\n
- * TSTR HU LL_RTC_TS_GetHour
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
-}
-
-/**
- * @brief Get Timestamp Minutes in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
- * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n
- * TSTR MNU LL_RTC_TS_GetMinute
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
-}
-
-/**
- * @brief Get Timestamp Seconds in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
- * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n
- * TSTR SU LL_RTC_TS_GetSecond
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x59
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
- * @brief Get Timestamp time (hour, minute and second) in BCD format
- * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
- * are available to get independently each parameter.
- * @rmtoll TSTR HT LL_RTC_TS_GetTime\n
- * TSTR HU LL_RTC_TS_GetTime\n
- * TSTR MNT LL_RTC_TS_GetTime\n
- * TSTR MNU LL_RTC_TS_GetTime\n
- * TSTR ST LL_RTC_TS_GetTime\n
- * TSTR SU LL_RTC_TS_GetTime
- * @param RTCx RTC Instance
- * @retval Combination of hours, minutes and seconds.
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSTR,
- RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
-}
-
-/**
- * @brief Get Timestamp Week day
- * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WEEKDAY_MONDAY
- * @arg @ref LL_RTC_WEEKDAY_TUESDAY
- * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
- * @arg @ref LL_RTC_WEEKDAY_THURSDAY
- * @arg @ref LL_RTC_WEEKDAY_FRIDAY
- * @arg @ref LL_RTC_WEEKDAY_SATURDAY
- * @arg @ref LL_RTC_WEEKDAY_SUNDAY
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
-}
-
-/**
- * @brief Get Timestamp Month in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
- * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n
- * TSDR MU LL_RTC_TS_GetMonth
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_MONTH_JANUARY
- * @arg @ref LL_RTC_MONTH_FEBRUARY
- * @arg @ref LL_RTC_MONTH_MARCH
- * @arg @ref LL_RTC_MONTH_APRIL
- * @arg @ref LL_RTC_MONTH_MAY
- * @arg @ref LL_RTC_MONTH_JUNE
- * @arg @ref LL_RTC_MONTH_JULY
- * @arg @ref LL_RTC_MONTH_AUGUST
- * @arg @ref LL_RTC_MONTH_SEPTEMBER
- * @arg @ref LL_RTC_MONTH_OCTOBER
- * @arg @ref LL_RTC_MONTH_NOVEMBER
- * @arg @ref LL_RTC_MONTH_DECEMBER
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
-}
-
-/**
- * @brief Get Timestamp Day in BCD format
- * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
- * @rmtoll TSDR DT LL_RTC_TS_GetDay\n
- * TSDR DU LL_RTC_TS_GetDay
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x01 and Max_Data=0x31
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-/**
- * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
- * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
- * and __LL_RTC_GET_DAY are available to get independently each parameter.
- * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n
- * TSDR MT LL_RTC_TS_GetDate\n
- * TSDR MU LL_RTC_TS_GetDate\n
- * TSDR DT LL_RTC_TS_GetDate\n
- * TSDR DU LL_RTC_TS_GetDate
- * @param RTCx RTC Instance
- * @retval Combination of Weekday, Day and Month
- */
-__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
-}
-
-
-#if defined(RTC_TAFCR_TAMPTS)
-/**
- * @brief Activate timestamp on tamper detection event
- * @rmtoll TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-
-/**
- * @brief Disable timestamp on tamper detection event
- * @rmtoll TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
-}
-#endif /* RTC_TAFCR_TAMPTS */
-
-/**
- * @brief Set timestamp Pin
- * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin
- * @param RTCx RTC Instance
- * @param TSPin specifies the RTC TimeStamp Pin.
- * This parameter can be one of the following values:
- * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp.
- * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL, TSPin);
-}
-
-/**
- * @brief Get timestamp Pin
- * @rmtoll TAFCR TSINSEL LL_RTC_TS_GetPin
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp Pin.
- * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp Pin.
- * @retval None
- */
-
-__STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Tamper Tamper
- * @{
- */
-
-/**
- * @brief Enable RTC_TAMPx input detection
- * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Enable\n
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- *
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @brief Clear RTC_TAMPx input detection
- * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Disable\n
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- *
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-#if defined(RTC_TAFCR_TAMPPUDIS)
-/**
- * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
- * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-
-/**
- * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
- * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
-}
-#endif /* RTC_TAFCR_TAMPPUDIS */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
-/**
- * @brief Set RTC_TAMPx precharge duration
- * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
- * @param RTCx RTC Instance
- * @param Duration This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
-}
-
-/**
- * @brief Get RTC_TAMPx precharge duration
- * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
- * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
-}
-#endif /* RTC_TAFCR_TAMPPRCH */
-
-#if defined(RTC_TAFCR_TAMPFLT)
-/**
- * @brief Set RTC_TAMPx filter count
- * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
- * @param RTCx RTC Instance
- * @param FilterCount This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
- * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
-}
-
-/**
- * @brief Get RTC_TAMPx filter count
- * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
- * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
- * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
-}
-#endif /* RTC_TAFCR_TAMPFLT */
-
-#if defined(RTC_TAFCR_TAMPFREQ)
-/**
- * @brief Set Tamper sampling frequency
- * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
- * @param RTCx RTC Instance
- * @param SamplingFreq This parameter can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
-}
-
-/**
- * @brief Get Tamper sampling frequency
- * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
- * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
-}
-#endif /* RTC_TAFCR_TAMPFREQ */
-
-/**
- * @brief Enable Active level for Tamper input
- * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- *
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- SET_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @brief Disable Active level for Tamper input
- * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
- * @param RTCx RTC Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- *
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
-{
- CLEAR_BIT(RTCx->TAFCR, Tamper);
-}
-
-/**
- * @brief Set Tamper Pin
- * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_SetPin
- * @param RTCx RTC Instance
- * @param TamperPin specifies the RTC Tamper Pin.
- * This parameter can be one of the following values:
- * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper.
- * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin)
-{
- MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL, TamperPin);
-}
-
-/**
- * @brief Get Tamper Pin
- * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_GetPin
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin.
- * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin.
- * @retval None
- */
-
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPin(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Wakeup Wakeup
- * @{
- */
-
-/**
- * @brief Enable Wakeup timer
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
- * @brief Disable Wakeup timer
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
-}
-
-/**
- * @brief Check if Wakeup timer is enabled or not
- * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
-}
-
-/**
- * @brief Select Wakeup clock
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
- * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
- * @param RTCx RTC Instance
- * @param WakeupClock This parameter can be one of the following values:
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
-}
-
-/**
- * @brief Get Wakeup clock
- * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
- * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
- * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
-}
-
-/**
- * @brief Set Wakeup auto-reload value
- * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
- * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
- * @param RTCx RTC Instance
- * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
-{
- MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
-}
-
-/**
- * @brief Get Wakeup auto-reload value
- * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload
- * @param RTCx RTC Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister
- * @param RTCx RTC Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR0
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5
- * @arg @ref LL_RTC_BKP_DR6
- * @arg @ref LL_RTC_BKP_DR7
- * @arg @ref LL_RTC_BKP_DR8
- * @arg @ref LL_RTC_BKP_DR9
- * @arg @ref LL_RTC_BKP_DR10
- * @arg @ref LL_RTC_BKP_DR11
- * @arg @ref LL_RTC_BKP_DR12
- * @arg @ref LL_RTC_BKP_DR13
- * @arg @ref LL_RTC_BKP_DR14
- * @arg @ref LL_RTC_BKP_DR15
- * @arg @ref LL_RTC_BKP_DR16
- * @arg @ref LL_RTC_BKP_DR17
- * @arg @ref LL_RTC_BKP_DR18
- * @arg @ref LL_RTC_BKP_DR19
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister
- * @param RTCx RTC Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR0
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5
- * @arg @ref LL_RTC_BKP_DR6
- * @arg @ref LL_RTC_BKP_DR7
- * @arg @ref LL_RTC_BKP_DR8
- * @arg @ref LL_RTC_BKP_DR9
- * @arg @ref LL_RTC_BKP_DR10
- * @arg @ref LL_RTC_BKP_DR11
- * @arg @ref LL_RTC_BKP_DR12
- * @arg @ref LL_RTC_BKP_DR13
- * @arg @ref LL_RTC_BKP_DR14
- * @arg @ref LL_RTC_BKP_DR15
- * @arg @ref LL_RTC_BKP_DR16
- * @arg @ref LL_RTC_BKP_DR17
- * @arg @ref LL_RTC_BKP_DR18
- * @arg @ref LL_RTC_BKP_DR19
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Calibration Calibration
- * @{
- */
-
-/**
- * @brief Set Calibration output frequency (1 Hz or 512 Hz)
- * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n
- * CR COSEL LL_RTC_CAL_SetOutputFreq
- * @param RTCx RTC Instance
- * @param Frequency This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
-{
- MODIFY_REG(RTCx->CR, RTC_CR_COE, Frequency);
-}
-
-/**
- * @brief Get Calibration output frequency (1 Hz or 512 Hz)
- * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n
- * CR COSEL LL_RTC_CAL_GetOutputFreq
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE));
-}
-
-/**
- * @brief Enable Coarse digital calibration
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR DCE LL_RTC_CAL_EnableCoarseDigital
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_EnableCoarseDigital(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_DCE);
-}
-
-/**
- * @brief Disable Coarse digital calibration
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CR DCE LL_RTC_CAL_DisableCoarseDigital
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_DisableCoarseDigital(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_DCE);
-}
-
-/**
- * @brief Set the coarse digital calibration
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
- * @rmtoll CALIBR DCS LL_RTC_CAL_ConfigCoarseDigital\n
- * CALIBR DC LL_RTC_CAL_ConfigCoarseDigital
- * @param RTCx RTC Instance
- * @param Sign This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
- * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
- * @param Value value of coarse calibration expressed in ppm (coded on 5 bits)
- * @note This Calibration value should be between 0 and 63 when using negative sign with a 2-ppm step.
- * @note This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef *RTCx, uint32_t Sign, uint32_t Value)
-{
- MODIFY_REG(RTCx->CALIBR, RTC_CALIBR_DCS | RTC_CALIBR_DC, Sign | Value);
-}
-
-/**
- * @brief Get the coarse digital calibration value
- * @rmtoll CALIBR DC LL_RTC_CAL_GetCoarseDigitalValue
- * @param RTCx RTC Instance
- * @retval value of coarse calibration expressed in ppm (coded on 5 bits)
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalValue(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DC));
-}
-
-/**
- * @brief Get the coarse digital calibration sign
- * @rmtoll CALIBR DCS LL_RTC_CAL_GetCoarseDigitalSign
- * @param RTCx RTC Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE
- * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef *RTCx)
-{
- return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DCS));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-
-
-
-/**
- * @brief Get RTC_TAMP1 detection flag
- * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
-}
-
-/**
- * @brief Get Time-stamp overflow flag
- * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
-}
-
-/**
- * @brief Get Time-stamp flag
- * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
-}
-
-/**
- * @brief Get Wakeup timer flag
- * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
-}
-
-/**
- * @brief Get Alarm B flag
- * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
-}
-
-/**
- * @brief Get Alarm A flag
- * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
-}
-
-
-
-/**
- * @brief Clear RTC_TAMP1 detection flag
- * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Time-stamp overflow flag
- * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Time-stamp flag
- * @rmtoll ISR TSF LL_RTC_ClearFlag_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Wakeup timer flag
- * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Alarm B flag
- * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Clear Alarm A flag
- * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Get Initialization flag
- * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
-}
-
-/**
- * @brief Get Registers synchronization flag
- * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
-}
-
-/**
- * @brief Clear Registers synchronization flag
- * @rmtoll ISR RSF LL_RTC_ClearFlag_RS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
-{
- WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Get Initialization status flag
- * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
-}
-
-
-/**
- * @brief Get Wakeup timer write flag
- * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
-}
-
-/**
- * @brief Get Alarm B write flag
- * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
-}
-
-/**
- * @brief Get Alarm A write flag
- * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Time-stamp interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSIE LL_RTC_EnableIT_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-/**
- * @brief Disable Time-stamp interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR TSIE LL_RTC_DisableIT_TS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
-}
-
-/**
- * @brief Enable Wakeup timer interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-
-/**
- * @brief Disable Wakeup timer interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
-}
-
-/**
- * @brief Enable Alarm B interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
- * @brief Disable Alarm B interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
-}
-
-/**
- * @brief Enable Alarm A interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
- * @brief Disable Alarm A interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
-}
-
-/**
- * @brief Enable all Tamper Interrupt
- * @rmtoll TAFCR TAMPIE LL_RTC_EnableIT_TAMP
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
- * @brief Disable all Tamper Interrupt
- * @rmtoll TAFCR TAMPIE LL_RTC_DisableIT_TAMP
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
-}
-
-/**
- * @brief Check if Time-stamp interrupt is enabled or not
- * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
-}
-
-/**
- * @brief Check if Wakeup timer interrupt is enabled or not
- * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
-}
-
-/**
- * @brief Check if Alarm B interrupt is enabled or not
- * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
-}
-
-/**
- * @brief Check if Alarm A interrupt is enabled or not
- * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
-}
-
-/**
- * @brief Check if all the TAMPER interrupts are enabled or not
- * @rmtoll TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->TAFCR,
- RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
-ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
-void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
-ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RTC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
deleted file mode 100644
index 625eef78ee..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_sdmmc.h
+++ /dev/null
@@ -1,1115 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_sdmmc.h
- * @author MCD Application Team
- * @brief Header file of SDMMC HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_SDMMC_H
-#define STM32F2xx_LL_SDMMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(SDIO)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-/** @addtogroup STM32F2xx_Driver
- * @{
- */
-
-/** @addtogroup SDMMC_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
- * @{
- */
-
-/**
- * @brief SDMMC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
-
- uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
- enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
-
- uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
-
- uint32_t BusWide; /*!< Specifies the SDMMC bus width.
- This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
-
- uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
-}SDIO_InitTypeDef;
-
-
-/**
- * @brief SDMMC Command Control structure
- */
-typedef struct
-{
- uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register. */
-
- uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
- Max_Data = 64 */
-
- uint32_t Response; /*!< Specifies the SDMMC response type.
- This parameter can be a value of @ref SDMMC_LL_Response_Type */
-
- uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
- enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
-
- uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_CPSM_State */
-}SDIO_CmdInitTypeDef;
-
-
-/**
- * @brief SDMMC Data Control structure
- */
-typedef struct
-{
- uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
-
- uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
-
- uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
-
- uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_DPSM_State */
-}SDIO_DataInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
- * @{
- */
-#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
-
-/**
- * @brief SDMMC Commands Index
- */
-#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */
-#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD 64U /*!< No command */
-
-/**
- * @brief Following commands are SD Card Specific commands.
- * SDMMC_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */
-
-/**
- * @brief Following commands are SD Card Specific security commands.
- * SDMMC_CMD_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_SD_APP_GET_MKB 43U
-#define SDMMC_CMD_SD_APP_GET_MID 44U
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U
-#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U
-
-/**
- * @brief Masks for errors Card Status R1 (OCR Register)
- */
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
-#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
-#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
-#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
-#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
-#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
-#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
-#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
-#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
-#define SDMMC_OCR_CC_ERROR 0x00100000U
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
-#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
-#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
-#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
-#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
-#define SDMMC_OCR_ERASE_RESET 0x00002000U
-#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
-#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
-
-/**
- * @brief Masks for R6 Response
- */
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
-#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
-#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
-
-#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
-#define SDMMC_HIGH_CAPACITY 0x40000000U
-#define SDMMC_STD_CAPACITY 0x00000000U
-#define SDMMC_CHECK_PATTERN 0x000001AAU
-#define SD_SWITCH_1_8V_CAPACITY 0x01000000U
-
-#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-
-#define SDMMC_MAX_TRIAL 0x0000FFFFU
-
-#define SDMMC_ALLZERO 0x00000000U
-
-#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
-#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
-#define SDMMC_CARD_LOCKED 0x02000000U
-
-#ifndef SDMMC_DATATIMEOUT
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
-#endif /* SDMMC_DATATIMEOUT */
-
-#define SDMMC_0TO7BITS 0x000000FFU
-#define SDMMC_8TO15BITS 0x0000FF00U
-#define SDMMC_16TO23BITS 0x00FF0000U
-#define SDMMC_24TO31BITS 0xFF000000U
-#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
-
-#define SDMMC_HALFFIFO 0x00000008U
-#define SDMMC_HALFFIFOBYTES 0x00000020U
-
-/**
- * @brief Command Class supported
- */
-#define SDIO_CCCC_ERASE 0x00000020U
-
-#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
-#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
-#define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */
-
-/** @defgroup SDIO_LL_Clock_Edge Clock Edge
- * @{
- */
-#define SDIO_CLOCK_EDGE_RISING 0x00000000U
-#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
- * @{
- */
-#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
-#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
- * @{
- */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
-#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Bus_Wide Bus Width
- * @{
- */
-#define SDIO_BUS_WIDE_1B 0x00000000U
-#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
- ((WIDE) == SDIO_BUS_WIDE_4B) || \
- ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
- * @{
- */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Division Clock Division
- * @{
- */
-#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Command_Index Command Index
- * @{
- */
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Response_Type Response Type
- * @{
- */
-#define SDIO_RESPONSE_NO 0x00000000U
-#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
- ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
- ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
- * @{
- */
-#define SDIO_WAIT_NO 0x00000000U
-#define SDIO_WAIT_IT SDIO_CMD_WAITINT
-#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
- ((WAIT) == SDIO_WAIT_IT) || \
- ((WAIT) == SDIO_WAIT_PEND))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_CPSM_State CPSM State
- * @{
- */
-#define SDIO_CPSM_DISABLE 0x00000000U
-#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
- ((CPSM) == SDIO_CPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Response_Registers Response Register
- * @{
- */
-#define SDIO_RESP1 0x00000000U
-#define SDIO_RESP2 0x00000004U
-#define SDIO_RESP3 0x00000008U
-#define SDIO_RESP4 0x0000000CU
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
- ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || \
- ((RESP) == SDIO_RESP4))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Data_Length Data Length
- * @{
- */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
- * @{
- */
-#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
-#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
-#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
- * @{
- */
-#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
-#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Transfer_Type Transfer Type
- * @{
- */
-#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
-#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_DPSM_State DPSM State
- * @{
- */
-#define SDIO_DPSM_DISABLE 0x00000000U
-#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
- ((DPSM) == SDIO_DPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
- * @{
- */
-#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
-#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
- * @{
- */
-#define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE
-#define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE
-#define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE
-#define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE
-#define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE
-#define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE
-#define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE
-#define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE
-#define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE
-#define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE
-#define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE
-#define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE
-#define SDIO_IT_TXACT SDIO_MASK_TXACTIE
-#define SDIO_IT_RXACT SDIO_MASK_RXACTIE
-#define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE
-#define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE
-#define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE
-#define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE
-#define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE
-#define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE
-#define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE
-#define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE
-#define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE
-#define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Flags Flags
- * @{
- */
-#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
-#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
- SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
- SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
- SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))
-
-#define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
- SDIO_FLAG_CMDSENT))
-
-#define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
- SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
- * @{
- */
-
-/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
- * @{
- */
-/* ------------ SDIO registers bit address in the alias region -------------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
-#define CLKEN_BITNUMBER 0x08U
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
-#define SDIOSUSPEND_BITNUMBER 0x0BU
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER 0x0CU
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER 0x0DU
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER 0x0EU
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
-#define DMAEN_BITNUMBER 0x03U
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER 0x08U
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER 0x09U
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER 0x0AU
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER 0x0BU
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
- * @brief SDIO_LL registers bit address in the alias region
- * @{
- */
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
- SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
- SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
- SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
- SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
- SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO Initialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
-
-/* SDIO Data Transfer Frequency (25MHz max) */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x2)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
- * @brief Enable the SDIO device.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
-
-/**
- * @brief Disable the SDIO device.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
-
-/**
- * @brief Enable the SDIO DMA transfer.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
-
-/**
- * @brief Disable the SDIO DMA transfer.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
-
-/**
- * @brief Enable the SDIO device interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
- * @brief Disable the SDIO device interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
-
-
-/**
- * @brief Clears the SDIO pending flags.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received
- * @retval None
- */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt
- * @retval None
- */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
-
-/**
- * @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
-
-/**
- * @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
-
-/**
- * @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
-
-/**
- * @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
-
-/**
- * @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
-
-/**
- * @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-
-/**
- * @brief Enable the command completion signal.
- * @retval None
- */
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
-
-/**
- * @brief Disable the command completion signal.
- * @retval None
- */
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
-
-/**
- * @brief Enable the CE-ATA interrupt.
- * @retval None
- */
-#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
-
-/**
- * @brief Disable the CE-ATA interrupt.
- * @retval None
- */
-#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
-
-/**
- * @brief Enable send CE-ATA command (CMD61).
- * @retval None
- */
-#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
-
-/**
- * @brief Disable send CE-ATA command (CMD61).
- * @retval None
- */
-#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
- * @{
- */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
- * @}
- */
-
-/* I/O operation functions *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
- * @{
- */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
- * @{
- */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
-
-/* SDMMC Commands management functions */
-uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
-uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
-uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
-uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
-uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* SDIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_spi.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_spi.h
deleted file mode 100644
index 2912732b92..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_spi.h
+++ /dev/null
@@ -1,1991 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_SPI_H
-#define STM32F2xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @defgroup SPI_LL SPI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
- * @{
- */
-
-/**
- * @brief SPI Init structures definition
- */
-typedef struct
-{
- uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
- uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_LL_EC_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
- uint32_t DataWidth; /*!< Specifies the SPI data width.
- This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
- uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
- uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
- uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
- uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_SPI_ReadReg function
- * @{
- */
-#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
-#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
-#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
-#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
- * @{
- */
-#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
-#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
-#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
- * @{
- */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
- * @{
- */
-#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
- * @{
- */
-#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
-#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
-#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
- * @{
- */
-#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
-#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
-#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
- * @{
- */
-#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable SPI peripheral
- * @rmtoll CR1 SPE LL_SPI_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Disable SPI peripheral
- * @note When disabling the SPI, follow the procedure described in the Reference Manual.
- * @rmtoll CR1 SPE LL_SPI_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Check if SPI peripheral is enabled
- * @rmtoll CR1 SPE LL_SPI_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set SPI operation mode to Master or Slave
- * @note This bit should not be changed when communication is ongoing.
- * @rmtoll CR1 MSTR LL_SPI_SetMode\n
- * CR1 SSI LL_SPI_SetMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
- * @brief Get SPI operation mode (Master or Slave)
- * @rmtoll CR1 MSTR LL_SPI_GetMode\n
- * CR1 SSI LL_SPI_GetMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-/**
- * @brief Set serial protocol used
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR2 FRF LL_SPI_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
-}
-
-/**
- * @brief Get serial protocol used
- * @rmtoll CR2 FRF LL_SPI_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
- * @arg @ref LL_SPI_PROTOCOL_TI
- */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
-}
-
-/**
- * @brief Set clock phase
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
- * @param SPIx SPI Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
- * @brief Get clock phase
- * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
- * @brief Set clock polarity
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Get clock polarity
- * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
- * @brief Set baud rate prescaler
- * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
- * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @param BaudRate This parameter can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
- * @brief Get baud rate prescaler
- * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
- * @brief Set transfer bit order
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
- * @param SPIx SPI Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
- * @brief Get transfer bit order
- * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
- * @brief Set transfer direction mode
- * @note For Half-Duplex mode, Rx Direction is set by default.
- * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
- * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
- * CR1 BIDIOE LL_SPI_SetTransferDirection
- * @param SPIx SPI Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
- * @brief Get transfer direction mode
- * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
- * CR1 BIDIOE LL_SPI_GetTransferDirection
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
- * @brief Set frame data width
- * @rmtoll CR1 DFF LL_SPI_SetDataWidth
- * @param SPIx SPI Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
-}
-
-/**
- * @brief Get frame data width
- * @rmtoll CR1 DFF LL_SPI_GetDataWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
- * @{
- */
-
-/**
- * @brief Enable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Disable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Check if CRC is enabled
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set CRCNext to transfer CRC on the line
- * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
- * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
- * @brief Set polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
- * @param SPIx SPI Instance
- * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
- WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
- * @brief Get polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
- * @brief Get Rx CRC
- * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
- * @brief Get Tx CRC
- * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
- * @{
- */
-
-/**
- * @brief Set NSS mode
- * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
- * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
- * @param SPIx SPI Instance
- * @param NSS This parameter can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
- * @brief Get NSS mode
- * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
- uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
- return (Ssm | Ssoe);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get CRC error flag
- * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get mode fault error flag
- * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get busy flag
- * @note The BSY flag is cleared under any one of the following conditions:
- * -When the SPI is correctly disabled
- * -When a fault is detected in Master mode (MODF bit set to 1)
- * -In Master mode, when it finishes a data transmission and no new data is ready to be
- * sent
- * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
- * each data transfer.
- * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear CRC error flag
- * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
- * @brief Clear mode fault error flag
- * @note Clearing this flag is done by a read access to the SPIx_SR
- * register followed by a write access to the SPIx_CR1 register
- * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg_sr;
- tmpreg_sr = SPIx->SR;
- (void) tmpreg_sr;
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Clear overrun error flag
- * @note Clearing this flag is done by a read access to the SPIx_DR
- * register followed by a read access to the SPIx_SR register
- * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->DR;
- (void) tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @note Clearing this flag is done by reading SPIx_SR register
- * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Enable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Enable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Disable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Disable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Check if error interrupt is enabled
- * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Rx buffer not empty interrupt is enabled
- * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Check if Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
- * @param SPIx SPI Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
- return (uint32_t) &(SPIx->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
- * @{
- */
-
-/**
- * @brief Read 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData8
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
- return (*((__IO uint8_t *)&SPIx->DR));
-}
-
-/**
- * @brief Read 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Write 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData8
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
-#if defined (__GNUC__)
- __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
- *spidr = TxData;
-#else
- *((__IO uint8_t *)&SPIx->DR) = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
- * @brief Write 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
-#if defined (__GNUC__)
- __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
- *spidr = TxData;
-#else
- SPIx->DR = TxData;
-#endif /* __GNUC__ */
-}
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL I2S
- * @{
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_LL_EC_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
- This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
- Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
- and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
- uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2S_ReadReg function
- * @{
- */
-#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
-#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
-#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
- * @{
- */
-#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
-#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
-#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
- * @{
- */
-#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
-#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
-#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
-#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
-#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
-#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
- * @{
- */
-#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
- * @{
- */
-#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
- * @{
- */
-
-#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Select I2S mode and Enable I2S peripheral
- * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
- * I2SCFGR I2SE LL_I2S_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Disable I2S peripheral
- * @rmtoll I2SCFGR I2SE LL_I2S_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Check if I2S peripheral is enabled
- * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_SetDataFormat
- * @param SPIx SPI Instance
- * @param DataFormat This parameter can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
- * @brief Get I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_GetDataFormat
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
- * @brief Set I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
- * @brief Get I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
- * @brief Set I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
- * @brief Get I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
- * @brief Set I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
- * @brief Get I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
- * @brief Set I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
- * @param SPIx SPI Instance
- * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
- * @brief Get I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
- * @param SPIx SPI Instance
- * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
- * @brief Set I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
- * @param SPIx SPI Instance
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
- * @brief Get I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
- * @brief Enable the master clock output (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Disable the master clock output (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Check if the master clock output (Pin MCK) is enabled
- * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
- * @brief Get busy flag
- * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
- * @brief Get underrun error flag
- * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Get frame format error flag
- * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_FRE(SPIx);
-}
-
-/**
- * @brief Get channel side flag.
- * @note 0: Channel Left has to be transmitted or has been received\n
- * 1: Channel Right has to be transmitted or has been received\n
- * It has no significance in PCM mode.
- * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
- return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear overrun error flag
- * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
- * @brief Clear underrun error flag
- * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @brief Clear frame format error flag
- * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_FRE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
- * @brief Enable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Enable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
- * @brief Disable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
- * @brief Disable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Disable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
- * @brief Check if ERR IT is enabled
- * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
- * @brief Check if RXNE IT is enabled
- * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
- * @brief Check if TXE IT is enabled
- * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
- * @{
- */
-
-/**
- * @brief Read 16-Bits in data register
- * @rmtoll DR DR LL_I2S_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
- * @brief Write 16-Bits in data register
- * @rmtoll DR DR LL_I2S_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_system.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_system.h
deleted file mode 100644
index 35c0af0286..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_system.h
+++ /dev/null
@@ -1,846 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_system.h
- * @author MCD Application Team
- * @brief Header file of SYSTEM LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL SYSTEM driver contains a set of generic APIs that can be
- used by user:
- (+) Some of the FLASH features need to be handled in the SYSTEM file.
- (+) Access to DBGCMU registers
- (+) Access to SYSCFG registers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_SYSTEM_H
-#define __STM32F2xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- * @{
- */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
- * @{
- */
-#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
-#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
-/**
- * @}
- */
-
-#if defined(SYSCFG_PMC_MII_RMII_SEL)
-/** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
- * @{
- */
-#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */
-#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
-
-/**
- * @}
- */
-#endif /* SYSCFG_PMC_MII_RMII_SEL */
-
-
-
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
- * @{
- */
-#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
-#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
-#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
-#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
-#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
-#if defined(GPIOF)
-#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
-#endif /* GPIOG */
-#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */
-#if defined(GPIOI)
-#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */
-#endif /* GPIOI */
-#if defined(GPIOJ)
-#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */
-#endif /* GPIOJ */
-#if defined(GPIOK)
-#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */
-#endif /* GPIOK */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
- * @{
- */
-#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
- * @{
- */
-#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
-#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
- * @{
- */
-#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
-#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
-#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
-#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
-#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
-#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
-#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
-#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
- * @{
- */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
- * @{
- */
-/**
- * @brief Set memory mapping at address 0x00000000
- * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
- * @param Memory This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_REMAP_FLASH
- * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
- * @arg @ref LL_SYSCFG_REMAP_FSMC
- * @arg @ref LL_SYSCFG_REMAP_SRAM
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
-{
- MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
-}
-
-/**
- * @brief Get memory mapping at address 0x00000000
- * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_REMAP_FLASH
- * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
- * @arg @ref LL_SYSCFG_REMAP_SRAM
- * @arg @ref LL_SYSCFG_REMAP_FSMC
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
- return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
-}
-
-/**
- * @brief Enables the Compensation cell Power Down
- * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
-{
- SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
-}
-
-/**
- * @brief Disables the Compensation cell Power Down
- * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
- * @note The I/O compensation cell can be used only when the device supply
- * voltage ranges from 2.4 to 3.6 V
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
-{
- CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
-}
-
-/**
- * @brief Get Compensation Cell ready Flag
- * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
-{
- return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
-}
-#if defined(SYSCFG_PMC_MII_RMII_SEL)
-/**
- * @brief Select Ethernet PHY interface
- * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
- * @param Interface This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_PMC_ETHMII
- * @arg @ref LL_SYSCFG_PMC_ETHRMII
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
-{
- MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
-}
-
-/**
- * @brief Get Ethernet PHY interface
- * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_PMC_ETHMII
- * @arg @ref LL_SYSCFG_PMC_ETHRMII
- * @retval None
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
-{
- return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
-}
-#endif /* SYSCFG_PMC_MII_RMII_SEL */
-
-
-
-/**
- * @brief Configure source input for the EXTI external interrupt.
- * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
- * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
- * @param Port This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE
- * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTH
- *
- * (*) value not defined in all devices
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval None
- */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
- MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
-}
-
-/**
- * @brief Get the configured defined for specific EXTI Line
- * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
- * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_LINE0
- * @arg @ref LL_SYSCFG_EXTI_LINE1
- * @arg @ref LL_SYSCFG_EXTI_LINE2
- * @arg @ref LL_SYSCFG_EXTI_LINE3
- * @arg @ref LL_SYSCFG_EXTI_LINE4
- * @arg @ref LL_SYSCFG_EXTI_LINE5
- * @arg @ref LL_SYSCFG_EXTI_LINE6
- * @arg @ref LL_SYSCFG_EXTI_LINE7
- * @arg @ref LL_SYSCFG_EXTI_LINE8
- * @arg @ref LL_SYSCFG_EXTI_LINE9
- * @arg @ref LL_SYSCFG_EXTI_LINE10
- * @arg @ref LL_SYSCFG_EXTI_LINE11
- * @arg @ref LL_SYSCFG_EXTI_LINE12
- * @arg @ref LL_SYSCFG_EXTI_LINE13
- * @arg @ref LL_SYSCFG_EXTI_LINE14
- * @arg @ref LL_SYSCFG_EXTI_LINE15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSCFG_EXTI_PORTA
- * @arg @ref LL_SYSCFG_EXTI_PORTB
- * @arg @ref LL_SYSCFG_EXTI_PORTC
- * @arg @ref LL_SYSCFG_EXTI_PORTD
- * @arg @ref LL_SYSCFG_EXTI_PORTE
- * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
- * @arg @ref LL_SYSCFG_EXTI_PORTH
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- * @{
- */
-
-/**
- * @brief Return the device identifier
- * @note For STM32F2xxxx ,the device ID is 0x411
- * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
- * @brief Return the device revision identifier
- * @note This field indicates the revision of the device.
- For example, it is read as revA -> 0x1000,revZ -> 0x1001, revB -> 0x2000, revY -> 0x2001, revX -> 0x2003, rev1 -> 0x2007, revV -> 0x200F, rev2 -> 0x201F
- * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Set Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- * @param PinAssignment This parameter can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
- * @brief Get Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
- * @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
- * @brief Freeze APB2 peripherals
- * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
- * @brief Unfreeze APB2 peripherals
- * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
- * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
- * @{
- */
-
-/**
- * @brief Set FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- * @param Latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5
- * @arg @ref LL_FLASH_LATENCY_6
- * @arg @ref LL_FLASH_LATENCY_7
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
- * @brief Get FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @arg @ref LL_FLASH_LATENCY_3
- * @arg @ref LL_FLASH_LATENCY_4
- * @arg @ref LL_FLASH_LATENCY_5
- * @arg @ref LL_FLASH_LATENCY_6
- * @arg @ref LL_FLASH_LATENCY_7
- */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
- * @brief Enable Prefetch
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
- * @brief Disable Prefetch
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
- * @brief Check if Prefetch buffer is enabled
- * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
-}
-
-/**
- * @brief Enable Instruction cache
- * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
- * @brief Disable Instruction cache
- * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
- * @brief Enable Data cache
- * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
- * @brief Disable Data cache
- * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
- * @brief Enable Instruction cache reset
- * @note bit can be written only when the instruction cache is disabled
- * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
- * @brief Disable Instruction cache reset
- * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
- * @brief Enable Data cache reset
- * @note bit can be written only when the data cache is disabled
- * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-/**
- * @brief Disable Data cache reset
- * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_tim.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_tim.h
deleted file mode 100644
index 9fc99ffa68..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_tim.h
+++ /dev/null
@@ -1,4038 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_TIM_H
-#define __STM32F2xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
-
-/** @defgroup TIM_LL TIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
- * @{
- */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
- 0x00U, /* 0: TIMx_CH1 */
- 0x00U, /* 1: TIMx_CH1N */
- 0x00U, /* 2: TIMx_CH2 */
- 0x00U, /* 3: TIMx_CH2N */
- 0x04U, /* 4: TIMx_CH3 */
- 0x04U, /* 5: TIMx_CH3N */
- 0x04U /* 6: TIMx_CH4 */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
- 0U, /* 0: OC1M, OC1FE, OC1PE */
- 0U, /* 1: - NA */
- 8U, /* 2: OC2M, OC2FE, OC2PE */
- 0U, /* 3: - NA */
- 0U, /* 4: OC3M, OC3FE, OC3PE */
- 0U, /* 5: - NA */
- 8U /* 6: OC4M, OC4FE, OC4PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
- 0U, /* 0: CC1S, IC1PSC, IC1F */
- 0U, /* 1: - NA */
- 8U, /* 2: CC2S, IC2PSC, IC2F */
- 0U, /* 3: - NA */
- 0U, /* 4: CC3S, IC3PSC, IC3F */
- 0U, /* 5: - NA */
- 8U /* 6: CC4S, IC4PSC, IC4F */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
- 0U, /* 0: CC1P */
- 2U, /* 1: CC1NP */
- 4U, /* 2: CC2P */
- 6U, /* 3: CC2NP */
- 8U, /* 4: CC3P */
- 10U, /* 5: CC3NP */
- 12U /* 6: CC4P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
- 0U, /* 0: OIS1 */
- 1U, /* 1: OIS1N */
- 2U, /* 2: OIS2 */
- 3U, /* 3: OIS2N */
- 4U, /* 4: OIS3 */
- 5U, /* 5: OIS3N */
- 6U /* 6: OIS4 */
-};
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
- * @{
- */
-
-
-/* Remap mask definitions */
-#define TIMx_OR_RMP_SHIFT 16U
-#define TIMx_OR_RMP_MASK 0x0000FFFFU
-#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
-#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
-#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
- * @{
- */
-/** @brief Convert channel id into channel index.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval none
- */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
- (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
- ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
- ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
- ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
- ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
- ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
-
-/** @brief Calculate the deadtime sampling period(in ps).
- * @param __TIMCLK__ timer input clock frequency (in Hz).
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval none
- */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- * @{
- */
-
-/**
- * @brief TIM Time Base configuration structure definition.
- */
-typedef struct
-{
- uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetPrescaler().*/
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetCounterMode().*/
-
- uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must
- be a number between 0x0000 and 0xFFFFFFFF.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetAutoReload().*/
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetClockDivision().*/
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- GP timers: this parameter must be a number between Min_Data = 0x00 and
- Max_Data = 0xFF.
- Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
- Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
- * @brief TIM Output Compare configuration structure definition.
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the output mode.
- This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetMode().*/
-
- uint32_t OCState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions
- @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions
- @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function
- LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetPolarity().*/
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetIdleState().*/
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM Input Capture configuration structure definition.
- */
-
-typedef struct
-{
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t ICActiveInput; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
- * @brief TIM Encoder interface configuration structure definition.
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetEncoderMode().*/
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
- * @brief TIM Hall sensor interface configuration structure definition.
- */
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- Prescaler must be set to get a maximum counter period longer than the
- time interval between 2 consecutive changes on the Hall inputs.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of
- @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
- A positive pulse (TRGO event) is generated with a programmable delay every time
- a change occurs on the Hall inputs.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
- * @brief BDTR (Break and Dead Time) structure definition
- */
-typedef struct
-{
- uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_LL_EC_OSSR
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been
- programmed. */
-
- uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OSSI
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been
- programmed. */
-
- uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
- register has been written, their content is frozen until the next reset.*/
-
- uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_OC_SetDeadTime()
-
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
- programmed. */
-
- uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
- This feature can be modified afterwards using unitary functions
- @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been
- programmed. */
-
- uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
- This feature can be modified afterwards using unitary function
- @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been
- programmed. */
-
- uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
- This feature can be modified afterwards using unitary functions
- @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been
- programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- * @{
- */
-#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
-#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- * @{
- */
-#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- * @{
- */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
- * @{
- */
-#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- * @{
- */
-#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- * @{
- */
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- * @{
- */
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_USART_H
-#define __STM32F2xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5)
-
-/** @defgroup USART_LL USART
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
- * @{
- */
-
-/**
- * @brief LL USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
-
- uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_LL_EC_PARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
-
- uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
- uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
- This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
- * @brief LL USART Clock Init Structure definition
- */
-typedef struct
-{
- uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
- USART HW configuration can be modified afterwards using unitary functions
- @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
- For more details, refer to description of this function. */
-
- uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
- For more details, refer to description of this function. */
-
- uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_LL_EC_PHASE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
- For more details, refer to description of this function. */
-
- uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
- For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_USART_ReadReg function
- * @{
- */
-#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */
-#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */
-#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */
-#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */
-#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */
-#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */
-#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */
-#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */
-#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */
-#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
- * @{
- */
-#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
- * @{
- */
-#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
- * @{
- */
-#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
- * @{
- */
-#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
- * @{
- */
-#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
- * @{
- */
-
-#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
- * @{
- */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
- * @{
- */
-#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
- * @{
- */
-#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
- * @{
- */
-#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
- * @{
- */
-#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
- */
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
- ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
- (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
- */
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
-/* USART BRR = mantissa + overflow + fraction
- = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
- (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
- (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
- * @{
- */
-
-/**
- * @brief USART Enable
- * @rmtoll CR1 UE LL_USART_Enable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief USART Disable (all USART prescalers and outputs are disabled)
- * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
- * and current operations are discarded. The configuration of the USART is kept, but all the status
- * flags, in the USARTx_SR are set to their default values.
- * @rmtoll CR1 UE LL_USART_Disable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief Indicate if USART is enabled
- * @rmtoll CR1 UE LL_USART_IsEnabled
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
-}
-
-/**
- * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
- * @rmtoll CR1 RE LL_USART_EnableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Receiver Disable
- * @rmtoll CR1 RE LL_USART_DisableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Transmitter Enable
- * @rmtoll CR1 TE LL_USART_EnableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Transmitter Disable
- * @rmtoll CR1 TE LL_USART_DisableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Configure simultaneously enabled/disabled states
- * of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
- * CR1 TE LL_USART_SetTransferDirection
- * @param USARTx USART Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
- * @brief Return enabled/disabled states of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
- * CR1 TE LL_USART_GetTransferDirection
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
- * @brief Configure Parity (enabled/disabled and parity mode if enabled).
- * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
- * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
- * (9th or 8th bit depending on data width) and parity is checked on the received data.
- * @rmtoll CR1 PS LL_USART_SetParity\n
- * CR1 PCE LL_USART_SetParity
- * @param USARTx USART Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
- * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
- * @rmtoll CR1 PS LL_USART_GetParity\n
- * CR1 PCE LL_USART_GetParity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
- * @brief Set Receiver Wake Up method from Mute mode.
- * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
- * @param USARTx USART Instance
- * @param Method This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
- * @brief Return Receiver Wake Up method from Mute mode
- * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
- * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M LL_USART_SetDataWidth
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
- * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M LL_USART_GetDataWidth
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
- * @brief Set Oversampling to 8-bit or 16-bit mode
- * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
- * @param USARTx USART Instance
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
- * @brief Return Oversampling mode
- * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
- * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
- * @param USARTx USART Instance
- * @param LastBitClockPulse This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
- * @brief Retrieve Clock pulse of the last data bit output configuration
- * (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
- * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_SetClockPhase
- * @param USARTx USART Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
- * @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_GetClockPhase
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
- * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
- * @param USARTx USART Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
- * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
- * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
- * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
- * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
- * CR2 CPOL LL_USART_ConfigClock\n
- * CR2 LBCL LL_USART_ConfigClock
- * @param USARTx USART Instance
- * @param Phase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @param LBCPOutput This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
- * @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
-}
-
-/**
- * @brief Set the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
- * @param USARTx USART Instance
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Retrieve the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
- * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
- * @note Call of this function is equivalent to following function call sequence :
- * - Data Width configuration using @ref LL_USART_SetDataWidth() function
- * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
- * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
- * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
- * CR1 PCE LL_USART_ConfigCharacter\n
- * CR1 M LL_USART_ConfigCharacter\n
- * CR2 STOP LL_USART_ConfigCharacter
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
- uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Set Address of the USART node.
- * @note This is used in multiprocessor communication during Mute mode or Stop mode,
- * for wake up with address mark detection.
- * @rmtoll CR2 ADD LL_USART_SetNodeAddress
- * @param USARTx USART Instance
- * @param NodeAddress 4 bit Address of the USART node.
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
-}
-
-/**
- * @brief Return 4 bit Address of the USART node as set in ADD field of CR2.
- * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
- * @rmtoll CR2 ADD LL_USART_GetNodeAddress
- * @param USARTx USART Instance
- * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
-}
-
-/**
- * @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
- * CR3 CTSE LL_USART_SetHWFlowCtrl
- * @param USARTx USART Instance
- * @param HardwareFlowControl This parameter can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
- * @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
- * CR3 CTSE LL_USART_GetHWFlowCtrl
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
- * @brief Enable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Disable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Indicate if One bit sampling method is enabled
- * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
-}
-
-/**
- * @brief Configure USART BRR register for achieving expected Baud Rate value.
- * @note Compute and set USARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
- * @note Peripheral clock and Baud rate values provided as function parameters should be valid
- * (Baud rate value != 0)
- * @rmtoll BRR BRR LL_USART_SetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
- uint32_t BaudRate)
-{
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
- }
- else
- {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
- }
-}
-
-/**
- * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
- * (full BRR content), and to used Peripheral Clock and Oversampling mode values
- * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
- * @rmtoll BRR BRR LL_USART_GetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
- uint32_t usartdiv = 0x0U;
- uint32_t brrresult = 0x0U;
-
- usartdiv = USARTx->BRR;
-
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- if ((usartdiv & 0xFFF7U) != 0U)
- {
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
- brrresult = (PeriphClk * 2U) / usartdiv;
- }
- }
- else
- {
- if ((usartdiv & 0xFFFFU) != 0U)
- {
- brrresult = PeriphClk / usartdiv;
- }
- }
- return (brrresult);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
- * @{
- */
-
-/**
- * @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_EnableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_DisableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
-}
-
-/**
- * @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
- * @param USARTx USART Instance
- * @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_IRDA_POWER_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
- * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
- * @brief Set Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
- * @param USARTx USART Instance
- * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
- * @{
- */
-
-/**
- * @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
-}
-
-/**
- * @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
-}
-
-/**
- * @brief Set Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
- * @param USARTx USART Instance
- * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
- * @param USARTx USART Instance
- * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
-}
-
-/**
- * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
- * @param USARTx USART Instance
- * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
- * @{
- */
-
-/**
- * @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
- * @{
- */
-
-/**
- * @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @param LINBDLength This parameter can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
- * @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
- * @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_EnableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_DisableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
- * @{
- */
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
- * @note In UART mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Asynchronous Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
- * CR2 CLKEN LL_USART_ConfigAsyncMode\n
- * CR3 SCEN LL_USART_ConfigAsyncMode\n
- * CR3 IREN LL_USART_ConfigAsyncMode\n
- * CR3 HDSEL LL_USART_ConfigAsyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
- /* In Asynchronous mode, the following bits must be kept cleared:
- - LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
- * @note In Synchronous mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * @note Other remaining configurations items related to Synchronous Mode
- * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
- * CR2 CLKEN LL_USART_ConfigSyncMode\n
- * CR3 SCEN LL_USART_ConfigSyncMode\n
- * CR3 IREN LL_USART_ConfigSyncMode\n
- * CR3 HDSEL LL_USART_ConfigSyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
- /* set the UART/USART in Synchronous mode */
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in LIN Mode
- * @note In LIN mode, the following bits must be kept cleared:
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
- * @note Other remaining configurations items related to LIN Mode
- * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
- * CR2 STOP LL_USART_ConfigLINMode\n
- * CR2 LINEN LL_USART_ConfigLINMode\n
- * CR3 IREN LL_USART_ConfigLINMode\n
- * CR3 SCEN LL_USART_ConfigLINMode\n
- * CR3 HDSEL LL_USART_ConfigLINMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
- /* In LIN mode, the following bits must be kept cleared:
- - STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
- /* Set the UART/USART in LIN mode */
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
- * @note In Half Duplex mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
- * @note Other remaining configurations items related to Half Duplex Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
- * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
- * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 IREN LL_USART_ConfigHalfDuplexMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
- /* In Half Duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
- /* set the UART/USART in Half Duplex mode */
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
- * @note In Smartcard mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also configures Stop bits to 1.5 bits and
- * sets the USART in Smartcard mode (SCEN bit).
- * Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
- * @note Other remaining configurations items related to Smartcard Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
- * CR2 STOP LL_USART_ConfigSmartcardMode\n
- * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
- * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
- * CR3 SCEN LL_USART_ConfigSmartcardMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
- /* In Smartcard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
- /* Configure Stop bits to 1.5 bits */
- /* Synchronous mode is activated by default */
- SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
- /* set the UART/USART in Smartcard mode */
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Irda Mode
- * @note In IRDA mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
- * @note Other remaining configurations items related to Irda Mode
- * (as Baud Rate, Word length, Power mode, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
- * CR2 CLKEN LL_USART_ConfigIrdaMode\n
- * CR2 STOP LL_USART_ConfigIrdaMode\n
- * CR3 SCEN LL_USART_ConfigIrdaMode\n
- * CR3 HDSEL LL_USART_ConfigIrdaMode\n
- * CR3 IREN LL_USART_ConfigIrdaMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
- /* set the UART/USART in IRDA mode */
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
- * (several USARTs connected in a network, one of the USARTs can be the master,
- * its TX output connected to the RX inputs of the other slaves USARTs).
- * @note In MultiProcessor mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Multi processor Mode
- * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
- * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
- * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
- * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
- * CR3 IREN LL_USART_ConfigMultiProcessMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
- /* In Multi Processor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if the USART Parity Error Flag is set or not
- * @rmtoll SR PE LL_USART_IsActiveFlag_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
-}
-
-/**
- * @brief Check if the USART Framing Error Flag is set or not
- * @rmtoll SR FE LL_USART_IsActiveFlag_FE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
-}
-
-/**
- * @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll SR NF LL_USART_IsActiveFlag_NE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
-}
-
-/**
- * @brief Check if the USART OverRun Error Flag is set or not
- * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
-}
-
-/**
- * @brief Check if the USART IDLE line detected Flag is set or not
- * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
-}
-
-/**
- * @brief Check if the USART Read Data Register Not Empty Flag is set or not
- * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Flag is set or not
- * @rmtoll SR TC LL_USART_IsActiveFlag_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
-}
-
-/**
- * @brief Check if the USART Transmit Data Register Empty Flag is set or not
- * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
-}
-
-/**
- * @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
-}
-
-/**
- * @brief Check if the USART Send Break Flag is set or not
- * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
-}
-
-/**
- * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
- * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
-}
-
-/**
- * @brief Clear Parity Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * NE, FE, ORE, IDLE would also be cleared.
- * @rmtoll SR PE LL_USART_ClearFlag_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Framing Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, ORE, IDLE would also be cleared.
- * @rmtoll SR FE LL_USART_ClearFlag_FE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Noise detected Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, FE, ORE, IDLE would also be cleared.
- * @rmtoll SR NF LL_USART_ClearFlag_NE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear OverRun Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, FE, IDLE would also be cleared.
- * @rmtoll SR ORE LL_USART_ClearFlag_ORE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear IDLE line detected Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, FE, ORE would also be cleared.
- * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Transmission Complete Flag
- * @rmtoll SR TC LL_USART_ClearFlag_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR, ~(USART_SR_TC));
-}
-
-/**
- * @brief Clear RX Not Empty Flag
- * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
-}
-
-/**
- * @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll SR LBD LL_USART_ClearFlag_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
-}
-
-/**
- * @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll SR CTS LL_USART_ClearFlag_nCTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Enable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Enable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Enable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Enable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Enable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
- * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Disable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Disable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Disable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Disable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Disable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Disable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
- * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
- * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
-}
-
-/**
- * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
- * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
-}
-
-/**
- * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
-}
-
-/**
- * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
- * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
-}
-
-/**
- * @brief Check if the USART Error Interrupt is enabled or disabled.
- * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
-}
-
-/**
- * @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
- * @{
- */
-
-/**
- * @brief Enable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Disable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for reception
- * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
-}
-
-/**
- * @brief Enable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Disable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for transmission
- * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_USART_DMA_GetRegAddr
- * @note Address of Data Register is valid for both Transmit and Receive transfers.
- * @param USARTx USART Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
-{
- /* return address of DR register */
- return ((uint32_t) & (USARTx->DR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 8 bits)
- * @rmtoll DR DR LL_USART_ReceiveData8
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
- return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 9 bits)
- * @rmtoll DR DR LL_USART_ReceiveData9
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
- */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
- return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
- * @rmtoll DR DR LL_USART_TransmitData8
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
- USARTx->DR = Value;
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
- * @rmtoll DR DR LL_USART_TransmitData9
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
- USARTx->DR = Value & 0x1FFU;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Execution Execution
- * @{
- */
-
-/**
- * @brief Request Break sending
- * @rmtoll CR1 SBK LL_USART_RequestBreakSending
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_SBK);
-}
-
-/**
- * @brief Put USART in Mute mode
- * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
- * @brief Put USART in Active mode
- * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h
deleted file mode 100644
index 9168ec2008..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_usb.h
+++ /dev/null
@@ -1,522 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_usb.h
- * @author MCD Application Team
- * @brief Header file of USB Low Layer HAL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_USB_H
-#define STM32F2xx_LL_USB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx_hal_def.h"
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @addtogroup STM32F2xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USB_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief USB Mode definition
- */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-
-typedef enum
-{
- USB_DEVICE_MODE = 0,
- USB_HOST_MODE = 1,
- USB_DRD_MODE = 2
-} USB_OTG_ModeTypeDef;
-
-/**
- * @brief URB States definition
- */
-typedef enum
-{
- URB_IDLE = 0,
- URB_DONE,
- URB_NOTREADY,
- URB_NYET,
- URB_ERROR,
- URB_STALL
-} USB_OTG_URBStateTypeDef;
-
-/**
- * @brief Host channel States definition
- */
-typedef enum
-{
- HC_IDLE = 0,
- HC_XFRC,
- HC_HALTED,
- HC_NAK,
- HC_NYET,
- HC_STALL,
- HC_XACTERR,
- HC_BBLERR,
- HC_DATATGLERR
-} USB_OTG_HCStateTypeDef;
-
-/**
- * @brief USB Instance Initialization Structure definition
- */
-typedef struct
-{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t Host_channels; /*!< Host Channels number.
- This parameter Depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
-
- uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
-
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
-
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
-
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
-
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
-
-} USB_OTG_CfgTypeDef;
-
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_LL_EP_Type */
-
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t even_odd_frame; /*!< IFrame parity
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint16_t tx_fifo_num; /*!< Transmission FIFO number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-} USB_OTG_EPTypeDef;
-
-typedef struct
-{
- uint8_t dev_addr; /*!< USB device address.
- This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
-
- uint8_t ch_num; /*!< Host channel number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_num; /*!< Endpoint number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t speed; /*!< USB Host Channel speed.
- This parameter can be any value of @ref HCD_Device_Speed:
- (HCD_DEVICE_SPEED_xxx) */
-
- uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
-
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
-
- uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_LL_EP_Type */
-
- uint16_t max_packet; /*!< Endpoint Max packet size.
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t data_pid; /*!< Initial data PID.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
-
- uint32_t XferSize; /*!< OTG Channel transfer size. */
-
- uint32_t xfer_len; /*!< Current transfer length. */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
-
- uint8_t toggle_in; /*!< IN transfer current toggle flag.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t toggle_out; /*!< OUT transfer current toggle flag
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
-
- uint32_t ErrCnt; /*!< Host channel error count. */
-
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
- This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
-} USB_OTG_HCTypeDef;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-/** @defgroup USB_OTG_CORE VERSION ID
- * @{
- */
-#define USB_OTG_CORE_ID_300A 0x4F54300AU
-#define USB_OTG_CORE_ID_310A 0x4F54310AU
-/**
- * @}
- */
-
-/** @defgroup USB_Core_Mode_ USB Core Mode
- * @{
- */
-#define USB_OTG_MODE_DEVICE 0U
-#define USB_OTG_MODE_HOST 1U
-#define USB_OTG_MODE_DRD 2U
-/**
- * @}
- */
-
-/** @defgroup USB_LL Device Speed
- * @{
- */
-#define USBD_HS_SPEED 0U
-#define USBD_HSINFS_SPEED 1U
-#define USBH_HS_SPEED 0U
-#define USBD_FS_SPEED 2U
-#define USBH_FSLS_SPEED 1U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
- * @{
- */
-#define USB_OTG_SPEED_HIGH 0U
-#define USB_OTG_SPEED_HIGH_IN_FULL 1U
-#define USB_OTG_SPEED_FULL 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
- * @{
- */
-#define USB_OTG_ULPI_PHY 1U
-#define USB_OTG_EMBEDDED_PHY 2U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
- * @{
- */
-#ifndef USBD_HS_TRDT_VALUE
-#define USBD_HS_TRDT_VALUE 9U
-#endif /* USBD_HS_TRDT_VALUE */
-#ifndef USBD_FS_TRDT_VALUE
-#define USBD_FS_TRDT_VALUE 5U
-#define USBD_DEFAULT_TRDT_VALUE 9U
-#endif /* USBD_HS_TRDT_VALUE */
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
- * @{
- */
-#define USB_OTG_HS_MAX_PACKET_SIZE 512U
-#define USB_OTG_FS_MAX_PACKET_SIZE 64U
-#define USB_OTG_MAX_EP0_SIZE 64U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
- * @{
- */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
-/**
- * @}
- */
-
-/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
- * @{
- */
-#define DCFG_FRAME_INTERVAL_80 0U
-#define DCFG_FRAME_INTERVAL_85 1U
-#define DCFG_FRAME_INTERVAL_90 2U
-#define DCFG_FRAME_INTERVAL_95 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
- * @{
- */
-#define EP_MPS_64 0U
-#define EP_MPS_32 1U
-#define EP_MPS_16 2U
-#define EP_MPS_8 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
- * @{
- */
-#define EP_SPEED_LOW 0U
-#define EP_SPEED_FULL 1U
-#define EP_SPEED_HIGH 2U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
- * @{
- */
-#define EP_TYPE_CTRL 0U
-#define EP_TYPE_ISOC 1U
-#define EP_TYPE_BULK 2U
-#define EP_TYPE_INTR 3U
-#define EP_TYPE_MSK 3U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
- * @{
- */
-#define STS_GOUT_NAK 1U
-#define STS_DATA_UPDT 2U
-#define STS_XFER_COMP 3U
-#define STS_SETUP_COMP 4U
-#define STS_SETUP_UPDT 6U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
- * @{
- */
-#define HCFG_30_60_MHZ 0U
-#define HCFG_48_MHZ 1U
-#define HCFG_6_MHZ 2U
-/**
- * @}
- */
-
-/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
- * @{
- */
-#define HPRT0_PRTSPD_HIGH_SPEED 0U
-#define HPRT0_PRTSPD_FULL_SPEED 1U
-#define HPRT0_PRTSPD_LOW_SPEED 2U
-/**
- * @}
- */
-
-#define HCCHAR_CTRL 0U
-#define HCCHAR_ISOC 1U
-#define HCCHAR_BULK 2U
-#define HCCHAR_INTR 3U
-
-#define HC_PID_DATA0 0U
-#define HC_PID_DATA2 1U
-#define HC_PID_DATA1 2U
-#define HC_PID_SETUP 3U
-
-#define GRXSTS_PKTSTS_IN 2U
-#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
-#define GRXSTS_PKTSTS_CH_HALTED 7U
-
-#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
- + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
- + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-
-#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
-
-#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
- + USB_OTG_HOST_CHANNEL_BASE\
- + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
-
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#define EP_ADDR_MSK 0xFU
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
- * @{
- */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
- * @{
- */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
- uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
- uint8_t epnum, uint8_t dev_address, uint8_t speed,
- uint8_t ep_type, uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
- USB_OTG_HCTypeDef *hc, uint8_t dma);
-
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32F2xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_utils.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_utils.h
deleted file mode 100644
index d80f094d77..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_utils.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_utils.h
- * @author MCD Application Team
- * @brief Header file of UTILS LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL UTILS driver contains a set of generic APIs that can be
- used by user:
- (+) Device electronic signature
- (+) Timing functions
- (+) PLL configuration functions
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F2xx_LL_UTILS_H
-#define __STM32F2xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-/** @defgroup UTILS_LL UTILS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
- * @{
- */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY 0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
- * @{
- */
-/**
- * @brief UTILS PLL structure definition
- */
-typedef struct
-{
- uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
- This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
- This parameter must be a number between Min_Data = 8 and Max_Data = 86
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t PLLP; /*!< Division for the main system clock.
- This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
- * @brief UTILS System, AHB and APB buses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAHBPrescaler(). */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB1Prescaler(). */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
- * @{
- */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
- * @{
- */
-#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
-#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
- * @{
- */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
- * @{
- */
-
-/**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed in
- * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source of the time base.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @note When a RTOS is used, it is recommended to avoid changing the SysTick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
-}
-
-void LL_Init1msTick(uint32_t HCLKFrequency);
-void LL_mDelay(uint32_t Delay);
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
- * @{
- */
-
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F2xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_wwdg.h b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_wwdg.h
deleted file mode 100644
index 1b5abfed64..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_ll_wwdg.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_ll_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG LL module.
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F2xx_LL_WWDG_H
-#define STM32F2xx_LL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f2xx.h"
-
-/** @addtogroup STM32F2xx_LL_Driver
- * @{
- */
-
-#if defined (WWDG)
-
-/** @defgroup WWDG_LL WWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-/** @defgroup WWDG_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
- * @{
- */
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
- * @{
- */
-#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
- * @{
- */
-/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
- * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
- * then it cannot be disabled again except by a reset.
- * This bit is set by software and only cleared by hardware after a reset.
- * When WDGA = 1, the watchdog can generate a reset.
- * @rmtoll CR WDGA LL_WWDG_Enable
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
-}
-
-/**
- * @brief Checks if Window Watchdog is enabled
- * @rmtoll CR WDGA LL_WWDG_IsEnabled
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
-{
- return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
- * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
- * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
- * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
- * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
- * @rmtoll CR T LL_WWDG_SetCounter
- * @param WWDGx WWDG Instance
- * @param Counter 0..0x7F (7 bit counter value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
-{
- MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
-}
-
-/**
- * @brief Return current Watchdog Counter Value (7 bits counter value)
- * @rmtoll CR T LL_WWDG_GetCounter
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Counter value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CR, WWDG_CR_T));
-}
-
-/**
- * @brief Set the time base of the prescaler (WDGTB).
- * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
- * is decremented every (4096 x 2expWDGTB) PCLK cycles
- * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
- * @param WWDGx WWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
-}
-
-/**
- * @brief Return current Watchdog Prescaler Value
- * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
- * @param WWDGx WWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
-}
-
-/**
- * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
- * @note This window value defines when write in the WWDG_CR register
- * to program Watchdog counter is allowed.
- * Watchdog counter value update must occur only when the counter value
- * is lower than the Watchdog window register value.
- * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
- * (in the control register) is refreshed before the downcounter has reached
- * the watchdog window register value.
- * Physically is possible to set the Window lower then 0x40 but it is not recommended.
- * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
- * @rmtoll CFR W LL_WWDG_SetWindow
- * @param WWDGx WWDG Instance
- * @param Window 0x00..0x7F (7 bit Window value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
-}
-
-/**
- * @brief Return current Watchdog Window Value (7 bits value)
- * @rmtoll CFR W LL_WWDG_GetWindow
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Window value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-/**
- * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
- * @note This bit is set by hardware when the counter has reached the value 0x40.
- * It must be cleared by software by writing 0.
- * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
- * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
-}
-
-/**
- * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
- * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_IT_Management IT_Management
- * @{
- */
-/**
- * @brief Enable the Early Wakeup Interrupt.
- * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
- * This interrupt is only cleared by hardware after a reset
- * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
-}
-
-/**
- * @brief Check if Early Wakeup Interrupt is enabled
- * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* WWDG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F2xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Release_Notes.html b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Release_Notes.html
deleted file mode 100644
index 6091df8563..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Release_Notes.html
+++ /dev/null
@@ -1,2375 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Src/Legacy/stm32f2xx_hal_can.c b/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Src/Legacy/stm32f2xx_hal_can.c
deleted file mode 100644
index 899c76f9cd..0000000000
--- a/bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Src/Legacy/stm32f2xx_hal_can.c
+++ /dev/null
@@ -1,1651 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f2xx_hal_can.c
- * @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Error functions
- *
- @verbatim
- ==============================================================================
- ##### User NOTE #####
- ==============================================================================
- [..]
- (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations.
- Another HAL CAN driver version has been designed with new API's, to fix these limitations.
-
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Connect and configure the involved CAN pins to AF9 using the
- following function HAL_GPIO_Init()
-
- (#) Initialize and configure the CAN using HAL_CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
-
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN Legacy HAL driver header file for more useful macros
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- *
-
-https://opensource.org/licenses/BSD-3-Clause
-
-
-
-
-
-
-
-
-
-Release Notes for STM32F2xx HAL Drivers
-Copyright © 2017 STMicroelectronics
-
-License
-This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at: -
-
-Update History
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects. -
Contents
--
-
- HAL/LL ADC driver
-
-
-
- Update timeout mechanism to avoid false timeout detection in case of preemption. -
- Update HAL ADC driver to add include of the LL ADC driver. -
- Update LL_ADC_DeInit() API to clear missing SQR3 register. -
- - HAL CAN driver
-
-
-
- Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error:
-
-
-
- Update CAN Initialization sequence to set “request initialization” bit before exit from sleep mode. -
-
- - Update HAL_CAN_Init() API to be aligned with reference manual and to avoid timeout error:
-
- HAL GPIO driver
-
-
-
- Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected. -
- - LL FMC driver
-
-
-
- Fix compilation warning with gcc -Wpedantic compiler option. -
- - HAL NAND driver
-
-
-
- Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories. -
- Update functions HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() to fix column address calculation issue. -
- - HAL SDMMC driver
-
-
-
- Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application. -
- SD_FindSCR() updated to resolve an issue with FIFO blocking when reading. -
- Update the definition of SDMMC_DATATIMEOUT constant in order to allow the user to redefine it in his proper application. -
- Add the block size settings in the initialization functions and remove it from read/write transactions to avoid repeated and inefficient reconfiguration. -
- Update read/write functions in DMA mode in order to force the DMA direction. -
- Deploy new functions MMC_ReadExtCSD() and SDMMC_CmdSendEXTCSD () that read and check the sectors number of the device in order to resolve the issue of wrongly reading big memory size. -
- - HAL/LL SPI driver
-
-
-
- Update to fix MISRA-C 2012 Rule-13.2. -
- Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits. -
- - HAL IRDA driver
-
-
-
- Fixed typos in the IRDA State definition description. -
- - HAL IWDG driver
-
-
-
- Updated HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue. -
- Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT). -
- - HAL/LL RTC driver
-
-
-
- New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
-
-
-
- Add HAL_RTC_DST_Add1Hour() -
- HAL_RTC_DST_Sub1Hour() -
- HAL_RTC_DST_SetStoreOperation() -
- HAL_RTC_DST_ClearStoreOperation() -
- HAL_RTC_DST_ReadStoreOperation() -
- - Update __HAL_RTC_…(__HANDLE__, …) macros to access registers through (__HANDLE__)->Instance pointer and avoid “unused variable” warnings. -
- Correct month management in IS_LL_RTC_MONTH() macro. -
- - New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
-
- HAL DMA driver
-
-
-
- Update HAL_DMA_IRQHandler() API to set the DMA state before unlocking access to the DMA handle. -
- - HAL EXTI driver
-
-
-
- Update macros using LINE as a macro parameter in order to use EXTI_LINE instead to resolve parameter conflicts with standard C usage. -
- Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers. -
- - HAL SMARTCARD driver
-
-
-
- Fixed typos in the SMARTCARD State definition description. -
- - HAL/LL TIM driver
-
-
-
- Made TIM_DMADelayPulseCplt callback as a private function. -
- Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters. -
- Update input capture measurement in DMA mode to avoid zero return values at high frequencies. -
- Updated LL_TIM_GetCounterMode() API to return the correct counter mode. -
- Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode. -
- - HAL I2C driver
-
-
-
- Update to prevent several calls of Start bit:
-
-
-
- Update I2C_MemoryTransmit_TXE_BTF() API to increment EventCount. -
- - Update to avoid I2C interrupt in endless loop:
-
-
-
- Update HAL_I2C_Master_Transmit_IT(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Transmit_DMA() and HAL_I2C_Master_Receive_DMA() APIs to unlock the I2C peripheral before generating the start. -
- - Update to use the right macro to clear I2C ADDR flag inside I2C_Slave_ADDR() API as it’s indicated in the reference manual. -
- Update HAL_I2C_EV_IRQHandler() and I2C_MasterTransmit_BTF() APIs to fix an issue where the transfer of the first few bytes to an I2C memory fails. -
- - Update to prevent several calls of Start bit:
-
- HAL RNG driver
-
-
-
- Update timeout mechanism to avoid false timeout detection in case of preemption. -
- - HAL UART driver
-
-
-
- Enhance reception for idle services (ReceptionToIdle):
-
-
-
- Add a new field (HAL_UART_RxTypeTypeDef) to the UART_HandleTypeDef structure to identify the type of ongoing reception. -
- Add UART Reception Event Callback registration. -
- - Add reception specific APIs specific to reception for Idle transfer in different modes:
-
-
-
- HAL_UARTEx_ReceiveToIdle(): Receive an amount of data in blocking mode until either the expected number of data is received or an IDLE event occurs. -
- HAL_UARTEx_ReceiveToIdle_IT(): Receive an amount of data in interrupt mode until either the expected number of data is received or an IDLE event occurs. -
- HAL_UARTEx_ReceiveToIdle_DMA(): Receive an amount of data in DMA mode until either the expected number of data is received or an IDLE event occurs. -
- - Update HAL_UART_Receive(), HAL_UART_Receive_IT() and HAL_UART_Receive_DMA() APIs to support the new enhancement of ReceptionToIdle. -
- Fix wrong comment related to RX pin configuration within the description section. -
- Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback. -
- - Enhance reception for idle services (ReceptionToIdle):
-
- LL USART driver
-
-
-
- Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro. -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects. -
Contents
--
-
- HAL/LL I2C driver
-
-
-
- Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API:
-
-
-
- Abort the right ongoing DMA transfer when memory write access request operation failed: fix typo “hdmarx” replaced by “hdmatx” -
-
- - Update to fix hardfault issue with HAL_I2C_Mem_Write_DMA() API:
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation. -
- HAL driver
-
-
-
- Enhance HAL_SetTickFreq() API robustness:
-
-
-
- HAL_SetTickFreq(): update to restore the previous tick frequency when HAL_InitTick() configuration failed. -
- - Add new defines for ARM compiler V6:
-
-
-
- __weak -
- __packed -
- __NOINLINE -
- - Update HAL_Init_Tick() API to proporely store the priority when using the non-default time base. -
- - Enhance HAL_SetTickFreq() API robustness:
-
- HAL/LL ADC driver
-
-
-
- Update the type for the following ADC parameters in ADC_InitTypeDef structure to fix MISRA-C 2012 Rule-10.4 error
-
-
-
- uint32_t ContinuousConvMode to FunctionalState ContinuousConvMode -
- uint32_t DiscontinuousConvMode to FunctionalState DiscontinuousConvMode -
- uint32_t DMAContinuousRequests to FunctionalState DMAContinuousRequests -
- - Update the following APIs to set status HAL_ADC_STATE_ERROR_INTERNAL and error code HAL_ADC_ERROR_INTERNAL when error occurs:
-
-
-
- HAL_ADC_Start() -
- HAL_ADC_Start_IT() -
- HAL_ADC_Start_DMA() -
- HAL_ADCEx_InjectedStart() -
- HAL_ADCEx_InjectedStart_IT() -
- HAL_ADCEx_MultiModeStart_DMA() -
- - Update HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error. -
- Update LL_ADC_REG_Init() API to avoid enabling continuous mode and discontinuous mode simultaneously. -
- - Update the type for the following ADC parameters in ADC_InitTypeDef structure to fix MISRA-C 2012 Rule-10.4 error
-
- HAL/LL GPIO driver
-
-
-
- Update HAL_GPIO_TogglePin() API to allow multi Pin’s toggling. -
- Update LL_GPIO_TogglePin() API to improve robustness: use BSRR register instead of ODR register. -
- - HAL/LL RCC driver
-
-
-
- Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S:
-
-
-
- HAL_RCCEx_EnablePLLI2S() -
- HAL_RCCEx_DisablePLLI2S() -
- - Add new HAL macros
-
-
-
- __HAL_RCC_GET_RTC_SOURCE()allowing to get the RTC clock source -
- __HAL_RCC_GET_RTC_HSE_PRESCALER()allowing to get the HSE clock divider for RTC peripheral. -
- - Update HAL_RCC_OscConfig() API to avoid overwriting a reserved bit
-
-
-
- Update to use MODIFY_REG instead of WRITE_REG. -
-
- - Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S:
-
- HAL/LL HASH driver
-
-
-
- Fix Misra-C 2012 Rule-5.1 warning on identifiers to be distinct in the first 31 characters in renaming all HAL_HASH_xxx_Accumulate_yy() and HAL_HASHEx_xxx_Accumulate_yy() APIs respectively into HAL_HASH_xxx_Accmlt_yy() and HAL_HASHEx_xxx_Accmlt_yy() -
- Correct phase management issue when performing two successive hash operations on two different buffers -
- Create new APIs to initialize the HASH peripheral then processes pInBuffer in interruption mode.
-
-
-
- HASH_Accumulate_IT() -
- HAL_HASH_SHA1_Accmlt_IT() -
- HAL_HASH_MD5_Accmlt_IT() -
- - Create new APIs to wrap-up multi-buffer hashing processing in polling and interrupt modes
-
-
-
- HAL_HASH_MD5_Accmlt_End() -
- HAL_HASH_SHA1_Accmlt_End() -
- HAL_HASH_MD5_Accmlt_End_IT() -
- HAL_HASH_SHA1_Accmlt_End_IT() -
- - Ensure processing suspension flag is reset to HAL_HASH_SUSPEND_NONE value in HAL_HASH_Init() API -
- Add comments to describe case of message made of several parts, not all with length multiple of 4 bytes. -
- HASH_DMAXferCplt() callback API state improperly set to READY instead of BUSY fixed. -
- - HAL NOR driver
-
-
-
- Correct MISRA-C 2012-Rule-10.4_a / 14.4_d / 18.4 warnings in HAL NOR drivers -
- Update address calculation in HAL_NOR_ProgramBuffer() -
- Add new commands operations:
-
-
-
- NOR_CMD_READ_ARRAY -
- NOR_CMD_WORD_PROGRAM
-
- - NOR_CMD_BUFFERED_PROGRAM -
- NOR_CMD_CONFIRM
-
- - NOR_CMD_BLOCK_ERASE
-
- - NOR_CMD_BLOCK_UNLOCK
-
- - NOR_CMD_READ_STATUS_REG -
- NOR_CMD_CLEAR_STATUS_REG -
- - Apply adequate commands according to the command set field value
-
-
-
- command set 1 for Micron JS28F512P33 -
- command set 2 for Micron M29W128G and Cypress S29GL128P -
- - Update some APIs in order to be compliant for memories with another command set.
-
-
-
- HAL_NOR_Init() -
- HAL_NOR_Read_ID() -
- HAL_NOR_ReturnToReadMode() -
- HAL_NOR_Read() -
- HAL_NOR_Program() -
- HAL_NOR_ReadBuffer() -
- HAL_NOR_ProgramBuffer() -
- HAL_NOR_Erase_Block() -
- HAL_NOR_Erase_Chip() -
- HAL_NOR_GetStatus() -
-
- - HAL SRAM driver
-
-
-
- General update to enhance HAL SRAM driver robustness
-
-
-
- Update HAL_SRAM_Init() API to avoid activation of burst access for SRAM -
-
- - General update to enhance HAL SRAM driver robustness
-
- LL FSMC driver
-
-
-
- Remove useless casts. -
- Update FSMC_NORSRAM_Init() API in order to resolve compilation issue with Microsoft Visual Studio 2017. -
- Update FSMC_NORSRAM_Extended_Timing_Init() API in order to manage Bus turnaround phase duration FSMC_BWTR1_BUSTURN availability. -
- - HAL/LL IWDG driver
-
-
-
- Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value -
- - HAL/LL I2C update
-
-
-
- Update I2C_MasterReceiveRXNE() static API to avoid set the STOP bit again after the bit clearing by Hardware during the masking operation
-
-
-
- Add new API I2C_WaitOnSTOPRequestThroughIT() to wait for stop bit. -
- - Update sequential APIs to avoid requesting a START when a STOP condition is not fully treated
-
-
-
- Wait the end of STOP treatment by polling (with a timeout) the STOP bit on Control register CR1 -
- - Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes
-
-
-
- Add stop condition generation when NACK occurs. -
-
- - Update I2C_MasterReceiveRXNE() static API to avoid set the STOP bit again after the bit clearing by Hardware during the masking operation
-
- HAL/LL I2S driver
-
-
-
- Update HAL_I2S_DMAStop() API to be more safe
-
-
-
- Add a check on BSY, TXE and RXNE flags before disabling the I2S -
- - Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).
-
-
-
- Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers. -
- Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX -
-
- - Update HAL_I2S_DMAStop() API to be more safe
-
- HAL/LL SPI driver
-
-
-
- Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers.
-
-
-
- Disable TX DMA request only in bidirectional receive mode -
- - Update HAL_SPI_Init() API
-
-
-
- To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode -
- Use the bit-mask for SPI configuration -
- - Update Transmit/Receive processes in half-duplex mode
-
-
-
- Disable the SPI instance before setting BDIOE bit -
- - Fix wrong timeout management
-
-
-
- Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled -
-
- - Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers.
-
- HAL/LL UART driver
-
-
-
- Update UART BRR calculation for ROM size gain -
- Update UART polling and interruption processes to fix issues related to accesses out of user specified buffer.
-
-
-
- Update UART_Transmit_IT(), UART_Receive_IT(), HAL_UART_Transmit() and HAL_UART_Receive() APIs. -
-
- - HAL SMARTCARD driver
-
-
-
- Update SMARTCARD transmission and reception APIs to handle memory corruption
-
-
-
- HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() -
-
- - Update SMARTCARD transmission and reception APIs to handle memory corruption
-
- HAL/LL TIM driver
-
-
-
- Align HAL/LL TIM driver with latest updates and enhancements -
- Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
-
-
-
- Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity. -
- Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity. -
- Update HAL_TIM_Encoder_Init() API -
- Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro. -
- - Fix bug when using multiple DMA request to different channels of same timer
-
-
-
- Introduce DMA burst state management mechanism
-
-
-
- Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef -
- Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState -
- Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation -
- Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure -
- Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel) -
- Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel) -
-
- - Introduce DMA burst state management mechanism
-
- Implement TIM channel state management mechanism
-
-
-
- Add new macro
-
-
-
- TIM_CHANNEL_STATE_SET_ALL and TIM_CHANNEL_N_STATE_SET_ALL -
- TIM_CHANNEL_STATE_SET and TIM_CHANNEL_N_STATE_SET -
- TIM_CHANNEL_STATE_GET and TIM_CHANNEL_N_STATE_GET -
-
- - Add new macro
-
- Add new API HAL_TIM_GetActiveChannel() -
- Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel -
- Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef -
- Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState and ChannelNState -
- Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation state -
- Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state -
- Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger.
-
-
-
- Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro. -
- Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit. -
- - Remove ‘register’ storage class specifier from LL TIM driver. -
- Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral -
- Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory -
- - HAL/LL USB driver
-
-
-
- Bug fix: USB_ReadPMA() and USB_WritePMA() by ensuring 16-bits access to USB PMA memory -
- Bug fix: correct USB RX count calculation -
- Fix USB Bulk transfer double buffer mode -
- Remove register keyword from USB defined macros as no more supported by C++ compiler -
- Minor rework on USBD_Start() and USBD_Stop() APIs: stopping device will be handled by HAL_PCD_DeInit() API. -
- Remove non used API for USB device mode. -
- - LL UTILS driver
-
-
-
- UTILS_SetFlashLatency() API renamed to LL_SetFlashLatency() and set exportable. -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- HAL/LL GPIO update
-
-
-
- Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s -
- - HAL I2C update
-
-
-
- Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue
-
-
-
- Add additional check on hi2c->hdmatx, hdmatx->XferCpltCallback, hi2c->hdmarx, hdmarx->XferCpltCallback in I2C_Master_SB() API to avoid enabling DMA request when IT mode is used. -
- - Update HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with I2C memory IT processes
-
-
-
- Add stop condition generation when NACK occurs. -
- - Update HAL_I2C_Init() API to force software reset before setting new I2C configuration. -
- Update HAL I2C processes to report ErrorCode when wrong I2C start condition occurs
-
-
-
- Add new ErrorCode define: HAL_I2C_WRONG_START -
- Set ErrorCode parameter in I2C handle to HAL_I2C_WRONG_START -
- - Update I2C_DMAXferCplt(), I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
-
-
-
- Add additional check on hi2c->hdmtx and hi2c->hdmarx before resetting DMA Tx/Rx complete callbacks. -
-
- - Update HAL_I2C_EV_IRQHandler() API to fix I2C send break issue
-
- HAL IRDA update
-
-
-
- Update IRDA interruption handler to manage correctly the overrun interrupt
-
-
-
- Add in the HAL_IRDA_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs. -
-
- - Update IRDA interruption handler to manage correctly the overrun interrupt
-
- HAL SMARTCARD update
-
-
-
- Update SMARTCARD interruption handler to manage correctly the overrun interrupt.
-
-
-
- Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs. -
-
- - Update SMARTCARD interruption handler to manage correctly the overrun interrupt.
-
- HAL UART update
-
-
-
- Update UART polling processes to handle efficiently the Lock mechanism
-
-
-
- Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API. -
- - Update UART interruption handler to manage correctly the overrun interrupt
-
-
-
- Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs. -
-
- - Update UART polling processes to handle efficiently the Lock mechanism
-
- HAL USART update
-
-
-
- Update USART interruption handler to manage correctly the overrun interrupt
-
-
-
- Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs. -
-
- - Update USART interruption handler to manage correctly the overrun interrupt
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’ -
- General updates to fix CodeSonar compilation warnings -
- General updates to fix the user manual .chm files -
- Add support of HAL callback registration feature -
- Add new HAL EXTI driver -
- The following changes done on the HAL drivers require an update on the application code based on older HAL versions
-
-
-
- HAL/LL Generic update
-
-
-
- Add support of HAL callback registration feature
-
-
-
- The feature disabled by default is available for the following HAL drivers:
-
-
-
- ADC, CAN, CRYP, DAC, DCMI, ETH, HASH, HCD, I2C, UART, USART, IRDA, SMARTCARD, -
- MMC, NAND, NOR, PCCARD, PCD, RNG, RTC, SD, SRAM, SPI, I2S, TIM and WWDG -
- - The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32f2xx_hal_conf.h project configuration file (template file stm32f2xx_hal_conf_template.h available from Drivers/STM32F2xx_HAL_Driver/Inc) -
- Once enabled , the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback() -
- - The feature disabled by default is available for the following HAL drivers:
-
- - Add support of HAL callback registration feature
-
- Rework of HAL CRYP driver (compatibility break)
-
-
-
- HAL CRYP driver has been redesigned with new API’s, to bypass limitations on data Encryption/Decryption management present with previous HAL CRYP driver version. -
- The new HAL CRYP driver is the recommended version. It is located as usual in Drivers/STM32F2xx_HAL_Driver/Src and Drivers/STM32f2xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CRYP_MODULE_ENABLED in stm32f2xx_hal_conf.h -
- The legacy HAL CRYP driver is no longer supported. -
- - Rework of HAL CAN driver (compatibility break)
-
-
-
- A new HAL CAN driver has been redesigned with new APIs, to bypass limitations on CAN Tx/Rx FIFO management present with previous HAL CAN driver version. -
- The new HAL CAN driver is the recommended version. It is located as usual in Drivers/STM32F2xx_HAL_Driver/Src and Drivers/STM32f2xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CAN_MODULE_ENABLED in stm32f2xx_hal_conf.h -
- The legacy HAL CAN driver is also present in the release in Drivers/STM32F2xx_HAL_Driver/Src/Legacy and Drivers/STM32F2xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. Its usage is not recommended as deprecated. It can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in stm32f2xx_hal_conf.h -
-
- - HAL/LL Generic update
-
- HAL/LL Generic update
-
-
-
- Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
-
-
-
- Add the following API’s :
-
-
-
- HAL_GetTickPrio(): Returns a tick priority. -
- HAL_SetTickFreq(): Sets new tick frequency. -
- HAL_GetTickFreq(): Returns tick frequency. -
- - Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default). -
- - Add the following API’s :
-
- Add UNUSED() macro implementation to avoid GCC warning
-
-
-
- The warning is detected when the UNUSED() macro is called from C++ file -
- - General updates to fix MISRA 2012 compilation errors
-
-
-
- HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() macros implementation update -
- “stdio.h” include updated with “stddef.h” -
- - Add HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2() API in order to returns the unique device identifier -
- - Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
-
- HAL CAN update
-
-
-
- Fields of CAN_InitTypeDef structure are reworked:
-
-
-
- SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority -
- - Rename CAN_FilterConfTypeDef structure to CAN_FilterTypeDef and update some fields:
-
-
-
- FilterNumber to FilterBank -
- BankNumber to SlaveStartFilterBank -
- - Rename CanTxMsgTypeDef structure to CAN_TxHeaderTypeDef and update some fields:
-
-
-
- Data to TransmitGlobalTime -
- - Rename CanRxMsgTypeDef structure to CAN_RxHeaderTypeDef and update some fields:
-
-
-
- Data to Timestamp -
- FMI to FilterMatchIndex -
- - Update possible values list for FilterActivation parameter in CAN_FilterTypeDef structure
-
-
-
- CAN_FILTER_ENABLE instead of ENABLE -
- CAN_FILTER_DISABLE instead of DISABLE -
- - HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API’s -
- HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion. -
- HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request. -
- HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() -
- to get Rx message. -
- HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage() -
- in the receive callback to get Rx message -
- HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep() -
- HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback(). -
- HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback(). -
- More complete “How to use the new driver” is detailed in the driver header section itself. -
- Refer to the following example to identify the changes -
- - Fields of CAN_InitTypeDef structure are reworked:
-
- HAL CRC update
-
-
-
- Update __HAL_CRC_DR_RESET() macro -
- Update HAL_CRC_DeInit() API to
-
-
-
- Be able to return HAL status when CRC is is already busy -
- DeInit the low level hardware after reset IDR register content -
- - Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings API’s:
-
-
-
- HAL_CRC_Accumulate() -
- HAL_CRC_Calculate() -
-
- - HAL CRYP update
-
-
-
- The CRYP_InitTypeDef is no more supported, changed by CRYP_ConfigTypedef to allow changing parameters -
- Using HAL_CRYP_setConfig() API without reinitialize the CRYP IP using the HAL_CRYP_Init() API -
- New parameters added in the CRYP_ConfigTypeDef structure: B0 and DataWidthUnit -
- Input data size and error code parameters are added in the CRYP_HandleTypeDef structure -
- Add new APIs to manage the CRYP configuration:
-
-
-
- HAL_CRYP_SetConfig() -
- HAL_CRYP_GetConfig() -
- - Add new APIs to encrypt and decrypt data:
-
-
-
- HAL_CRYP_Encypt() -
- HAL_CRYP_Decypt() -
- HAL_CRYP_Encypt_IT() -
- HAL_CRYP_Decypt_IT() -
- HAL_CRYP_Encypt_DMA() -
- HAL_CRYP_Decypt_DMA() -
- - More complete “How to use the new driver” is detailed in the driver header section itself. -
- Refer to the following example to identify the changes -
- - HAL DAC update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Update HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA() and HAL_DAC_ConfigChannel() API to
-
-
-
- Update lock mechanism for DAC process -
- Optimize code by using direct register read -
- - Update HAL_DAC_IRQHandler() function to
-
-
-
- Add error management in case DMA errors through HAL_DAC_DMAUnderrunCallbackCh1() and HAL_DACEx_DMAUnderrunCallbackCh2() -
- Optimize code by using direct register read -
-
- - Update HAL_DAC_Start(), HAL_DAC_Start_DMA(), HAL_DAC_Stop_DMA() and HAL_DAC_ConfigChannel() API to
-
- - Overall rework of the driver for a more efficient implementation
-
- HAL DCMI update
-
-
-
- Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral -
- Add new timeout implementation based on cpu cycles for DCMI stop -
- Update lock mechanism for DCMI process -
- Update HAL_DCMI_IRQHandler() function to:
-
-
-
- Optimize code by using direct register read -
- - The extension files stm32f2xx_hal_dcmi_ex.c/.h is added and kept empty for projects compatibility reason -
- Add DCMI_SyncUnmaskTypeDef structure and HAL_DCMI_ConfigSyncUnmask() API to manage embedded synchronization delimiters unmasks -
- HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback() -
- - HAL DMA update
-
-
-
- Add clean of callbacks in HAL_DMA_DeInit() API -
- Remove FIFO error enabling in “HAL_DMA_Start_IT”
-
-
-
- when FIFO error monitoring is requested in IT model, the macro __HAL_DMA_ENABLE_IT can be used to enable the FIFO error IT at the user Msp functio -
-
- - HAL FLASH update
-
-
-
- HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked -
- - HAL GPIO update
-
-
-
- HAL_GPIO_TogglePin() API implementation update: to improve robustness -
- HAL_GPIO_DeInit() API update to ensure clear all GPIO EXTI pending interrupts. -
- - HAL HASH update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- HASH API changes for MISRA-C 2012 compliance -
- Update HASH_Start_DMA() to add check on HASH_CR_MDMAT bit before checking input buffer length in case of multi-buffer processing -
- Fill-up empty statement in HAL_HASH_DMAFeed_ProcessSuspend() to correct CodeSonar warning -
-
- - Overall rework of the driver for a more efficient implementation
-
- HAL I2C update
-
-
-
- I2C API changes for MISRA-C 2012 compliance:
-
-
-
- Rename HAL_I2C_Master_Sequential_Transmit_IT() to HAL_I2C_Master_Seq_Transmit_IT() -
- Rename HAL_I2C_Master_Sequentiel_Receive_IT() to HAL_I2C_Master_Seq_Receive_IT() -
- Rename HAL_I2C_Slave_Sequentiel_Transmit_IT() to HAL_I2C_Slave_Seq_Transmit_IT() -
- Rename HAL_I2C_Slave_Sequentiel_Receive_DMA() to HAL_I2C_Slave_Seq_Receive_DMA() -
- - Add support of I2C repeated start feature in DMA Mode With the following new API’s
-
-
-
- HAL_I2C_Master_Seq_Transmit_DMA() -
- HAL_I2C_Master_Seq_Receive_DMA() -
- HAL_I2C_Slave_Seq_Transmit_DMA() -
- HAL_I2C_Slave_Seq_Receive_DMA() -
- - Add new I2C transfer options to easy manage the sequential transfers
-
-
-
- I2C_OTHER_FRAME -
- I2C_OTHER_AND_LAST_FRAME -
- - Fix I2C send break issue in IT processes
-
-
-
- Add additional check on hi2c->hdmatxand hi2c->hdmarx to avoid the DMA request enable when ITmode is used. -
-
- - I2C API changes for MISRA-C 2012 compliance:
-
- HAL UART/USART/IrDA/SMARTCARD update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Improve I/O operation functions: separate transfer process and PPP state management -
- Update the HAL_PPP_IRQHandler function by optimizing the management of interrupt errors -
- Align driver with the Reference Manual regarding registers and bit definition naming -
-
- - Overall rework of the driver for a more efficient implementation
-
- LL IWDG update
-
-
-
- Update LL inline macros to use IWDGx parameter instead of IWDG instance defined in CMSIS device -
- - HAL RNG update
-
-
-
- Add ErrorCode parameter in HAL RNG Handler structure -
- Add HAL_RNG_GetError() API -
- HAL Lock/Unlock mechanism update -
- - HAL/LL RTC update
-
-
-
- HAL/ LL drivers optimization
-
-
-
- HAL driver: remove unused variables -
- LL driver: getter APIs optimization -
-
- - HAL/ LL drivers optimization
-
- HAL/LL RCC update
-
-
-
- Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
-
-
-
- Be able to return HAL/LL status -
- Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers -
- Clear all interrupt flags -
- Initialize systick interrupt period -
-
- - Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
-
- HAL SDMMC update
-
-
-
- Add API HAL_SD_ConfigSpeedBusOperation() to configure the SD card speed bus mode -
- Fix and improve state and error management -
- Fix preprocessing compilation issue with SDIO STA STBITERR interrupt -
- Align driver with the Reference Manual regarding registers and bit definition naming -
- - HAL SPI update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Add the following new macros:
-
-
-
- SPI_CHECK_FLAG() -
- SPI_CHECK_IT_SOURCE() -
- - Update HAL_SPI_StateTypeDef structure to add new state: HAL_SPI_STATE_ABORT -
- Add HAL_SPI_Abort() to manage abort issue in SPI TX or Rx mode only -
- Update HAL_SPI_Transmit()/HAL_SPI_Receive() API’s to fix memory overflow issue. -
- Update HAL_SPI_Transmit_DMA : checking hmdtx instead of hdmrx. -
- Update HAL_SPI_IRQHandler() function to
-
-
-
- Add error management in case DMA errors through HAL_DMA_Abort_IT() and ErrorCallback() -
- Optimize code by using direct register read -
- - Align driver with the Reference Manual regarding registers and bit definition naming -
- - Add the following new macros:
-
- - Overall rework of the driver for a more efficient implementation
-
- HAL I2S update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Add the following new macros:
-
-
-
- I2S_CHECK_FLAG() -
- I2S_CHECK_IT_SOURCE() -
- - Update HAL_I2S_Transmit()/HAL_I2S_Receive() API’s to fix memory overflow issue -
- Update HAL_SPI_IRQHandler() function to
-
-
-
- Add error management in case DMA errors through HAL_DMA_Abort_IT() and ErrorCallback() -
- Optimize code by using direct register read -
- - Add extra call to HAL_LOCK/HAL_UNLOCK to the followings API’s:
-
-
-
- HAL_I2S_Transmit() -
- HAL_I2S_Receive() -
- HAL_I2S_Transmit_IT() -
- HAL_I2S_Receive_IT() -
- HAL_I2S_Transmit_DMA() -
- HAL_I2S_Receive_DMA() -
- - Align driver with the Reference Manual regarding registers and bit definition naming -
- - Add the following new macros:
-
- - Overall rework of the driver for a more efficient implementation
-
- HAL/LL TIM update
-
-
-
- Move the following TIM structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h
-
-
-
- TIM_MasterConfigTypeDef() -
- TIM_BreakDeadTimeConfigTypeDef() -
- - Add new TIM Callbacks API’s:
-
-
-
- HAL_TIM_PeriodElapsedHalfCpltCallback() -
- HAL_TIM_IC_CaptureHalfCpltCallback() -
- HAL_TIM_PWM_PulseFinishedHalfCpltCallback() -
- HAL_TIM_TriggerHalfCpltCallback() -
- - TIM API changes for MISRA-C 2012 compliance:
-
-
-
- Rename HAL_TIM_SlaveConfigSynchronization to HAL_TIM_SlaveConfigSynchro -
- Rename HAL_TIM_SlaveConfigSynchronization_IT to HAL_TIM_SlaveConfigSynchro_IT -
- Rename HAL_TIMEx_ConfigCommutationEvent to HAL_TIMEx_ConfigCommutEvent -
- Rename HAL_TIMEx_ConfigCommutationEvent_IT to HAL_TIMEx_ConfigCommutEvent_IT -
- Rename HAL_TIMEx_ConfigCommutationEvent_DMA to HAL_TIMEx_ConfigCommutEvent_DMA -
- Rename HAL_TIMEx_CommutationCallback to HAL_TIMEx_CommutCallback -
- Rename HAL_TIMEx_DMACommutationCplt to TIMEx_DMACommutationCplt -
- - Add a call to HAL_DMA_Abort_IT from HAL_TIM_XXX_Stop_DMA -
- - Move the following TIM structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h
-
- HAL/LL USB update
-
-
-
- Rework USB interrupt handler and improve HS DMA support in Device mode -
- Fix BCD handling for OTG instance in device mode -
- cleanup reference to low speed in device mode -
- Allow writing TX FIFO in case of transfer length is equal to available space in the TX FIFO -
- Fix Toggle OUT interrupt channel in host mode -
- Add new callback to be used to handle usb device connection/disconnection
-
-
-
- HAL_HCD_PortEnabled_Callback() -
- HAL_HCD_PortDisabled_Callback() -
- - Update to prevent reactivate host interrupt channel -
- Updated USB_WritePacket(), USB_ReadPacket()APIs to prevent compilation warning with GCC GNU v8.2.0 -
- Rework USB_EPStartXfer() API to enable theUSB endpoint before unmasking the TX FiFo empty interrupt in case DMA is not used -
- USB HAL_HCD_Init() and HAL_PCD_Init() APIsupdated to avoid enabling USB DMA feature for OTG FS instance, USB DMAfeature is available only on OTG HS Instance -
- Remove duplicated line in hal_hcd.c header file comment section -
- Rework USB HAL driver to use instancePCD_SPEED_xxx, HCD_SPEED_xx speeds instead of OTG register Core speed definition during the instance initialization -
- Software Quality improvement with a fix ofCodeSonar warning on PCD_Port_IRQHandler() and HCD_Port_IRQHandler()interrupt handlers -
- - HAL UTILS update
-
-
-
- Update LL_GetFlashSize() API to return uint32_t instead of uint16_t -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- Fix compilation warning with GCC compiler -
- Remove Date and version from header files -
- HAL Generic update
-
-
-
- Update __weak and __packed defined values for ARM compiler -
- Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler -
- - HAL I2C update
-
-
-
- Update Interface APIs headers to remove confusing message about device address -
- UpdateI2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to fix badHandling of NACK in I2C master receive process. -
- - HAL RCC update
-
-
-
- Update HAL_RCC_GetOscConfig()API to:
-
-
-
- set PLLR in theRCC_OscInitStruct -
- check on null pointer -
- Update HAL_RCC_ClockConfig()API to: -
- check on null pointer -
- optimize code size byupdating the handling method of the SWS bits -
- update to use __HAL_FLASH_GET_LATENCY() flash macro instead of using direct registeraccess to LATENCY bits in FLASH ACR register. -
- - Update HAL_RCC_DeInit() to
-
-
-
- Be able to return HAL status (HAL_OK, HAL_TIMEOUT and HAL_ERROR) -
- Add checks for HSI, PLL and PLLI2S ready before modifying RCC CFGR registers -
- Clear all interrupt flags -
- Initialize systick interrupt period -
- - Update HAL_RCC_GetSysClockFreq() to avoid risk of rounding error which may leads to a wrong returned value. -
- - Update HAL_RCC_GetOscConfig()API to:
-
- HAL RNG update
-
-
-
- HAL_RNG_Init() remove Lock()/Unlock() -
- - HAL MMC update
-
-
-
- HAL_MMC_Erase() API: add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled. -
- - LL DMA update
-
-
-
- Update to clear DMA flags using WRITE_REG() instead SET_REG() API to avoid read access to the IFCR register that is write only. -
- Update values for the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 -
- - LL RTC update
-
-
-
- Fix warning with static analyzer -
- - LL USART update
-
-
-
- Add assert macros to check USART BaudRate register -
- - LL I2C update
-
-
-
- Rename IS_I2C_CLOCK_SPEED()and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() andIS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition. -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- HAL CONF Template update
-
-
-
- Add support for HAL MMC driver. -
- - HAL CAN update
-
-
-
- Addmanagement of overrun error. -
- Allowpossibility to receive messages from the 2 RX FIFOs in parallel viainterrupt. -
- Fix messagelost issue with specific sequence of transmit requests. -
- Handletransmission failure with error callback, when NART is enabled. -
- Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission whentimeout is reached -
-
-
-
-
-
-Main Changes
--
-
- Add Low Layer drivers allowing performance and footprint optimization
-
-
-
- Low Layer drivers APIs provide register level programming: require deep knowledge of peripherals described in STM32F2xx Reference Manuals -
- Low Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR, RCC, RNG, RTC, SPI, TIM, USART, WWDG peripherals and additional Low Level Bus, System and Utilities APIs. -
- Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f2xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f2xx_ll_ppp.h file must be included in user code. -
- - General updates to fix known defects and enhancements implementation -
- Fix extra warnings with GCC compiler -
- HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’ -
- Add new HAL MMC driver -
- The following changes done on the HAL drivers require an update on the application code based on older HAL versions
-
-
-
- HAL SD update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Modify initialization API and structures -
- Modify Read / Write sequences: separate transfer process and SD Cards state management -
- Adding interrupt mode for Read / Write operations -
- Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors -
- - Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application -
- - Overall rework of the driver for a more efficient implementation
-
- HAL NAND update -
- Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields -
- Add new HAL_NAND_ConfigDevice API -
- - HAL SD update
-
- HAL update
-
-
-
- Modify default HAL_Delay implementation to guarantee minimum delay -
- Add HAL_GetUID API : returns the unique device identifier -
- - HAL Cortex update
-
-
-
- Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f2xx_hal_cortex.h to stm32f2xx_hal_cortex.c -
- Clear the whole MPU control register in HAL_MPU_Disable() API -
- - HAL FLASH update
-
-
-
- IS_FLASH_ADDRESS() macro update to support OTP range -
- FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations -
- - HAL GPIO update
-
-
-
- Update IS_GPIO_PIN() macro implementation to be more safe -
- - HAL RCC update
-
-
-
- Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4 -
- Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f2xx.c file instead of APBAHBPrescTable[] table. -
- - HAL DMA update
-
-
-
- HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst -
- - HAL UART/USART/IrDA/SMARTCARD (referenced as PPP here below)
-
-
-
- DMA Receive process; the code has been updated to clear the PPP OVR flag before enabling DMA receive request. -
- Add transfer abort APIs and associated callbacks :
-
-
-
- HAL_PPP_Abort() -
- HAL_PPP_AbortTransmit() -
- HAL_PPP_AbortReceive() -
- HAL_PPP_Abort_IT() -
- HAL_PPP_AbortTransmit_IT() -
- HAL_PPP_AbortReceive_IT() -
- HAL_PPP_AbortCpltCallback() -
- HAL_PPP_AbortTransmitCpltCallback() -
- HAL_PPP_AbortReceiveCpltCallback() -
-
- - HAL CAN update
-
-
-
- Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes -
- HAL CAN driver optimization -
- - HAL TIM update
-
-
-
- Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. -
- Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption. -
- - HAL I2C update
-
-
-
- Update HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending extra bytes at the end of the transmit processes -
- UpdateHAL_I2C_Mem_Read() API to fix wrong check on misused parameter “Size” -
- UpdateI2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs toenhance Master sequential reception process. -
- - HAL SPI update
-
-
-
- Add transfer abort APIs and associated callbacks in interrupt mode
-
-
-
- HAL_SPI_Abort() -
- HAL_SPI_Abort_IT() -
- HAL_SPI_AbortCpltCallback() -
-
- - Add transfer abort APIs and associated callbacks in interrupt mode
-
- HAL USB PCD update
-
-
-
- Flush all TX FIFOs on USB Reset -
- Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API’s -
- - LL USB update
-
-
-
- Enable DMA Burst mode for USB OTG HS -
- Fix SD card detection issue -
- - LL SDMMC update
-
-
-
- Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- Enhance HAL delay and time base implementation:
-
-
-
- Add new drivers stm32f2xx_hal_timebase_tim_template.c, stm32f2xx_hal_timebase_rtc_alarm_template.c and stm32f2xx_hal_timebase_rtc_wakeup_template.c which override the native HAL time base functions (defined as weak) to either use the TIM or the RTC as time base tick source. For more details about the usage of these drivers, please refer to HAL_TimeBase examples and FreeRTOS-based applications -
- - The following changes done on the HAL drivers require an update on the application code based on HAL V1.1.2
-
-
-
- HAL UART, USART, IRDA, SMARTCARD, SPI, I2C (referenced as PPP here below) drivers
-
-
-
- Add PPP error management during DMA process. This requires the following updates on user application:
-
-
-
- Configure and enable the PPP IRQ in HAL_PPP_MspInit() function -
- In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function -
- Add and customize the Error Callback API: HAL_PPP_ErrorCallback() -
- - HAL I2C driver:◾Update to avoid waiting on STOPF/BTF/AF flag under DMA ISR by using the PPP end of transfer interrupt in theDMA transfer process. This requires the following updates on user application:
-
-
-
- Configure and enable the PPP IRQ in HAL_PPP_MspInit() function -
- In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function -
- - I2C transfer processes IT update: NACK during addressing phase is managed through I2C Error interrupt instead of HAL state -
- - Add PPP error management during DMA process. This requires the following updates on user application:
-
- HAL IWDG driver: rework overall driver for better implementation
-
-
-
- Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs -
- - HAL WWDG driver: rework overall driver for better implementation
-
-
-
- Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs -
- Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the “counter” parameter -
-
- - HAL UART, USART, IRDA, SMARTCARD, SPI, I2C (referenced as PPP here below) drivers
-
- HAL Generic update
-
-
-
- stm32f2xx_hal_conf_template.h
-
-
-
- Optimize HSE Startup Timeout value from 5000ms to 100 ms -
- Add new define LSE_STARTUP_TIMEOUT -
- Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled. -
- - Update HAL drivers to support MISRA C 2004 rule 10.6 -
- Add new template driver to configure timebase using TIMER :
-
-
-
- stm32f2xx_hal_timebase_tim_template.c -
-
- - stm32f2xx_hal_conf_template.h
-
- HAL CAN update
-
-
-
- Update HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to unlock process when all Mailboxes are busy -
- - HAL DCMI update
-
-
-
- Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt -
- Update HAL_DCMI_Start_DMA() function to Enable the DCMI peripheral -
- Add new timeout implementation based on cpu cycles for DCMI stop -
- Add HAL_DCMI_Suspend() function to suspend DCMI capture -
- Add HAL_DCMI_Resume() function to resume capture after DCMI suspend -
- Update lock mechanism for DCMI process -
- Update HAL_DCMI_IRQHandler() function to
-
-
-
- Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT() -
- Optimize code by using direct register read -
-
- - HAL DMA update
-
-
-
- Add new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to register/unregister the different callbacks identified by the enum typedef HAL_DMA_CallbackIDTypeDef -
- Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context
-
-
-
- The new registered Abort callback is called when DMA transfer abortion is completed -
- - Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API -
- Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED -
- Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef -
- - HAL ETH update
-
-
-
- Removal of ETH MAC debug register defines -
- - HAL HCD update
-
-
-
- Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disable -
- - HAL I2C update
-
-
-
- Add support of I2C repeated start feature:
-
-
-
- With the following new API’s
-
-
-
- HAL_I2C_Master_Sequential_Transmit_IT() -
- HAL_I2C_Master_Sequential_Receive_IT() -
- HAL_I2C_Master_Abort_IT() -
- HAL_I2C_Slave_Sequential_Transmit_IT() -
- HAL_I2C_Slave_Sequential_Receive_IT() -
- HAL_I2C_EnableListen_IT() -
- HAL_I2C_DisableListen_IT() -
- - Add new user callbacks:
-
-
-
- HAL_I2C_ListenCpltCallback() -
- HAL_I2C_AddrCallback() -
-
- - With the following new API’s
-
- Update to generate STOP condition when a acknowledge failure error is detected -
- Several update on HAL I2C driver to implement the new I2C state machine:
-
-
-
- Add new API to get the I2C mode: HAL_I2C_GetMode() -
- Update I2C process to manage the new I2C states. -
- - Fix wrong behaviour in single byte transmission -
- Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature. -
- Update I2C transmission process to support the case data size equal 0 -
- Update Polling management:
-
-
-
- The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative -
- - Add the management of Abort service: Abort DMA transfer through interrupt
-
-
-
- In the case of Master Abort IT transfer usage:
-
-
-
- Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process -
- A new abort state is defined in the HAL_I2C_StateTypeDef structure -
-
- - In the case of Master Abort IT transfer usage:
-
- Add the management of I2C peripheral errors, ACK failure and STOP condition detection during DMA process. This requires the following updates on user application:
-
-
-
- Configure and enable the I2C IRQ in HAL_I2C_MspInit() function -
- In stm32f2xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function -
- Add and customize the Error Callback API: HAL_I2C_ErrorCallback() -
- - NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API’s -
- I2C addressing phase is updated to be managed using interrupt instead of polling (Only for HAL I2C driver)
-
-
-
- Add new static functions to manage I2C SB, ADDR and ADD10 flags -
-
- - Add support of I2C repeated start feature:
-
- HAL IRDA update
-
-
-
- Several update on HAL IRDA driver to implement the new UART state machine:
-
-
-
- Add new field in IRDA_HandleTypeDef structure: “rxState”, IRDA state information related to Rx Operations -
- Rename “state” field in UART_HandleTypeDef structure by “gstate”: IRDA state information related to global Handle management and Tx Operations -
- Update IRDA process to manage the new UART states. -
- Update __HAL_IRDA_RESET_HANDLE_STATE() macro to handle the new IRDA state parameters (gState, rxState) -
- - Removal of IRDA_TIMEOUT_VALUE define -
- Update IRDA_BRR() Macro to fix wrong baudrate calculation -
- Update Polling management:
-
-
-
- The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative -
- - Update DMA process:
-
-
-
- Update the management of IRDA peripheral errors during DMA process. This requires the following updates in user application:
-
-
-
- Configure and enable the IRDA IRQ in HAL_IRDA_MspInit() function -
- In stm32f2xx_it.c file, IRDA_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function -
- Add and customize the Error Callback API: HAL_IRDA_ErrorCallback() -
-
- - Update the management of IRDA peripheral errors during DMA process. This requires the following updates in user application:
-
- - Several update on HAL IRDA driver to implement the new UART state machine:
-
- HAL IWDG update
-
-
-
- Overall rework of the driver for a more efficient implementation
-
-
-
- Remove the following APIs:
-
-
-
- HAL_IWDG_Start() -
- HAL_IWDG_MspInit() -
- HAL_IWDG_GetState() -
- - Update implementation:
-
-
-
- HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter -
- HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter -
- - Refer to the following example to identify the changes: IWDG_Example -
- - Remove the following APIs:
-
- - Overall rework of the driver for a more efficient implementation
-
- HAL NOR update
-
-
-
- Update NOR_ADDR_SHIFT macro implementation -
- - HAL PCD update
-
-
-
- Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value -
- - HAL RCC update
-
-
-
- Add new default define value for HSI calibration “RCC_HSICALIBRATION_DEFAULT” -
- Optimize Internal oscillators and PLL startup timeout -
- Update to avoid the disable for HSE/LSE oscillators before setting the new RCC HSE/LSE configuration and add the following notes in HAL_RCC_OscConfig() API description:
-
-
-
-
-
- @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not -
--
-
- supported by this API. User should request a transition to LSE Off -
--
-
- first and then LSE On or LSE Bypass. -
--
-
- @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not -
--
-
- supported by this API. User should request a transition to HSE Off -
--
-
- first and then HSE On or HSE Bypass.◦Optimize the HAL_RCC_ClockConfig() API implementation -
-
- - Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock -
- HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue -
- - HAL RTC update
-
-
-
- Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags -
- - HAL SMARTCARD update
-
-
-
- Several update on HAL SMARTCARD driver to implement the new UART state machine:
-
-
-
- Add new field in SMARTCARD_HandleTypeDef structure: “rxState”, SMARTCARDstate information related to Rx Operations -
- Rename “state” field in UART_HandleTypeDef structure by “gstate”: SMARTCARDstate information related to global Handle management and Tx Operations -
- Update SMARTCARD process to manage the new UART states. -
- Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro to handle the new SMARTCARD state parameters (gState, rxState) -
- - Update SMARTCARD_BRR() macro to fix wrong baudrate calculation -
- Update Polling management:
-
-
-
- The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative -
- - Update DMA process:
-
-
-
- Update the management of SMARTCARD peripheral errors during DMA process. This requires the following updates in user application:
-
-
-
- Configure and enable the SMARTCARD IRQ in HAL_SMARTCARD_MspInit() function -
- In stm32f2xx_it.c file, SMARTCARD_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function -
- Add and customize the Error Callback API: HAL_SMARTCARD_ErrorCallback() -
-
- - Update the management of SMARTCARD peripheral errors during DMA process. This requires the following updates in user application:
-
- - Several update on HAL SMARTCARD driver to implement the new UART state machine:
-
- HAL SPI update
-
-
-
- Major Update to improve performance in polling/interrupt mode to reach max frequency:
-
-
-
- Polling mode:
-
-
-
- Replace use of SPI_WaitOnFlagUnitTimeout() funnction by “if” statement to check on RXNE/TXE flags while transferring data -
- Use API data pointer instead of SPI handle data pointer -
- Use a Goto implementation instead of “if..else” statements -
-
- - Polling mode:
-
- Interrupt mode:
-
-
-
- Minimize access on SPI registers -
- Split the SPI modes into dedicated static functions to minimize checking statements under HAL_IRQHandler(): -
- 1lines/2lines modes -
- 8 bit/ 16 bits data formats -
- CRC calculation enabled/disabled -
- Remove waiting loop under ISR when closing the communication -
- - All modes
-
-
-
- Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled
-
-
-
- Update Timeout management to check on global process -
- Update Error code management in all processes -
- Update DMA process:◾Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application: -
- Configure and enable the SPI IRQ in HAL_SPI_MspInit() function -
- In stm32f2xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function -
- Add and customize the Error Callback API: HAL_SPI_ErrorCallback() -
- Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA -
-
- - Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled
-
- - Major Update to improve performance in polling/interrupt mode to reach max frequency:
-
- HAL UART update
-
-
-
- Several update on HAL UART driver to implement the new UART state machine:
-
-
-
- Add new field in UART_HandleTypeDef structure: “rxState”, UART state information related to Rx Operations -
- Rename “state” field in UART_HandleTypeDef structure by “gstate”: UART state information related to global Handle management and Tx Operations -
- Update UART process to manage the new UART states. -
- Update __HAL_UART_RESET_HANDLE_STATE() macro to handle the new UART state parameters (gState, rxState) -
- - Update UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate calculation. -
- Update Polling management:
-
-
-
- The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative -
- - Update DMA process:
-
-
-
- Update the management of UART peripheral errors during DMA process. This requires the following updates in user application:
-
-
-
- Configure and enable the UART IRQ in HAL_UART_MspInit() function -
- In stm32f2xx_it.c file, UART_IRQHandler() function: add a call to HAL_UART_IRQHandler() function -
- Add and customize the Error Callback API: HAL_UART_ErrorCallback() -
-
- - Update the management of UART peripheral errors during DMA process. This requires the following updates in user application:
-
- - Several update on HAL UART driver to implement the new UART state machine:
-
- HAL USART update
-
-
-
- Update Polling management:
-
-
-
- The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative -
- - Update DMA process:
-
-
-
- Update the management of USART peripheral errors during DMA process. This requires the following updates in user application:
-
-
-
- Configure and enable the USART IRQ in HAL_USART_MspInit() function -
- In stm32f2xx_it.c file, USART_IRQHandler() function: add a call to HAL_USART_IRQHandler() function -
- Add and customize the Error Callback API: HAL_USART_ErrorCallback() -
-
- - Update the management of USART peripheral errors during DMA process. This requires the following updates in user application:
-
- - Update Polling management:
-
- HAL WWDG update
-
-
-
- Overall rework of the driver for more efficient implementation
-
-
-
- Remove the following APIs:
-
-
-
- HAL_WWDG_Start() -
- HAL_WWDG_Start_IT() -
- HAL_WWDG_MspDeInit() -
- HAL_WWDG_GetState() -
- - Update implementation:
-
-
-
- HAL_WWDG_Init() -
- A new parameter in the Init structure: EWIMode
-
-
-
- HAL_WWDG_MspInit() -
- - HAL_WWDG_Refresh()
-
-
-
- This function insures the reload of the counter -
- The “counter” parameter has been removed -
- - HAL_WWDG_IRQHandler() -
- HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback() -
-
- - Remove the following APIs:
-
- Refer to the following example to identify the changes: WWDG_Example -
- - Overall rework of the driver for more efficient implementation
-
-
-
-
-
-Main Changes
--
-
- HAL RCC update
-
-
-
- Fix compilation errors with the __HAL_RCC_DAC_IS_CLK_DISABLED(), __HAL_RCC_CRYP_IS_CLK_DISABLED() and __HAL_RCC_HASH_IS_CLK_DISABLED() macros -
- - HAL ETH update
-
-
-
- Update HAL_ETH_Init() function to add timeout on the Software reset management -
-
-
-
-
-
-Main Changes
--
-
- General updates to fix known defects and enhancements implementation -
- One change done on the HAL CRYP requires an update on the application code based on HAL V1.1.0
-
-
-
- Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters -
- - HAL generic update
-
-
-
- Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line:
-
-
-
- UNUSED(hppp); -
- - HSE_STARTUP_TIMEOUT constant has been corrected in stm32f2xx_hal_conf_template.h file, its value changed from 5000 to 100. -
- - Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line:
-
- HAL CORTEX update
-
-
-
- Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro -
- - HAL HASH update
-
-
-
- Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef -
- Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef -
- - HAL RCC update
-
-
-
- Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status -
- Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG -
- - HAL FLASH update
-
-
-
- __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it. -
- - HAL CRYP update
-
-
-
- Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue -
- - HAL TIM update
-
-
-
- Update HAL_TIM_ConfigClockSource() API to check only the required parameters -
- - HAL NAND update
-
-
-
- Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access -
- - HAL CAN update
-
-
-
- Update to use “=” instead of “|=” to clear flags in the MSR, TSR, RF0R and RF1R registers -
- - HAL PCD update
-
-
-
- Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation -
- - LL FSMC update
-
-
-
- Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters -
-
-
-
-
-
-Main Changes
--
-
- Maintenance release to fix known defects and enhancements implementation -
- Macros and literals renaming to ensure compatibles across STM32 series, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy -
- Add *.chm UM for all drivers -
- Update drivers to be C++ compliant -
- Several update on source code formatting, for better UM generation (i.e. Doxygen tags updated) -
- Four changes done on the HAL requires an update on the application code based on HAL V1.0.1
-
-
-
- LSI_VALUE constant has been corrected in stm32f2xx_hal_conf.h file, its value changed from 40 KHz to 32 KHz -
- UART, USART, IRDA and SMARTCARD (referenced as PPP here below) drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, PPP TC interrupt is used instead. Below the update to be done on user application:
-
-
-
- Configure and enable the USART IRQ in HAL_PPP_MspInit() function -
- In stm32f2xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function -
- - CRYP driver updated to support multi instance,so user must ensure that the new parameter Instance is initialized in his application(CRYPHandle.Instance = CRYP) -
- HASH IT process: update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits -
- - HAL generic update
-
-
-
- stm32f2xx_hal_def.h
-
-
-
- Remove NULL definition and add include for stdio.h -
- Add UNUSED() macro -
- Add a new define __NOINLINE to be used for the no inline code independent from tool chain -
- - stm32f2xx_hal_conf_template.h
-
-
-
- Add a new define for LSI default value LSI_VALUE -
- Add a new define for LSE default value LSE_VALUE -
- Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced time base implementation) -
- - Enhance HAL delay and time base implementation
-
-
-
- Systick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source) -
- Functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file, for more details please refer to HAL_TimeBase example -
- - Fix flag clear procedure: use atomic write operation “=” instead of ready-modify-write operation “|=” or “&=” -
- Fix on Timeout management, Timeout value set to 0 passed to API automatically exits the function after checking the flag without any wait -
- Common update for the following communication peripherals: SPI, UART, USART and IRDA
-
-
-
- Add DMA circular mode support -
- Remove lock from recursive process -
- - Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state -
- Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation -
- When USE_RTOS == 1 (in stm32f2xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty -
- Miscellaneous comments and formatting update -
- Update all macros and literals naming to be upper case -
- ErrorCode parameter in PPP_HandleTypeDef structure updated to uint32_t instead of enum HAL_PPP_ErrorTypeDef -
- Remove the unused FLAG and IT assert macros -
- stm32f2xx_hal_ppp.c
-
-
-
- HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit() -
- - Important Note: aliases has been added for any API naming change, to keep compatibility with previous version -
- - stm32f2xx_hal_def.h
-
- HAL ADC update
-
-
-
- ADC HAL state machine update to use bit fields instead of enum:
-
-
-
- HAL_ADC_StateTypeDef enum fields are replaced by respective defines -
- - Add new literal: ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode. -
- IS_ADC_CHANNEL() macro update to don’t assert stop the ADC_CHANNEL_TEMPSENSOR value -
- HAL_ADC_PollForConversion(): update to manage particular case when ADC configured in DMA mode and ADC sequencer with several ranks and polling for end of each conversion -
- HAL_ADC_Start()/HAL_ADC_Start_IT() /HAL_ADC_Start_DMA() update:
-
-
-
- unlock the process before starting the ADC software conversion. -
- Optimize the ADC stabilization delays -
- - __HAL_ADC_GET_IT_SOURCE() update macro implementation -
- Add more details in ‘How to use this driver’ section -
- Add new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode. -
- - ADC HAL state machine update to use bit fields instead of enum:
-
- HAL DAC update
-
-
-
- Enhance the DMA channelconfiguration when used with DAC -
- HAL_DAC_ConfigChannel(): update the access to the DAC peripheral registers via the hdac handle instance -
- HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2 -
- HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration -
- HAL_DACEx_TriangleWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration -
- Add new macro to check if the specified DAC interrupt source is enabled or disabled
-
-
-
- __HAL_DAC_GET_IT_SOURCE() -
- - HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition -
- HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition -
- - HAL CAN update
-
-
-
- Unlock the CAN process when communication error occurred -
- CanTxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8] -
- CanRxMsgTypeDef structure: update to use uint8_t Data[8] instead of uint32_t Data[8] -
- - HAL CORTEX update
-
-
-
- Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter -
- Add specific API for MPU management
-
-
-
- add MPU_Region_InitTypeDef structure -
- add new function HAL_MPU_ConfigRegion() -
-
- - HAL CRYP update
-
-
-
- HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue -
- Add restriction for the CCM Encrypt/Decrypt API’s that only DataType equal to 8bits is supported -
- Update to manage multi instance:
-
-
-
- Add new parameter Instance in the CRYP_HandleTypeDef Handle structure. -
- Add new parameter in all HAL CRYP macros
-
-
-
- example: __HAL_CRYP_ENABLE() updated by __HAL_CRYP_ENABLE(HANDLE) -
-
-
- - HAL DCMI update
-
-
-
- HAL_DCMI_ConfigCROP(): Invert assert macros to check Y0 and Ysize parameters -
- - HAL DMA update
-
-
-
- Overall driver update for code optimization -
- add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure -
- add DMA_Base_Registers private structure -
- add static function DMA_CalcBaseAndBitshift()
-
-
-
- update HAL_DMA_Init() function to use the new added static function -
- update HAL_DMA_DeInit() function to optimize clear flag operations -
- update HAL_DMA_Start_IT() function to optimize interrupts enable -
- update HAL_DMA_PollForTransfer() function to optimize check on flags -
- update HAL_DMA_IRQHandler() function to optimize interrupt flag management -
- - Fix in HAL_DMA_PollForTransfer() to:
-
-
-
- set DMA error code in case of HAL_ERROR status -
- set HAL Unlock before DMA state update -
- - HAL_DMA_Init(): Update to clear the DBM bit in the SxCR register before setting the new configuration -
- DMA_SetConfig(): add to clear the DBM bit in the SxCR register -
- - HAL FLASH update
-
-
-
- update HAL_FLASH_Program_IT() function by removing the pending flag clear -
- update HAL_FLASH_IRQHandler() function to improve erase operation procedure -
- update FLASH_WaitForLastOperation() function by checking on end of operation flag -
- Add “HAL_” prefix in the defined values for the FLASH error code -
- Example: FLASH_ERROR_PGP renamed by HAL_FLASH_ERROR_PGP -
- Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function -
- Update FLASH_SetErrorCode() function to use “|=” operant to update the Flash ErrorCode parameter in the FLASH handle -
- IS_FLASH_ADDRESS(): Update the macro check using ‘<=’ condition instead of ‘<’ -
- IS_OPTIONBYTE(): Update the macro check using ‘<=’ condition instead of ‘<’ -
- Add “FLASH_” prefix in the defined values of FLASH Type Program parameter -
- Example: TYPEPROGRAM_BYTE renamed by FLASH_TYPEPROGRAM_BYTE -
- Add “FLASH_” prefix in the defined values of FLASH Type Erase parameter -
- Example: TYPEERASE_SECTORS renamed by FLASH_TYPEERASE_SECTORS -
- Add “FLASH_” prefix in the defined values of FLASH Voltage Range parameter -
- Example: VOLTAGE_RANGE_1 renamed by FLASH_VOLTAGE_RANGE_1 -
- Add “OB_” prefix in the defined values of FLASH WRP State parameter -
- Example: WRPSTATE_ENABLE renamed by OB_WRPSTATE_ENABLE -
- __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset ICRST bit in the ACR register after setting it. -
- __HAL_FLASH_DATA_CACHE_RESET() macro: update to reset DCRST bit in the ACR register after setting it. -
- FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus -
- __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency -
- - HAL ETH update
-
-
-
- Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete -
- Use HAL_Delay() instead of counting loop -
- __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only -
- Add the following macros used toWake up the device from STOP mode by Ethernet event :
-
-
-
- __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() -
- __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() -
- __HAL_ETH_WAKEUP_EXTI_GET_FLAG() -
- __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() -
- __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EGDE_TRIGGER() -
- __HAL_ETH_WAKE_EXTI_ENABLE_FALLING_EGDE_TRIGGER() -
- __HAL_ETH_WAKE_EXTI_ENABLE_FALLINGRISING_TRIGGER() -
- - Rename literals
-
-
-
- ETH_PROMISCIOUSMODE_ENABLE by ETH_PROMISCUOUS_MODE_ENABLE -
- ETH_PROMISCIOUSMODE_DISABLE by ETH_PROMISCUOUS_MODE_DISABLE -
- - Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro -
- Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS) -
- - HAL PWR update
-
-
-
- HAL_PWR_ConfigPVD(): add clear of the EXTI trigger before new configuration -
- Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function -
- HAL_PWR_EnterSLEEPMode()
-
-
-
- Remove disable and enable of SysTick Timer -
- Update to clear SLEEPDEEP bit of Cortex System Control Register (SCB->SCR) before entering in sleep mode -
- Update usage of __WFE() in low power entry function: if there is a pending event, calling __WFE() will not enter the CortexM3 core to sleep mode. The solution is to made the call below; the first __WFE() is always ignored and clears the event if one was already pending, the second is always applied
-
-
-
- __SEV() -
- __WFE() -
- __WFE() -
-
- - Add new macro for software event generation __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -
- Remove the following defines form Generic driver and add them under extension driver because they are only used within extension functions. -
- CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function -
- CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function -
- Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register
-
-
-
- HAL_PWR_DisableSleepOnExit() -
- HAL_PWR_EnableSleepOnExit() -
- HAL_PWR_EnableSEVOnPend() -
- HAL_PWR_DisableSEVOnPend() -
- - HAL_PWR_EnterSLEEPMode()
-
-
-
- Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode -
- - Add new PVD configuration modes
-
-
-
- PWR_PVD_MODE_NORMAL -
- PWR_PVD_MODE_EVENT_RISING -
- PWR_PVD_MODE_EVENT_FALLING -
- PWR_PVD_MODE_EVENT_RISING_FALLING -
- - Add new macros to manage PVD Trigger
-
-
-
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() -
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE( -
- __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() -
- __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() -
- __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() -
- __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() -
- - PVD macros:
-
-
-
- Remove the EXTILINE parameter -
- Update to use prefix "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD" -
- - Rename HAL_PWR_PVDConfig() function by HAL_PWR_ConfigPVD() -
- - HAL GPIO update
-
-
-
- Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW -
- Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM -
- Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH -
- Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH -
- Add a new macro __HAL_GPIO_EXTI_GENERATE_SWIT() to manage the generation of software interrupton selected EXTI line -
- HAL_GPIO_Init(): use temporary variable when modifying the registers, to avoid unexpected transition in the GPIO pin configuration -
- Remove IS_GET_GPIO_PIN macro -
- Add a new function HAL_GPIO_LockPin() -
- Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x
-
-
-
- __HAL_GPIO_EXTI_CLEAR_IT() -
- __HAL_GPIO_EXTI_GET_IT() -
- __HAL_GPIO_EXTI_CLEAR_FLAG() -
- __HAL_GPIO_EXTI_GET_FLAG() -
- - HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the CMSIS assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE() -
- Rename __HAL_GET_GPIO_SOURCE() by GPIO_GET_INDEX() and move this later to file stm32f2xx_hal_gpio_ex.h -
- HAL_GPIO_DeInit(): Update to check if GPIO Pin x is already used in EXTI mode on another GPIO Port before De-Initialize the EXTI registers -
- - HAL HASH update
-
-
-
- HAL_HASH_MD5_Start_IT(): fix input address management issue -
- HAL_HASH_MODE_Start_IT() (MODE stands for MD5 and SHA1) updates:
-
-
-
- Fix processing fail for small input buffers -
- Update to unlock the process and call return HAL_OK at the end of HASH processing to avoid incorrectly repeating software -
- Update to properly manage the HashITCounter -
- Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits -
- - __HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected -
- HAL_HASH_SHA1_Accumulate() updates:
-
-
-
- Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. -
- Add the following note in API description
-
-
-
-
-
- @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted. -
-
-
-
- - HAL RCC update
-
-
-
- HAL_RCCEx_PeriphCLKConfig() updates:
-
-
-
- Update the LSE check condition after backup domain reset: update to check LSE ready flag when LSE oscillator is already enabled instead of check on LSE oscillator only when LSE is used as RTC clock source -
- - In HAL_RCC_ClockConfig()function: update the AHB clock divider before clock switch to new source -
- Allow to calibrate the HSI when it is used as system clock source -
- Reorganize the RCC macros to make them more clear -
- Rename the following Macros
-
-
-
- __PPP_CLK_ENABLE() by __HAL_RCC_PPP_CLK_ENABLE() -
- __PPP_CLK_DISABLE() by __HAL_RCC_PPP_CLK_DISABLE() -
- __PPP_FORCE_RESET() by __HAL_RCC_PPP_FORCE_RESET() -
- __PPP_RELEASE_RESET() by __HAL_RCC_PPP_RELEASE_RESET() -
- __PPP_CLK_SLEEP_ENABLE() by __HAL_RCC_PPP_CLK_SLEEP_ENABLE() -
- __PPP_CLK_SLEEP_DISABLE() by __HAL_RCC_PPP_CLK_SLEEP_DISABLE() -
- - Add description of RCC known Limitations -
- HAL_RCC_OscConfig() fix issues:
-
-
-
- Remove the disable of HSE oscillator when HSE_BYPASS is used as system clock source or as PPL clock source -
- Add a check on HSERDY flag when HSE_BYPASS is selected as new state for HSE oscillator. -
- - Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config() -
- __HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable delay -
- HAL_RCC_OscConfig() fix issues:
-
-
-
- Add a check on LSERDY flag when LSE_BYPASS is selected as new state for LSE oscillator. -
- - __HAL_RCC_HSE_CONFIG() macro: add the comment below:
-
-
-
-
-
- @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. -
--
-
- User should request a transition to HSE Off first and then HSE On or HSE Bypass. -
-
- - __HAL_RCC_LSE_CONFIG() macro: add the comment below:
-
-
-
-
-
- @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. -
--
-
- User should request a transition to LSE Off first and then LSE On or LSE Bypass. -
-
- - Add the following new macros for PLL source and PLLM selection :
-
-
-
- __HAL_RCC_PLL_PLLSOURCE_CONFIG() -
- __HAL_RCC_PLL_PLLM_CONFIG() -
- - Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK) -
- __HAL_RCC_GET_SYSCLK_SOURCE() updates: -
- Add new RCC Literals:
-
-
-
- RCC_SYSCLKSOURCE_STATUS_HSI -
- RCC_SYSCLKSOURCE_STATUS_HSE -
- RCC_SYSCLKSOURCE_STATUS_PLLCLK -
- - Update macro description to refer to the literals above -
- - HAL_RCCEx_PeriphCLKConfig() updates:
-
- HAL I2S update
-
-
-
- HAL_I2S_Init(): add check on I2S instance using CMSIS macro IS_I2S_ALL_INSTANCE() -
- HAL_I2S_IRQHandler() update for compliance with C++ -
- Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliance with C++ -
- HAL_I2S_GetError(): update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration -
- HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode -
- - HAL I2C update
-
-
-
- I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR. -
- Update busy flag Timeout value -
- I2C Master Receive Processes update to disable ACK before generate the STOP -
- Update to clear the POS bit in the CR1 register at the begging of all the HAL I2C processes -
- Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for compliance with C++ -
- - HAL IrDA update
-
-
-
- Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_IRDA_CLEAR_PEFLAG()
-
-
-
- __HAL_ IRDA _CLEAR_FEFLAG() -
- __HAL_ IRDA _CLEAR_NEFLAG() -
- __HAL_ IRDA _CLEAR_OREFLAG() -
- __HAL_ IRDA _CLEAR_IDLEFLAG() -
- - Add several enhancements without affecting the driver functionalities
-
-
-
- Remove the check on RXNE set after reading the Data in the DR register -
- Update HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC -
- - Add the following APIs used within DMA process ◾HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-
-
-
- HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); -
- HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-
- - void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -
- void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -
- - DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, IrDA TC interrupt is used instead. Below the update to be done on user application:
-
-
-
- Configure and enable the USART IRQ in HAL_IRDA_MspInit() function -
- In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function -
- - IT transmit process; the code has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application -
- Rename Macros: add prefix "__HAL"
-
-
-
- __IRDA_ENABLE() by __HAL_IRDA_ENABLE() -
- __IRDA_DISABLE() by __HAL_IRDA_DISABLE() -
- - Add new user macros to manage the sample method feature
-
-
-
- __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE() -
- __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE() -
- - HAL_IRDA_Transmit_IT(): update to remove the enable of the parity error interrupt -
- Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for compliance with C++ -
- HAL_IRDA_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual
-
-
-
- Add clear the TC flag in the SR register before enabling the DMA transmit request -
-
- - Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_IRDA_CLEAR_PEFLAG()
-
- HAL SPI update
-
-
-
- SPI interface is used in synchronous polling mode: at high clock rates like SPI prescaler 2 and 4, calling -
- AL_SPI_TransmitReceive() returns with error HAL_TIMEOUT -
- HAL_SPI_TransmitReceive_DMA() does not clean up the TX DMA, so any subsequent SPI calls return the DMA error -
- HAL_SPI_Transmit_DMA() is failing when data size is equal to 1 byte -
- Add the following APIs used within the DMA process
-
-
-
- HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); -
- HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); -
- HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); -
- void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); -
- void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); -
- void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); -
- - HAL_SPI_TransmitReceive_DMA() update to remove the DMA Tx Error Callback initialization when SPI RxOnly mode is selected -
- Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix “Unused variable” warning with TrueSTUDIO. -
- Rename Literals: remove “D” from “DISABLED” and “ENABLED”
-
-
-
- SPI_TIMODE_DISABLED by SPI_TIMODE_DISABLE -
- SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE -
- SPI_CRCCALCULATION_DISABLED by SPI_CRCCALCULATION_DISABLE -
- SPI_CRCCALCULATION_ENABLED by SPI_CRCCALCULATION_ENABLE -
- - Add use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliance with C++ -
- HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TransmitReceive_DMA() update to unlock the process before enabling the SPI peripheral -
- HAL_SPI_Transmit_DMA() update to manage correctly the DMA TX stream in SPI Full duplex mode -
- Section SPI_Exported_Functions_Group2 update to remove duplication in *.chm UM -
- Fix the wrong definition of HAL_SPI_ERROR_FLAG literal -
- - HAL CRC update
-
-
-
- These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR() -
- - __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG() -
- HAL LL SDMMC update
-
-
-
- Use of CMSIS constants instead of magic values -
- Miscellaneous update in functions internal coding -
- IS_SDIO_ALL_INSTANCE() macro moved to CMSIS files -
- - HAL NAND update
-
-
-
- Fix issue of macros returning wrong address for NAND blocks -
- Fix issue for read/write NAND page/spare area -
- Rename NAND Address structure to NAND_AddressTypeDef instead of NAND_AddressTypedef -
- Update the used algorithm of these functions
-
-
-
- HAL_NAND_Read_Page() -
- HAL_NAND_Write_Page() -
- HAL_NAND_Read_SpareArea() -
- HAL_NAND_Write_SpareArea() -
- - HAL_NAND_Write_Page(): move initialization of tickstart before while loop -
- HAL_NAND_Erase_Block(): add whait until NAND status is ready before exiting this function -
- - HAL NOR update
-
-
-
- Add the NOR addressbank macro used within the API -
- Update NOR APIimplementation to avoid the use of NOR address bank hard coded -
- NOR Status literals renamed
-
-
-
- NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS -
- NOR_ONGOING by HAL_NOR_STATUS_ONGOING -
- NOR_ERROR by HAL_NOR_STATUS_ERROR -
- NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT -
- - HAL_NOR_GetStatus() update to fix Timeout issue and exit from waiting loop when timeout occurred -
- - HAL PCCARD update -
- Rename PCCARD Address structure to HAL_PCCARD_StatusTypeDef instead of CF_StatusTypedef -
- PCCARD Status literals renamed
-
-
-
- CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS -
- CF_ONGOING by HAL_PCCARD_STATUS_ONGOING -
- CF_ERROR by HAL_PCCARD_STATUS_ERROR -
- CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT -
- - Update “CF” by “PCCARD” in functions, literals and macros -
- HAL HCD update
-
-
-
- HCD_StateTypeDef structure members renamed -
- These macro are renamed
-
-
-
- __HAL_GET_FLAG(HANDLE, INTERRUPT) by __HAL_HCD_GET_FLAG(HANDLE, INTERRUPT) -
- __HAL_IS_INVALID_INTERRUPT(HANDLE) by __HAL_HCD_IS_INVALID_INTERRUPT(HANDLE) -
- - Update to use local variable in USB Host channel re-activation -
- - HAL PCD update
-
-
-
- HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f2xx_hal_pcd_ex.h/.c -
- PCD_StateTypeDef structure members renamed -
- Fix incorrect masking of TxFIFOEmpty -
- stm32f2xx_ll_usb.c: fix issue in HS mode -
- New macros added
-
-
-
- __HAL_PCD_IS_PHY_SUSPENDED() -
- __HAL_USB_HS_EXTI_GENERATE_SWIT() -
- __HAL_USB_FS_EXTI_GENERATE_SWIT() -
- - These macro are renamed
-
-
-
- __HAL_GET_FLAG(HANDLE, INTERRUPT) by __HAL_PCD_GET_FLAG(HANDLE, INTERRUPT) -
- __HAL_CLEAR_FLAG(HANDLE, INTERRUPT) by __HAL_PCD_CLEAR_FLAG(HANDLE, INTERRUPT)
-
- - __HAL_IS_INVALID_INTERRUPT(HANDLE) by __HAL_PCD_IS_INVALID_INTERRUPT(HANDLE)
-
- - __HAL_PCD_UNGATE_CLOCK(HANDLE) by __HAL_PCD_UNGATE_PHYCLOCK(HANDLE) -
- __HAL_PCD_GATE_CLOCK(HANDLE) by __HAL_PCD_GATE_PHYCLOCK(HANDLE) -
- - Rename functions
-
-
-
- HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup() -
- HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup() -
- - Rename literals
-
-
-
- USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -
- USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -
- USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -
- USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -
- USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -
- USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -
- USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_WAKEUP_EXTI_LINE -
- USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_WAKEUP_EXTI_LINE -
- - Rename USB EXTI macros (FS, HS referenced as SUBBLOCK here below)
-
-
-
- __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()
-
- - __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT() -
- __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() -
- __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG() -
- __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE() -
- __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE() -
- __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() -
- __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT() -
- - __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()
- HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time -
- - HAL RNG update
-
-
-
- Add new functions
-
-
-
- HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number, return random value in argument and return HAL status. -
- HAL_RNG_GenerateRandomNumber_IT(): to start generation of the 32-bits random number, user should call the HAL_RNG_ReadLastRandomNumber() function under the HAL_RNG_ReadyCallback() to get the generated random value. -
- HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle -
- - HAL_RNG_GetRandomNumber(): return value update (obsolete), replaced by HAL_RNG_GenerateRandomNumber() -
- HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT() -
- __HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro -
- Add new define for RNG ready interrupt: RNG_IT_DRDY -
- - Add new functions
-
- HAL RTC update
-
-
-
- Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag -
- HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below -
-
-
- @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values -
--
-
- in the higher-order calendar shadow registers to ensure consistency between the time and date values. -
--
-
- Reading RTC current time locks the values in calendar shadow registers until Current date is read. -
-- Rename literals: add prefix "__HAL"
-
-
-
- FORMAT_BIN by RTC_FORMAT_BIN -
- FORMAT_BCD by RTC_FORMAT_BCD -
- - Rename macros (ALARM, WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here below)
-
-
-
- __HAL_RTC_EXTI_ENABLE_IT() by __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT() -
- __HAL_RTC_EXTI_DISABLE_IT() by __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT() -
- __HAL_RTC_EXTI_CLEAR_FLAG() by __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG() -
- __HAL_RTC_EXTI_GENERATE_SWIT() by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT() -
- - Add new macros (ALARM, WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here below)
-
-
-
- __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() -
- __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT() -
- __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT() -
- __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE() -
- __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG() -
- - Update to use CMSIS mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..) -
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue -
- __HAL_RTC_ALARM_GET_IT(), __HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), __HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() macros implementation changed: remove unused cast -
- IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value -
- Update to define hardware independent literals names:
-
-
-
- Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT -
- Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1 -
- Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1 -
- Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT -
- Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1 -
- Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1 -
-
- - HAL SD update
-
-
-
- Rename SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS -
- SD_PowerON() updated to add 1ms required power up waiting time before starting the SD initialization sequence -
- SD_DMA_RxCplt()/SD_DMA_TxCplt(): add a call to HAL_DMA_Abort() -
- HAL_SD_ReadBlocks() update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter -
- HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() update to call the HAL_DMA_Start_IT() function withDMA Datalength set to BlockSize/4 as the DMA is configured in word -
- - HAL SMARTCARD update
-
-
-
- Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_SMARTCARD_CLEAR_PEFLAG()
-
-
-
- __HAL_SMARTCARD_CLEAR_FEFLAG() -
- __HAL_SMARTCARD_CLEAR_NEFLAG() -
- __HAL_SMARTCARD_CLEAR_OREFLAG() -
- __HAL_SMARTCARD_CLEAR_IDLEFLAG() -
- - Add several enhancements without affecting the driver functionalities
-
-
-
- Add a new state HAL_SMARTCARD_STATE_BUSY_TX_RX and all processes has been updated accordingly -
- Update HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC -
- - DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, SMARTCARD TC interrupt is used instead. Below the update to be done on user application:
-
-
-
- Configure and enable the USART IRQ in HAL_SAMRTCARD_MspInit() function -
- In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function -
- - IT transmit process; the code has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application -
- Rename macros: add prefix "__HAL"
-
-
-
- __SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE() -
- __SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE() -
- __SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT() -
- __SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT() -
- __SMARTCARD_DMA_REQUEST_ENABLE() by __HAL_SMARTCARD_DMA_REQUEST_ENABLE() -
- __SMARTCARD_DMA_REQUEST_DISABLE() by __HAL_SMARTCARD_DMA_REQUEST_DISABLE() -
- - Rename literals: remove “D” from “DISABLED” and “ENABLED”
-
-
-
- SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE -
- SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE -
- - Add new user macros to manage the sample method feature
-
-
-
- __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE() -
- __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE() -
- - Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for compliance with C++ -
- HAL_SMARTCARD_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual
-
-
-
- Add clear the TC flag in the SR register before enabling the DMA transmit request -
- HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt -
- HAL_SMARTCARD_IRQHandler() update check condition for transmission end -
- Clean up: remove the following literals that aren’t used in smartcard mode
-
-
-
- SMARTCARD_PARITY_NONE -
- SMARTCARD_WORDLENGTH_8B -
- SMARTCARD_STOPBITS_1 -
- SMARTCADR_STOPBITS_2 -
-
-
- - Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_SMARTCARD_CLEAR_PEFLAG()
-
- HAL TIM update
-
-
-
- HAL_TIM_IRQHandler(): update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1 -
- __HAL_TIM_SET_PRESCALER() updated to use ‘=’ instead of ‘|=’ -
- Add thefollowing macro in TIM HAL driver -
- __HAL_TIM_GET_COMPARE() -
- __HAL_TIM_GET_COUNTER() -
- __HAL_TIM_GET_AUTORELOAD() -
- __HAL_TIM_GET_CLOCKDIVISION() -
- __HAL_TIM_GET_ICPRESCALER() -
- Add TIM_CHANNEL_ALL as possible value for all Encoder Start/Stop APIs Description -
- HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro -
- HAL_TIM_PWM_ConfigChannel() add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter -
- TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call HAL_TIM_PWM_PulseFinishedCallback() -
- TIM_DMACaptureCplt() update to set the TIM Channel before to call HAL_TIM_IC_CaptureCallback() -
- HAL_TIM_IC_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter -
- HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specific TIM channel -
- Add new function for TIM Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT() -
- HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values -
- HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes -
- Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register:
-
-
-
- __HAL_TIM_URS_ENABLE() -
- __HAL_TIM_URS_DISABLE() -
- - Add new macro for TIM Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY() -
- - HAL UART update
-
-
-
- Add new macros to control CTS and RTS -
- Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_UART_CLEAR_PEFLAG()
-
-
-
- __HAL_UART_CLEAR_FEFLAG() -
- __HAL_UART_CLEAR_NEFLAG() -
- __HAL_UART_CLEAR_OREFLAG() -
- __HAL_UART_CLEAR_IDLEFLAG() -
- - Remove the check on RXNE set after reading the Data in the DR register -
- Add IS_UART_LIN_WORD_LENGTH() and IS_UART_LIN_OVERSAMPLING() macros: to check respectively WordLength and OverSampling parameters in LIN mode -
- DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, UART TC interrupt is used instead. Below the update to be done on user application:
-
-
-
- Configure and enable the USART IRQ in HAL_UART_MspInit() function -
- In stm32f2xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_UART_IRQHandler() function -
- - IT transmit process; the code has been updated to avoid waiting on TC flag under UART ISR, UART TC interrupt is used instead. No impact on user application -
- Rename macros:
-
-
-
- __HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE() -
- __HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE() -
- - Rename literals:
-
-
-
- UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE -
- UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK -
- - Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for compliance with C++ -
- HAL_UART_Transmit_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual
-
-
-
- Add clear the TC flag in the SR register before enabling the DMA transmit request -
-
- - HAL USART update
-
-
-
- Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_USART_CLEAR_PEFLAG()
-
-
-
- __HAL_USART_CLEAR_FEFLAG() -
- __HAL_USART_CLEAR_NEFLAG() -
- __HAL_USART_CLEAR_OREFLAG() -
- __HAL_USART_CLEAR_IDLEFLAG() -
- - Update HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC -
- DMA transmit process; the code has been updated to avoid waiting on TC flag under DMA ISR, USART TC interrupt is used instead. Below the update to be done on user application:
-
-
-
- Configure and enable the USART IRQ in HAL_USART_MspInit() function -
- In stm32f2xx_it.c file, USARTx_IRQHandler() function: add a call to HAL_USART_IRQHandler() function -
- - IT transmit process; the code has been updated to avoid waiting on TC flag under USART ISR, USART TC interrupt is used instead. No impact on user application -
- HAL_USART_Init() update to enable the USART oversampling by 8 by default in order to reach max USART frequencies -
- USART_DMAReceiveCplt() update to set the new USART state after checking on the old state -
- HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() update to follow the right procedure “Transmission using DMA” in the reference manual
-
-
-
- Add clear the TC flag in the SR register before enabling the DMA transmit request -
- - Rename macros:
-
-
-
- __USART_ENABLE() by __HAL_USART_ENABLE() -
- __USART_DISABLE() by __HAL_USART_DISABLE() -
- __USART_ENABLE_IT() by __HAL_USART_ENABLE_IT() -
- __USART_DISABLE_IT() by __HAL_USART_DISABLE_IT() -
- - Rename literals: remove “D” from “DISABLED” and “ENABLED”
-
-
-
- USART_CLOCK_DISABLED by USART_CLOCK_DISABLE -
- USART_CLOCK_ENABLED by USART_CLOCK_ENABLE -
- USARTNACK_ENABLED by USART_NACK_ENABLE -
- USARTNACK_DISABLED by USART_NACK_DISABLE -
- - Add new user macros to manage the sample method feature
-
-
-
- __HAL_USART_ONE_BIT_SAMPLE_ENABLE() -
- __HAL_USART_ONE_BIT_SAMPLE_DISABLE() -
- - Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for compliance with C++ -
- HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected -
- - Add specific macros to manage the flags cleared only by a software sequence ◾__HAL_USART_CLEAR_PEFLAG()
-
- HAL WWDG update
-
-
-
- Update macro parameters to use underscore: XXX -
- Use of CMSIS constants instead of magic values -
- Use MODIFY_REG macro in HAL_WWDG_Init() -
- Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit() -
- Add new parameter in __HAL_WWDG_ENABLE_IT() macro -
- Add new macros to manage WWDG IT & correction:
-
-
-
- __HAL_WWDG_DISABLE() -
- __HAL_WWDG_DISABLE_IT() -
- __HAL_WWDG_GET_IT() -
- __HAL_WWDG_GET_IT_SOURCE() -
-
- - HAL IWDG update
-
-
-
- Use WRITE_REG instead of SET_BIT for all IWDG macros -
- __HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register -
- Use MODIFY_REG macro in HAL_IWDG_Init() -
- Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init() -
- Rename the defined IWDG keys:
-
-
-
- KR_KEY_RELOAD by IWDG_KEY_RELOAD -
- KR_KEY_ENABLE by IWDG_KEY_ENABLE -
- KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE -
- KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE -
- - Add new macro: __HAL_IWDG_RESET_HANDLE_STATE() -
- Update IWDG_ENABLE_WRITE_ACCESS() and IWDG_DISABLE_WRITE_ACCESS() as private macro -
- - HAL LL FSMC update
-
-
-
- Add WriteFifo and PageSize fields in the FSMC_NORSRAM_InitTypeDef structure -
- Update FSMC_NORSRAM_Init(), FSMC_NORSRAM_DeInit() and FSMC_NORSRAM_Extended_Timing_Init() functions -
- - HAL LL USB update
-
-
-
- Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation -
- USB_FlushTxFifo API: update to flush all Tx FIFO -
- Update to use local variable in USB Host channel re-activation -
-
-
-
-
-
-Main Changes
--
-
- Patch release : moved macros related to RNG from hal_rcc_ex.h to hal_rcc.h as RNG is present in all versions of the STM32F2 -
-
-
-
-
-Main Changes
--
-
- First official release -