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[bsp/renesas]: add ra4e2-eco

This commit is contained in:
Erik 2025-07-04 14:38:21 +08:00 committed by Rbb666
parent 207915ab24
commit ed5d877054
154 changed files with 188772 additions and 0 deletions
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1
.github/ALL_BSP_COMPILE.json vendored
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@ -250,6 +250,7 @@
"renesas/ra6m3-ek",
"renesas/ra6m3-hmi-board",
"renesas/ra6e2-fpb",
"renesas/ra4e2-eco",
"renesas/ra4m2-eco",
"renesas/ra2l1-cpk",
"renesas/ra8m1-ek",

21
bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
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@ -104,6 +104,26 @@ extern "C"
#endif
#endif /* SOC_SERIES_R7FA2L1 */
#ifdef SOC_SERIES_R7FA4E2
#include "ra4e2/uart_config.h"
#ifdef BSP_USING_ADC
#include "ra4e2/adc_config.h"
#endif
#ifdef BSP_USING_DAC
#include "ra4ra4e2m2/dac_config.h"
#endif
#ifdef BSP_USING_PWM
#include "ra4e2/pwm_config.h"
#endif
#ifdef BSP_USING_CAN
#include "ra4e2/can_config.h"
#endif
#endif /* SOC_SERIES_R7FA4E2 */
#ifdef SOC_SERIES_R7FA4M2
#include "ra4m2/uart_config.h"
@ -188,3 +208,4 @@ extern "C"
#endif
#endif /* __DRV_CONFIG_H__ */

42
bsp/renesas/libraries/HAL_Drivers/config/ra4e2/adc_config.h Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
struct rt_adc_dev
{
struct rt_adc_ops ops;
struct rt_adc_device adc_device;
};
struct ra_adc_map
{
const char *device_name;
const adc_cfg_t *g_cfg;
const adc_ctrl_t *g_ctrl;
const adc_channel_cfg_t *g_channel_cfg;
};
#endif
#endif
#ifdef __cplusplus
}
#endif

49
bsp/renesas/libraries/HAL_Drivers/config/ra4e2/can_config.h Normal file
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@ -0,0 +1,49 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-29 mazhiyuan first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_CAN0)
#ifndef CAN0_CONFIG
#define CAN0_CONFIG \
{ \
.name = "can0", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
.p_api_ctrl = &g_can0_ctrl, \
.p_cfg = &g_can0_cfg, \
}
#endif /* CAN0_CONFIG */
#endif /* BSP_USING_CAN0 */
#if defined(BSP_USING_CAN1)
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
.p_api_ctrl = &g_can1_ctrl, \
.p_cfg = &g_can1_cfg, \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */
#ifdef __cplusplus
}
#endif
#endif

41
bsp/renesas/libraries/HAL_Drivers/config/ra4e2/dac_config.h Normal file
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@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC
struct ra_dac_map
{
char name;
const struct st_dac_cfg *g_cfg;
const struct st_dac_instance_ctrl *g_ctrl;
};
struct ra_dac_dev
{
rt_dac_device_t ra_dac_device_t;
struct ra_dac_map *ra_dac_map_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif

69
bsp/renesas/libraries/HAL_Drivers/config/ra4e2/pwm_config.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-26 KevinXu first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
enum
{
#ifdef BSP_USING_PWM0
BSP_PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
BSP_PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
BSP_PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
BSP_PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
BSP_PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
BSP_PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
BSP_PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
BSP_PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
BSP_PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
BSP_PWM9_INDEX,
#endif
BSP_PWMS_NUM
};
#define PWM_DRV_INITIALIZER(num) \
{ \
.name = "pwm"#num , \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

137
bsp/renesas/libraries/HAL_Drivers/config/ra4e2/uart_config.h Normal file
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@ -0,0 +1,137 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.p_api_ctrl = &g_uart0_ctrl, \
.p_cfg = &g_uart0_cfg, \
}
#endif /* UART0_CONFIG */
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.p_api_ctrl = &g_uart1_ctrl, \
.p_cfg = &g_uart1_cfg, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.p_api_ctrl = &g_uart2_ctrl, \
.p_cfg = &g_uart2_cfg, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.p_api_ctrl = &g_uart3_ctrl, \
.p_cfg = &g_uart3_cfg, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.p_api_ctrl = &g_uart4_ctrl, \
.p_cfg = &g_uart4_cfg, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.p_api_ctrl = &g_uart5_ctrl, \
.p_cfg = &g_uart5_cfg, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.p_api_ctrl = &g_uart6_ctrl, \
.p_cfg = &g_uart6_cfg, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.p_api_ctrl = &g_uart7_ctrl, \
.p_cfg = &g_uart7_cfg, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.p_api_ctrl = &g_uart8_ctrl, \
.p_cfg = &g_uart8_cfg, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.p_api_ctrl = &g_uart9_ctrl, \
.p_cfg = &g_uart9_cfg, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#ifdef __cplusplus
}
#endif
#endif

6
bsp/renesas/libraries/Kconfig
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@ -31,6 +31,12 @@ config SOC_SERIES_R7FA6M5
select SOC_FAMILY_RENESAS_RA
default n
config SOC_SERIES_R7FA4E2
bool
select ARCH_ARM_CORTEX_M33
select SOC_FAMILY_RENESAS_RA
default n
config SOC_SERIES_R7FA4M2
bool
select ARCH_ARM_CORTEX_M4

1307
bsp/renesas/ra4e2-eco/.config Normal file
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File diff suppressed because it is too large Load Diff

5
bsp/renesas/ra4e2-eco/.gitignore vendored Normal file
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@ -0,0 +1,5 @@
/RTE
/Listings
/Objects
ra_cfg.txt

27
bsp/renesas/ra4e2-eco/.settings/standalone.prefs Normal file
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@ -0,0 +1,27 @@
#Thu Jul 03 23:33:55 CST 2025
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#6.1.0+fsp.5.9.0/all=1441545198,ra/arm/CMSIS_6/LICENSE|409404162,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h|3070162158,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h|2642675438,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h|432601292,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h|1219721305,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h|1716662092,ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h|3033126542,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h|3716711724,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h|1573341164,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h|1528066797,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h|956077447,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h|3181146757,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h|3422691989,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h|3011809468,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h|862174236,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h|3557548549,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h|2145813412,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h|215226313,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h|3759822293,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h|3285488134,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h|3342995321,ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h|440777068,ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h|987654843,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h|1790528804,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h|117658130,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h|3644000269,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h|947683335,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h|3200474466,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h|2703360002,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h|271089146,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h|3180041419,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h|1572899130,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h|1964429271,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h|2095512231,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h|2951442685,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h|1179088122,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h|1753083115,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h|163659099,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h|718227869,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h|681720804,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h|154254372,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#6.1.0+fsp.5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra4e2_fpb\#\#\#\#5.9.0/all=3582453363,ra/board/ra4e2_fpb/board.h|2896414481,ra/board/ra4e2_fpb/board_init.c|3253082331,ra/board/ra4e2_fpb/board_init.h|2991560567,ra/board/ra4e2_fpb/board_leds.c|3045537102,ra/board/ra4e2_fpb/board_leds.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra4e2_fpb\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#device\#\#\#\#5.9.0/all=2861757161,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#device\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#device\#\#R7FA4E2B93CFM\#\#5.9.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#device\#\#R7FA4E2B93CFM\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#events\#\#\#\#5.9.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#events\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#fsp\#\#\#\#5.9.0/all=737697109,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|109493390,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3173683717,ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h|1260461465,ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h|1977341195,ra/fsp/src/bsp/mcu/ra4e2/bsp_mcu_info.h|561992683,ra/fsp/src/bsp/mcu/ra4e2/bsp_peripheral.h|1736202474,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1697962378,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|864672585,ra/fsp/src/bsp/mcu/all/bsp_common.c|3719181226,ra/fsp/src/bsp/mcu/all/bsp_common.h|971295641,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1230338327,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2662182446,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1002834645,ra/fsp/src/bsp/mcu/all/bsp_exceptions.h|2678793973,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2982971571,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|3480596119,ra/fsp/src/bsp/mcu/all/bsp_guard.c|379456290,ra/fsp/src/bsp/mcu/all/bsp_guard.h|554349144,ra/fsp/src/bsp/mcu/all/bsp_io.c|1270173761,ra/fsp/src/bsp/mcu/all/bsp_io.h|2440079210,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2972687487,ra/fsp/src/bsp/mcu/all/bsp_irq.h|3308061560,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1712869516,ra/fsp/src/bsp/mcu/all/bsp_mmf.h|2063080463,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|297343942,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|277796574,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|982162934,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2062061941,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1725271817,ra/fsp/src/bsp/mcu/all/bsp_sdram.c|2275550317,ra/fsp/src/bsp/mcu/all/bsp_sdram.h|2205243978,ra/fsp/src/bsp/mcu/all/board_sdram.h|103411416,ra/fsp/src/bsp/mcu/all/bsp_security.c|1515045059,ra/fsp/src/bsp/mcu/all/bsp_security.h|686902729,ra/fsp/src/bsp/mcu/all/bsp_macl.c|3660402312,ra/fsp/src/bsp/mcu/all/bsp_macl.h|3202460155,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2646736735,ra/fsp/inc/fsp_features.h|494301981,ra/fsp/inc/instances/r_ioport.h|2725574191,script/fsp.scat|346195372,script/ac6/fsp_keep.via
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4e2\#\#fsp\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.9.0/all=2526699076,ra/fsp/inc/fsp_version.h|3114565751,ra/fsp/inc/api/fsp_common_api.h|1692739955,ra/fsp/inc/api/r_ioport_api.h|2238316510,ra/fsp/inc/api/bsp_api.h|3066967601,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2057644446,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.9.0/all=1692739955,ra/fsp/inc/api/r_ioport_api.h|494301981,ra/fsp/inc/instances/r_ioport.h|3160786249,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#5.9.0/all=2458545632,ra/fsp/inc/api/r_transfer_api.h|2561410940,ra/fsp/inc/api/r_uart_api.h|3350247515,ra/fsp/inc/instances/r_sci_uart.h|3173989482,ra/fsp/src/r_sci_uart/r_sci_uart.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#5.9.0/libraries=
com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_sci_i2c.151106823=false
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_sci_i2c.1519643068=false
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_sci_i2c.2057056591=false
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.2136651481=false

17
bsp/renesas/ra4e2-eco/Kconfig Normal file
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@ -0,0 +1,17 @@
mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
PKGS_DIR := packages
ENV_DIR := /
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
source "$(BSP_DIR)/board/Kconfig"

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# 瑞萨 RA-Eco-RA4E2-64PIN 开发板 BSP 说明
## 简介
本文档为瑞萨 RA-Eco-RA4E2-64PIN 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
RA-Eco-RA4E2-64PIN-V1.0是一款基于100MHz Arm® Cortex®-M33内核架构的核心板，主控芯片为R7FA4E2B93CFM。RA4E2组是RA4系列中最新的入门级微控制器，基于带有TrustZone的100MHz Arm® Cortex®-M33内核。RA4E2 MCU提供了高性能和优化的外设功能以及最小的封装选项，包括节省空间的36引脚BGA和32引脚QFN封装。这些都满足了对成本敏感和空间受限的应用的需要。由于RA4E2具有均衡的性能、先进的外设功能和可扩展性，它为更广泛的RA系列提供了一个入门点。
开发板正面外观如下图：
![image-20211011174017429](docs/picture/RA-Eco-RA4E2-64PIN.jpg)
该开发板常用 **板载资源** 如下：
- MCU：R7FA4E2B93CFM，100MHz，Arm Cortex®-M33 内核
- 128KB 代码闪存, 40KB SRAM
- 1个复位按键
- 1个自定义按键
- 2个LED
- 扩展接口：两个 PMOD 连接器
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
| UART | 支持 | UART9 为默认日志输出端口 |
| GPIO | 支持 | |
| I3C/I2C | 支持 | 未验证 |
| ADC | 支持 | 未验证 |
| DAC | 支持 | 未验证 |
| SPI | 支持 | 未验证 |
| FLASH | 支持 | 未验证 |
| PWM | 支持 | 未验证 |
| CAN FD | 支持 | 未验证 |
| 持续更新中... | | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**硬件连接**
使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART9：P109(TXD)、P110(RXD)。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA4E2B9，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/rtthread.hex 文件，点击 Program Device 按钮开始烧录。
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.2.1 build Jul 4 2025 00:07:09
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
msh >help
RT-Thread shell commands:
pin - pin [option]
sensor_fifo - Sensor fifo mode test function
sensor_int - Sensor interrupt mode test function
sensor_polling - Sensor polling mode test function
sensor - sensor test function
reboot - Reboot System
clear - clear the terminal screen
version - show RT-Thread version information
list - list objects
help - RT-Thread shell help
ps - List threads in the system
free - Show the memory usage in the system
backtrace - print backtrace of a thread
msh >
```
**应用入口函数**
应用层的入口函数在 **bsp\ra4e2-eco\src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 RA-Eco-RA4E2-64PIN 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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menu "Hardware Drivers Config"
config SOC_R7FA4E2B9
bool
select SOC_SERIES_R7FA4E2
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select ARCH_ARM_CORTEX_SECURE
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
rsource "../../libraries/HAL_Drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART9
bool "Enable UART9"
default n
if BSP_USING_UART9
config BSP_UART9_RX_USING_DMA
bool "Enable UART9 RX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_TX_USING_DMA
bool "Enable UART9 TX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART9_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_HW_I2C
bool "Enable hardware I2C BUS"
select RT_USING_I2C
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
config BSP_USING_HW_I2C2
bool "Enable Hardware I2C2 BUS"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 40 /* The SRAM size of the chip needs to be modified */
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __RAM_segment_used_end__;
#define HEAP_BEGIN (&__RAM_segment_used_end__)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

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from building import *
import rtconfig
cwd = GetCurrentDir()
src = []
if GetDepend(['BSP_USING_RW007']):
src += Glob('drv_rw007.c')
CPPPATH = [cwd, cwd+"/../"]
LOCAL_CFLAGS = ''
if rtconfig.PLATFORM in ['gcc', 'armclang']:
LOCAL_CFLAGS += ' -std=c99'
elif rtconfig.PLATFORM in ['armcc']:
LOCAL_CFLAGS += ' --c99'
group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
Return('group')

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-01-19 Sherman first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE(pin) \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_04_PIN_00: \
case BSP_IO_PORT_02_PIN_06: \
case BSP_IO_PORT_01_PIN_05: \
return 0; \
case BSP_IO_PORT_02_PIN_05: \
case BSP_IO_PORT_01_PIN_01: \
case BSP_IO_PORT_01_PIN_04: \
return 1; \
case BSP_IO_PORT_02_PIN_03: \
case BSP_IO_PORT_01_PIN_00: \
case BSP_IO_PORT_02_PIN_13: \
return 2; \
case BSP_IO_PORT_02_PIN_02: \
case BSP_IO_PORT_01_PIN_10: \
case BSP_IO_PORT_02_PIN_12: \
return 3; \
case BSP_IO_PORT_04_PIN_02: \
case BSP_IO_PORT_01_PIN_11: \
case BSP_IO_PORT_04_PIN_11: \
return 4; \
case BSP_IO_PORT_04_PIN_01: \
case BSP_IO_PORT_03_PIN_02: \
case BSP_IO_PORT_04_PIN_10: \
return 5; \
case BSP_IO_PORT_03_PIN_01: \
case BSP_IO_PORT_00_PIN_00: \
case BSP_IO_PORT_04_PIN_09: \
return 6; \
case BSP_IO_PORT_00_PIN_01: \
case BSP_IO_PORT_04_PIN_08: \
return 7; \
case BSP_IO_PORT_00_PIN_02: \
case BSP_IO_PORT_03_PIN_05: \
case BSP_IO_PORT_04_PIN_15: \
return 8; \
case BSP_IO_PORT_00_PIN_04: \
case BSP_IO_PORT_03_PIN_04: \
case BSP_IO_PORT_04_PIN_14: \
return 9; \
case BSP_IO_PORT_00_PIN_05: \
case BSP_IO_PORT_07_PIN_09: \
return 10; \
case BSP_IO_PORT_05_PIN_01: \
case BSP_IO_PORT_00_PIN_06: \
case BSP_IO_PORT_07_PIN_08: \
return 11; \
case BSP_IO_PORT_05_PIN_02: \
case BSP_IO_PORT_00_PIN_08: \
return 12; \
case BSP_IO_PORT_00_PIN_15: \
case BSP_IO_PORT_00_PIN_09: \
return 13; \
case BSP_IO_PORT_04_PIN_03: \
case BSP_IO_PORT_05_PIN_12: \
case BSP_IO_PORT_05_PIN_05: \
return 14; \
case BSP_IO_PORT_04_PIN_04: \
case BSP_IO_PORT_05_PIN_11: \
case BSP_IO_PORT_05_PIN_06: \
return 15; \
default : \
return -1; \
} \
}

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.c"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_6/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h" path=""/>
<file category="header" name="ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_6/LICENSE"/>
<file category="header" name="ra/board/ra4e2_fpb/board.h" path=""/>
<file category="source" name="ra/board/ra4e2_fpb/board_init.c"/>
<file category="header" name="ra/board/ra4e2_fpb/board_init.h" path=""/>
<file category="source" name="ra/board/ra4e2_fpb/board_leds.c"/>
<file category="header" name="ra/board/ra4e2_fpb/board_leds.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E2B9.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/board_sdram.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_macl.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_macl.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_macl.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mmf.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sdram.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4e2/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4e2/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4e2/bsp_mcu_info.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4e2/bsp_peripheral.h" path=""/>
<file category="other" name="ra/fsp/src/r_icu/r_icu.o"/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="other" name="ra/fsp/src/r_sci_i2c/r_sci_i2c.o"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

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bsp/renesas/ra4e2-eco/configuration.xml Normal file
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@ -0,0 +1,426 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="11">
<generalSettings>
<option key="#Board#" value="board.ra4e2fpb"/>
<option key="CPU" value="RA4E2"/>
<option key="Core" value="CM33"/>
<option key="#TargetName#" value="R7FA4E2B93CFM"/>
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
<option key="#DeviceCommand#" value="R7FA4E2B9"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA4E2B93CFM.pincfg"/>
<option key="#FSPVersion#" value="5.9.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra4e2_fpb##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration>
<config id="config.bsp.ra4e2.R7FA4E2B93CFM">
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
<property id="config.bsp.rom_size_bytes_hidden" value="131072"/>
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
<property id="config.bsp.irq_count_hidden" value="96"/>
</config>
<config id="config.bsp.ra4e2">
<property id="config.bsp.series" value="config.bsp.series.value"/>
</config>
<config id="config.bsp.ra4e2.fsp">
<property id="config.bsp.fsp.inline_irq_functions" value="config.bsp.common.inline_irq_functions.enabled"/>
<property id="config.bsp.fsp.tz.exception_response" value="config.bsp.fsp.tz.exception_response.nmi"/>
<property id="config.bsp.fsp.tz.cmsis.bfhfnmins" value="config.bsp.fsp.tz.cmsis.bfhfnmins.secure"/>
<property id="config.bsp.fsp.tz.cmsis.sysresetreqs" value="config.bsp.fsp.tz.cmsis.sysresetreqs.secure_only"/>
<property id="config.bsp.fsp.tz.cmsis.s_priority_boost" value="config.bsp.fsp.tz.cmsis.s_priority_boost.disabled"/>
<property id="config.bsp.fsp.tz.csar" value="config.bsp.fsp.tz.csar.both"/>
<property id="config.bsp.fsp.tz.rstsar" value="config.bsp.fsp.tz.rstsar.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramprcr" value="config.bsp.fsp.tz.sramsar.sramprcr.both"/>
<property id="config.bsp.fsp.tz.sramsar.sramecc" value="config.bsp.fsp.tz.sramsar.sramecc.both"/>
<property id="config.bsp.fsp.tz.stbramsar" value="config.bsp.fsp.tz.stbramsar.both"/>
<property id="config.bsp.fsp.tz.bussara" value="config.bsp.fsp.tz.bussara.both"/>
<property id="config.bsp.fsp.tz.bussarb" value="config.bsp.fsp.tz.bussarb.both"/>
<property id="config.bsp.fsp.tz.uninitialized_ns_application_fallback" value="config.bsp.fsp.tz.uninitialized_ns_application_fallback.enabled"/>
<property id="config.bsp.fsp.cache_line_size" value="config.bsp.fsp.cache_line_size.32"/>
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
<property id="config.bsp.fsp.BPS.BPS0" value=""/>
<property id="config.bsp.fsp.PBPS.PBPS0" value=""/>
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="50000000"/>
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="16666666"/>
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
<property id="config.bsp.fsp.mcu.adc.sensors_are_exclusive" value="0"/>
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="25000000"/>
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="50000000"/>
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
<property id="config.bsp.fsp.mcu.canfd.num_channels" value="1"/>
<property id="config.bsp.fsp.mcu.canfd.rx_fifos" value="2"/>
<property id="config.bsp.fsp.mcu.canfd.buffer_ram" value="1216"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules" value="32"/>
<property id="config.bsp.fsp.mcu.canfd.afl_rules_each_chnl" value="32"/>
<property id="config.bsp.fsp.mcu.canfd.max_data_rate_hz" value="8"/>
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0201"/>
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
<property id="config.bsp.fsp.mcu.adc_dmac.samples_per_channel" value="32767"/>
<property id="config.bsp.fsp.mcu.rtc.err_adjustment_value.max_value" value="63"/>
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
<property id="config.bsp.common.id1" value=""/>
<property id="config.bsp.common.id2" value=""/>
<property id="config.bsp.common.id3" value=""/>
<property id="config.bsp.common.id4" value=""/>
<property id="config.bsp.common.id_fixed" value=""/>
</config>
<config id="config.bsp.ra">
<property id="config.bsp.common.main" value="0x400"/>
<property id="config.bsp.common.heap" value="0"/>
<property id="config.bsp.common.vcc" value="3300"/>
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.disabled"/>
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
</config>
</raBspConfiguration>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.hoco"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.100"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.cecclk.source" option="board.clock.cecclk.source.disabled"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.6"/>
<node id="board.clock.cecclk.div" option="board.clock.cecclk.div.1"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.1"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.cecclk.display" option="board.clock.cecclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
</raClockConfiguration>
<raComponentSelection>
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="5.9.0">
<description>Board Support Package Common Files</description>
<originalPack>Renesas.RA.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="5.9.0">
<description>I/O Port</description>
<originalPack>Renesas.RA.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="6.1.0+fsp.5.9.0">
<description>Arm CMSIS Version 6 - Core (M)</description>
<originalPack>Arm.CMSIS6.6.1.0+fsp.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="Board" subgroup="ra4e2_fpb" variant="" vendor="Renesas" version="5.9.0">
<description>RA4E2-FPB Board Support Files</description>
<originalPack>Renesas.RA_board_ra4e2_fpb.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4e2" subgroup="device" variant="R7FA4E2B93CFM" vendor="Renesas" version="5.9.0">
<description>Board support package for R7FA4E2B93CFM</description>
<originalPack>Renesas.RA_mcu_ra4e2.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4e2" subgroup="device" variant="" vendor="Renesas" version="5.9.0">
<description>Board support package for RA4E2</description>
<originalPack>Renesas.RA_mcu_ra4e2.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4e2" subgroup="fsp" variant="" vendor="Renesas" version="5.9.0">
<description>Board support package for RA4E2 - FSP Data</description>
<originalPack>Renesas.RA_mcu_ra4e2.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="BSP" condition="" group="ra4e2" subgroup="events" variant="" vendor="Renesas" version="5.9.0">
<description>Board support package for RA4E2 - Events</description>
<originalPack>Renesas.RA_mcu_ra4e2.5.9.0.pack</originalPack>
</component>
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="5.9.0">
<description>SCI UART</description>
<originalPack>Renesas.RA.5.9.0.pack</originalPack>
</component>
</raComponentSelection>
<raElcConfiguration/>
<raIcuConfiguration/>
<raModuleConfiguration>
<module id="module.driver.ioport_on_ioport.0">
<property id="module.driver.ioport.name" value="g_ioport"/>
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
</module>
<module id="module.driver.uart_on_sci_uart.2136651481">
<property id="module.driver.uart.name" value="g_uart9"/>
<property id="module.driver.uart.channel" value="9"/>
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
<property id="module.driver.uart.baud" value="115200"/>
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
<property id="module.driver.uart.baudrate_max_err" value="5"/>
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
<property id="module.driver.uart.irda.ire" value="module.driver.uart.irda.ire.disabled"/>
<property id="module.driver.uart.irda.irrxinv" value="module.driver.uart.irda.irrxinv.disabled"/>
<property id="module.driver.uart.irda.irtxinv" value="module.driver.uart.irda.irtxinv.disabled"/>
<property id="module.driver.uart.rs485.de_enable" value="module.driver.uart.rs485.de_enable.disabled"/>
<property id="module.driver.uart.rs485.de_polarity" value="module.driver.uart.rs485.de_polarity.high"/>
<property id="module.driver.uart.rs485.de_port_number" value="module.driver.uart.rs485.de_port_number.PORT_DISABLE"/>
<property id="module.driver.uart.rs485.de_pin_number" value="module.driver.uart.rs485.de_pin_number.PIN_DISABLE"/>
<property id="module.driver.uart.callback" value="user_uart9_callback"/>
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
</module>
<context id="_hal.0">
<stack module="module.driver.ioport_on_ioport.0"/>
<stack module="module.driver.uart_on_sci_uart.2136651481"/>
</context>
<config id="config.driver.sci_uart">
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
<property id="config.driver.sci_uart.rs485" value="config.driver.sci_uart.rs485.disabled"/>
<property id="config.driver.sci_uart.irda" value="config.driver.sci_uart.irda.disabled"/>
</config>
<config id="config.driver.ioport">
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
</config>
</raModuleConfiguration>
<raPinConfiguration>
<symbolicName propertyId="p000.symbolic_name" value="ARDUINO_A0"/>
<symbolicName propertyId="p001.symbolic_name" value="ARDUINO_A1"/>
<symbolicName propertyId="p002.symbolic_name" value="ARDUINO_A2"/>
<symbolicName propertyId="p003.symbolic_name" value="ARDUINO_A4"/>
<symbolicName propertyId="p004.symbolic_name" value="ARDUINO_A3"/>
<symbolicName propertyId="p005.symbolic_name" value="PMOD1_RESET"/>
<symbolicName propertyId="p006.symbolic_name" value="ARDUINO_D8"/>
<symbolicName propertyId="p008.symbolic_name" value="ARDUINO_D7"/>
<symbolicName propertyId="p013.symbolic_name" value="ARDUINO_A5"/>
<symbolicName propertyId="p014.symbolic_name" value="PMOD2_GPIO1"/>
<symbolicName propertyId="p015.symbolic_name" value="PMOD2_GPIO2"/>
<symbolicName propertyId="p100.symbolic_name" value="I3C_SCL_ARDUINO_SCL"/>
<symbolicName propertyId="p101.symbolic_name" value="I3C_SDA_ARDUINO_SDA"/>
<symbolicName propertyId="p102.symbolic_name" value="PMOD2_SCK"/>
<symbolicName propertyId="p105.symbolic_name" value="ARDUINO_D2"/>
<symbolicName propertyId="p106.symbolic_name" value="PMOD1_GPIO1"/>
<symbolicName propertyId="p107.symbolic_name" value="PMOD1_GPIO2"/>
<symbolicName propertyId="p108.symbolic_name" value="DEBUG_SWDIO"/>
<symbolicName propertyId="p109.symbolic_name" value="PMOD1_TX_ARDUINO_D11"/>
<symbolicName propertyId="p110.symbolic_name" value="PMOD1_RX_ARDUINO_D12"/>
<symbolicName propertyId="p111.symbolic_name" value="PMOD1_RSPCK_ARDUINO_D13"/>
<symbolicName propertyId="p113.symbolic_name" value="ARDUINO_D6"/>
<symbolicName propertyId="p200.symbolic_name" value="NMI"/>
<symbolicName propertyId="p201.symbolic_name" value="BOOT_MODE"/>
<symbolicName propertyId="p205.symbolic_name" value="PMOD2_IRQ"/>
<symbolicName propertyId="p206.symbolic_name" value="LED2"/>
<symbolicName propertyId="p207.symbolic_name" value="LED1"/>
<symbolicName propertyId="p208.symbolic_name" value="ARDUINO_RESET"/>
<symbolicName propertyId="p300.symbolic_name" value="DEBUG_SWDCLK"/>
<symbolicName propertyId="p301.symbolic_name" value="ARDUINO_D10"/>
<symbolicName propertyId="p304.symbolic_name" value="SW1"/>
<symbolicName propertyId="p400.symbolic_name" value="I2C_I3C_SEL_SCL"/>
<symbolicName propertyId="p401.symbolic_name" value="I2C_I3C_SEL_SDA"/>
<symbolicName propertyId="p402.symbolic_name" value="PMOD1_IRQ"/>
<symbolicName propertyId="p403.symbolic_name" value="ARDUINO_D9"/>
<symbolicName propertyId="p407.symbolic_name" value="PMOD2_RESET"/>
<symbolicName propertyId="p408.symbolic_name" value="ARDUINO_D3"/>
<symbolicName propertyId="p409.symbolic_name" value="ARDUINO_D5"/>
<symbolicName propertyId="p410.symbolic_name" value="PMOD2_MISO_ARDUINO_D0"/>
<symbolicName propertyId="p411.symbolic_name" value="PMOD2_MOSI_ARDUINO_D1"/>
<symbolicName propertyId="p500.symbolic_name" value="ARDUINO_D4"/>
<pincfg active="true" name="RA4E2 FPB" selected="true" symbol="g_bsp_pin_cfg">
<configSetting altId="adc0.an000.p000" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p001" configurationId="adc0.an001"/>
<configSetting altId="adc0.an002.p002" configurationId="adc0.an002"/>
<configSetting altId="adc0.an004.p004" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p003" configurationId="adc0.an007"/>
<configSetting altId="adc0.an011.p013" configurationId="adc0.an011"/>
<configSetting altId="adc0.mode.custom.free" configurationId="adc0.mode"/>
<configSetting altId="i3c_fslash_iic.i3c_scl.p100" configurationId="i3c_fslash_iic.i3c_scl"/>
<configSetting altId="i3c_fslash_iic.i3c_sda.p101" configurationId="i3c_fslash_iic.i3c_sda"/>
<configSetting altId="i3c_fslash_iic.mode.custom.free" configurationId="i3c_fslash_iic.mode"/>
<configSetting altId="irq.irq1.p104" configurationId="irq.irq1"/>
<configSetting altId="irq.irq2.p213" configurationId="irq.irq2"/>
<configSetting altId="irq.irq3.p212" configurationId="irq.irq3"/>
<configSetting altId="irq.irq5.p302" configurationId="irq.irq5"/>
<configSetting altId="irq.irq9.p304" configurationId="irq.irq9"/>
<configSetting altId="irq.mode.custom.free" configurationId="irq.mode"/>
<configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.swclk.p300" configurationId="jtag_fslash_swd.swclk"/>
<configSetting altId="jtag_fslash_swd.swdio.p108" configurationId="jtag_fslash_swd.swdio"/>
<configSetting altId="p000.adc0.an000" configurationId="p000"/>
<configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
<configSetting altId="p001.adc0.an001" configurationId="p001"/>
<configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
<configSetting altId="p002.adc0.an002" configurationId="p002"/>
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
<configSetting altId="p003.adc0.an007" configurationId="p003"/>
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
<configSetting altId="p004.adc0.an004" configurationId="p004"/>
<configSetting altId="p004.gpio_mode.gpio_mode_an" configurationId="p004.gpio_mode"/>
<configSetting altId="p005.input" configurationId="p005"/>
<configSetting altId="p005.gpio_mode.gpio_mode_in" configurationId="p005.gpio_mode"/>
<configSetting altId="p006.input" configurationId="p006"/>
<configSetting altId="p006.gpio_mode.gpio_mode_in" configurationId="p006.gpio_mode"/>
<configSetting altId="p008.input" configurationId="p008"/>
<configSetting altId="p008.gpio_mode.gpio_mode_in" configurationId="p008.gpio_mode"/>
<configSetting altId="p013.adc0.an011" configurationId="p013"/>
<configSetting altId="p013.gpio_mode.gpio_mode_an" configurationId="p013.gpio_mode"/>
<configSetting altId="p014.input" configurationId="p014"/>
<configSetting altId="p014.gpio_mode.gpio_mode_in" configurationId="p014.gpio_mode"/>
<configSetting altId="p015.input" configurationId="p015"/>
<configSetting altId="p015.gpio_mode.gpio_mode_in" configurationId="p015.gpio_mode"/>
<configSetting altId="p100.i3c_fslash_iic.i3c_scl" configurationId="p100"/>
<configSetting altId="p100.gpio_speed.gpio_speed_h" configurationId="p100.gpio_drivecapacity"/>
<configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
<configSetting altId="p101.i3c_fslash_iic.i3c_sda" configurationId="p101"/>
<configSetting altId="p101.gpio_speed.gpio_speed_h" configurationId="p101.gpio_drivecapacity"/>
<configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
<configSetting altId="p104.irq.irq1" configurationId="p104"/>
<configSetting altId="p104.gpio_irq.gpio_irq_enabled" configurationId="p104.gpio_irq"/>
<configSetting altId="p104.gpio_mode.gpio_mode_irq" configurationId="p104.gpio_mode"/>
<configSetting altId="p105.input" configurationId="p105"/>
<configSetting altId="p105.gpio_mode.gpio_mode_in" configurationId="p105.gpio_mode"/>
<configSetting altId="p106.input" configurationId="p106"/>
<configSetting altId="p106.gpio_mode.gpio_mode_in" configurationId="p106.gpio_mode"/>
<configSetting altId="p107.input" configurationId="p107"/>
<configSetting altId="p107.gpio_mode.gpio_mode_in" configurationId="p107.gpio_mode"/>
<configSetting altId="p108.jtag_fslash_swd.swdio" configurationId="p108"/>
<configSetting altId="p108.gpio_speed.gpio_speed_h" configurationId="p108.gpio_drivecapacity"/>
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
<configSetting altId="p109.sci9.txd9" configurationId="p109"/>
<configSetting altId="p109.gpio_speed.gpio_speed_h" configurationId="p109.gpio_drivecapacity"/>
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
<configSetting altId="p110.sci9.rxd9" configurationId="p110"/>
<configSetting altId="p110.gpio_speed.gpio_speed_h" configurationId="p110.gpio_drivecapacity"/>
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
<configSetting altId="p111.input" configurationId="p111"/>
<configSetting altId="p111.gpio_mode.gpio_mode_in" configurationId="p111.gpio_mode"/>
<configSetting altId="p113.input" configurationId="p113"/>
<configSetting altId="p113.gpio_mode.gpio_mode_in" configurationId="p113.gpio_mode"/>
<configSetting altId="p205.input" configurationId="p205"/>
<configSetting altId="p205.gpio_mode.gpio_mode_in" configurationId="p205.gpio_mode"/>
<configSetting altId="p206.output.low" configurationId="p206"/>
<configSetting altId="p206.gpio_speed.gpio_speed_h" configurationId="p206.gpio_drivecapacity"/>
<configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/>
<configSetting altId="p207.output.low" configurationId="p207"/>
<configSetting altId="p207.gpio_speed.gpio_speed_h" configurationId="p207.gpio_drivecapacity"/>
<configSetting altId="p207.gpio_mode.gpio_mode_peripheral" configurationId="p207.gpio_mode"/>
<configSetting altId="p208.input" configurationId="p208"/>
<configSetting altId="p208.gpio_mode.gpio_mode_in" configurationId="p208.gpio_mode"/>
<configSetting altId="p212.irq.irq3" configurationId="p212"/>
<configSetting altId="p212.gpio_irq.gpio_irq_enabled" configurationId="p212.gpio_irq"/>
<configSetting altId="p212.gpio_mode.gpio_mode_irq" configurationId="p212.gpio_mode"/>
<configSetting altId="p213.irq.irq2" configurationId="p213"/>
<configSetting altId="p213.gpio_irq.gpio_irq_enabled" configurationId="p213.gpio_irq"/>
<configSetting altId="p213.gpio_mode.gpio_mode_irq" configurationId="p213.gpio_mode"/>
<configSetting altId="p300.jtag_fslash_swd.swclk" configurationId="p300"/>
<configSetting altId="p300.gpio_speed.gpio_speed_h" configurationId="p300.gpio_drivecapacity"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
<configSetting altId="p301.input" configurationId="p301"/>
<configSetting altId="p301.gpio_mode.gpio_mode_in" configurationId="p301.gpio_mode"/>
<configSetting altId="p302.irq.irq5" configurationId="p302"/>
<configSetting altId="p302.gpio_irq.gpio_irq_enabled" configurationId="p302.gpio_irq"/>
<configSetting altId="p302.gpio_mode.gpio_mode_irq" configurationId="p302.gpio_mode"/>
<configSetting altId="p304.irq.irq9" configurationId="p304"/>
<configSetting altId="p304.gpio_irq.gpio_irq_enabled" configurationId="p304.gpio_irq"/>
<configSetting altId="p304.gpio_mode.gpio_mode_irq" configurationId="p304.gpio_mode"/>
<configSetting altId="p400.output.high" configurationId="p400"/>
<configSetting altId="p400.gpio_speed.gpio_speed_h" configurationId="p400.gpio_drivecapacity"/>
<configSetting altId="p400.gpio_mode.gpio_mode_out.high" configurationId="p400.gpio_mode"/>
<configSetting altId="p401.output.high" configurationId="p401"/>
<configSetting altId="p401.gpio_speed.gpio_speed_h" configurationId="p401.gpio_drivecapacity"/>
<configSetting altId="p401.gpio_mode.gpio_mode_out.high" configurationId="p401.gpio_mode"/>
<configSetting altId="p402.input" configurationId="p402"/>
<configSetting altId="p402.gpio_mode.gpio_mode_in" configurationId="p402.gpio_mode"/>
<configSetting altId="p403.input" configurationId="p403"/>
<configSetting altId="p403.gpio_mode.gpio_mode_in" configurationId="p403.gpio_mode"/>
<configSetting altId="p407.input" configurationId="p407"/>
<configSetting altId="p407.gpio_mode.gpio_mode_in" configurationId="p407.gpio_mode"/>
<configSetting altId="p408.input" configurationId="p408"/>
<configSetting altId="p408.gpio_mode.gpio_mode_in" configurationId="p408.gpio_mode"/>
<configSetting altId="p409.input" configurationId="p409"/>
<configSetting altId="p409.gpio_mode.gpio_mode_in" configurationId="p409.gpio_mode"/>
<configSetting altId="p410.sci0.rxd0" configurationId="p410"/>
<configSetting altId="p410.gpio_speed.gpio_speed_h" configurationId="p410.gpio_drivecapacity"/>
<configSetting altId="p410.gpio_mode.gpio_mode_peripheral" configurationId="p410.gpio_mode"/>
<configSetting altId="p411.sci0.txd0" configurationId="p411"/>
<configSetting altId="p411.gpio_speed.gpio_speed_h" configurationId="p411.gpio_drivecapacity"/>
<configSetting altId="p411.gpio_mode.gpio_mode_peripheral" configurationId="p411.gpio_mode"/>
<configSetting altId="p500.input" configurationId="p500"/>
<configSetting altId="p500.gpio_mode.gpio_mode_in" configurationId="p500.gpio_mode"/>
<configSetting altId="sci0.mode.simplei2c.b" configurationId="sci0.mode"/>
<configSetting altId="sci0.pairing.b" configurationId="sci0.pairing"/>
<configSetting altId="sci0.rxd0.p410" configurationId="sci0.rxd0"/>
<configSetting altId="sci0.txd0.p411" configurationId="sci0.txd0"/>
<configSetting altId="sci9.mode.asynchronousuart.b" configurationId="sci9.mode"/>
<configSetting altId="sci9.pairing.b" configurationId="sci9.pairing"/>
<configSetting altId="sci9.rxd9.p110" configurationId="sci9.rxd9"/>
<configSetting altId="sci9.txd9.p109" configurationId="sci9.txd9"/>
<lockSetting id="irq.irq1" lock="true"/>
<lockSetting id="irq.irq2" lock="true"/>
<lockSetting id="irq.irq5" lock="true"/>
</pincfg>
<pincfg active="false" name="R7FA4E2B93CFM.pincfg" selected="false" symbol="">
<configSetting altId="jtag_fslash_swd.mode.swd.free" configurationId="jtag_fslash_swd.mode"/>
<configSetting altId="jtag_fslash_swd.swclk.p300" configurationId="jtag_fslash_swd.swclk"/>
<configSetting altId="jtag_fslash_swd.swdio.p108" configurationId="jtag_fslash_swd.swdio"/>
<configSetting altId="p108.jtag_fslash_swd.swdio" configurationId="p108"/>
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
<configSetting altId="p300.jtag_fslash_swd.swclk" configurationId="p300"/>
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

BIN
bsp/renesas/ra4e2-eco/docs/picture/RA-Eco-RA4E2-64PIN.jpg Normal file
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Width:  |  Height:  |  Size: 348 KiB

22
bsp/renesas/ra4e2-eco/memory_regions.scat Normal file
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@ -0,0 +1,22 @@
/* generated memory regions file - do not edit */
#define RAM_START 0x20000000
#define RAM_LENGTH 0xA000
#define FLASH_START 0x00000000
#define FLASH_LENGTH 0x20000
#define DATA_FLASH_START 0x08000000
#define DATA_FLASH_LENGTH 0x1000
#define OPTION_SETTING_START 0x0100A100
#define OPTION_SETTING_LENGTH 0x100
#define OPTION_SETTING_S_START 0x0100A200
#define OPTION_SETTING_S_LENGTH 0x100
#define ID_CODE_START 0x0100A120
#define ID_CODE_LENGTH 0x10
#define SDRAM_START 0x80010000
#define SDRAM_LENGTH 0x0
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x0
#define OSPI_DEVICE_0_START 0x80020000
#define OSPI_DEVICE_0_LENGTH 0x0
#define OSPI_DEVICE_1_START 0x80030000
#define OSPI_DEVICE_1_LENGTH 0x0

957
bsp/renesas/ra4e2-eco/project.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target_1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
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bsp/renesas/ra4e2-eco/project.uvprojx Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += Glob(cwd + '/fsp/src/r_*/*.c')
CPPPATH = [ cwd + '/arm/CMSIS_6/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File
*/
#ifndef __CMSIS_ARMCLANG_A_H
#define __CMSIS_ARMCLANG_A_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_ARMCLANG_H
#error "This file must not be included directly"
#endif
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
}
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
#define __SADD8 __builtin_arm_sadd8
#define __QADD8 __builtin_arm_qadd8
#define __SHADD8 __builtin_arm_shadd8
#define __UADD8 __builtin_arm_uadd8
#define __UQADD8 __builtin_arm_uqadd8
#define __UHADD8 __builtin_arm_uhadd8
#define __SSUB8 __builtin_arm_ssub8
#define __QSUB8 __builtin_arm_qsub8
#define __SHSUB8 __builtin_arm_shsub8
#define __USUB8 __builtin_arm_usub8
#define __UQSUB8 __builtin_arm_uqsub8
#define __UHSUB8 __builtin_arm_uhsub8
#define __SADD16 __builtin_arm_sadd16
#define __QADD16 __builtin_arm_qadd16
#define __SHADD16 __builtin_arm_shadd16
#define __UADD16 __builtin_arm_uadd16
#define __UQADD16 __builtin_arm_uqadd16
#define __UHADD16 __builtin_arm_uhadd16
#define __SSUB16 __builtin_arm_ssub16
#define __QSUB16 __builtin_arm_qsub16
#define __SHSUB16 __builtin_arm_shsub16
#define __USUB16 __builtin_arm_usub16
#define __UQSUB16 __builtin_arm_uqsub16
#define __UHSUB16 __builtin_arm_uhsub16
#define __SASX __builtin_arm_sasx
#define __QASX __builtin_arm_qasx
#define __SHASX __builtin_arm_shasx
#define __UASX __builtin_arm_uasx
#define __UQASX __builtin_arm_uqasx
#define __UHASX __builtin_arm_uhasx
#define __SSAX __builtin_arm_ssax
#define __QSAX __builtin_arm_qsax
#define __SHSAX __builtin_arm_shsax
#define __USAX __builtin_arm_usax
#define __UQSAX __builtin_arm_uqsax
#define __UHSAX __builtin_arm_uhsax
#define __USAD8 __builtin_arm_usad8
#define __USADA8 __builtin_arm_usada8
#define __SSAT16 __builtin_arm_ssat16
#define __USAT16 __builtin_arm_usat16
#define __UXTB16 __builtin_arm_uxtb16
#define __UXTAB16 __builtin_arm_uxtab16
#define __SXTB16 __builtin_arm_sxtb16
#define __SXTAB16 __builtin_arm_sxtab16
#define __SMUAD __builtin_arm_smuad
#define __SMUADX __builtin_arm_smuadx
#define __SMLAD __builtin_arm_smlad
#define __SMLADX __builtin_arm_smladx
#define __SMLALD __builtin_arm_smlald
#define __SMLALDX __builtin_arm_smlaldx
#define __SMUSD __builtin_arm_smusd
#define __SMUSDX __builtin_arm_smusdx
#define __SMLSD __builtin_arm_smlsd
#define __SMLSDX __builtin_arm_smlsdx
#define __SMLSLD __builtin_arm_smlsld
#define __SMLSLDX __builtin_arm_smlsldx
#define __SEL __builtin_arm_sel
#define __QADD __builtin_arm_qadd
#define __QSUB __builtin_arm_qsub
#define __PKHBT(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
}
else
{
result = __SXTB16(__ROR(op1, rotate));
}
return result;
}
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
}
else
{
result = __SXTAB16(op1, __ROR(op2, rotate));
}
return result;
}
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return (result);
}
#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
/** @} end of group CMSIS_SIMD_intrinsics */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV %1, sp \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV sp, %1 \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
/* Permit access to VFP/NEON, registers by modifying CPACR */
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
/* Ensure that subsequent instructions occur in the context of VFP/NEON access permitted */
" ISB \n"
/* Enable VFP/NEON */
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
/* Initialise VFP/NEON registers to 0 */
" MOV R2,#0 \n"
/* Initialise D16 registers to 0 */
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
/* Initialise D32 registers to 0 */
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
/* Initialise FPSCR to a known state */
" VMRS R1,FPSCR \n"
" LDR R2,=0x00086060 \n" /* Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. */
" AND R1,R1,R2 \n"
" VMSR FPSCR,R1 "
: : : "cc", "r1", "r2"
);
}
#endif /* __CMSIS_ARMCLANG_A_H */

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/*
* Copyright (c) 2023-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(A) Compiler LLVM/Clang Header File
*/
#ifndef __CMSIS_CLANG_A_H
#define __CMSIS_CLANG_A_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_CLANG_H
#error "This file must not be included directly"
#endif
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
}
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
#define __SADD8 __builtin_arm_sadd8
#define __QADD8 __builtin_arm_qadd8
#define __SHADD8 __builtin_arm_shadd8
#define __UADD8 __builtin_arm_uadd8
#define __UQADD8 __builtin_arm_uqadd8
#define __UHADD8 __builtin_arm_uhadd8
#define __SSUB8 __builtin_arm_ssub8
#define __QSUB8 __builtin_arm_qsub8
#define __SHSUB8 __builtin_arm_shsub8
#define __USUB8 __builtin_arm_usub8
#define __UQSUB8 __builtin_arm_uqsub8
#define __UHSUB8 __builtin_arm_uhsub8
#define __SADD16 __builtin_arm_sadd16
#define __QADD16 __builtin_arm_qadd16
#define __SHADD16 __builtin_arm_shadd16
#define __UADD16 __builtin_arm_uadd16
#define __UQADD16 __builtin_arm_uqadd16
#define __UHADD16 __builtin_arm_uhadd16
#define __SSUB16 __builtin_arm_ssub16
#define __QSUB16 __builtin_arm_qsub16
#define __SHSUB16 __builtin_arm_shsub16
#define __USUB16 __builtin_arm_usub16
#define __UQSUB16 __builtin_arm_uqsub16
#define __UHSUB16 __builtin_arm_uhsub16
#define __SASX __builtin_arm_sasx
#define __QASX __builtin_arm_qasx
#define __SHASX __builtin_arm_shasx
#define __UASX __builtin_arm_uasx
#define __UQASX __builtin_arm_uqasx
#define __UHASX __builtin_arm_uhasx
#define __SSAX __builtin_arm_ssax
#define __QSAX __builtin_arm_qsax
#define __SHSAX __builtin_arm_shsax
#define __USAX __builtin_arm_usax
#define __UQSAX __builtin_arm_uqsax
#define __UHSAX __builtin_arm_uhsax
#define __USAD8 __builtin_arm_usad8
#define __USADA8 __builtin_arm_usada8
#define __SSAT16 __builtin_arm_ssat16
#define __USAT16 __builtin_arm_usat16
#define __UXTB16 __builtin_arm_uxtb16
#define __UXTAB16 __builtin_arm_uxtab16
#define __SXTB16 __builtin_arm_sxtb16
#define __SXTAB16 __builtin_arm_sxtab16
#define __SMUAD __builtin_arm_smuad
#define __SMUADX __builtin_arm_smuadx
#define __SMLAD __builtin_arm_smlad
#define __SMLADX __builtin_arm_smladx
#define __SMLALD __builtin_arm_smlald
#define __SMLALDX __builtin_arm_smlaldx
#define __SMUSD __builtin_arm_smusd
#define __SMUSDX __builtin_arm_smusdx
#define __SMLSD __builtin_arm_smlsd
#define __SMLSDX __builtin_arm_smlsdx
#define __SMLSLD __builtin_arm_smlsld
#define __SMLSLDX __builtin_arm_smlsldx
#define __SEL __builtin_arm_sel
#define __QADD __builtin_arm_qadd
#define __QSUB __builtin_arm_qsub
#define __PKHBT(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
}
else
{
result = __SXTB16(__ROR(op1, rotate));
}
return result;
}
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
}
else
{
result = __SXTAB16(op1, __ROR(op2, rotate));
}
return result;
}
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return (result);
}
#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
/** @} end of group CMSIS_SIMD_intrinsics */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV %1, sp \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV sp, %1 \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
/* Permit access to VFP/NEON, registers by modifying CPACR */
const uint32_t cpacr = __get_CPACR();
__set_CPACR(cpacr | 0x00F00000ul);
__ISB();
/* Enable VFP/NEON */
const uint32_t fpexc = __get_FPEXC();
__set_FPEXC(fpexc | 0x40000000ul);
__ASM volatile(
/* Initialise VFP/NEON registers to 0 */
" MOV R2,#0 \n"
/* Initialise D16 registers to 0 */
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
/* Initialise D32 registers to 0 */
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
: : : "cc", "r2"
);
/* Initialise FPSCR to a known state */
const uint32_t fpscr = __get_FPSCR();
__set_FPSCR(fpscr & 0x00086060ul);
}
/*@} end of group CMSIS_Core_intrinsics */
#pragma clang diagnostic pop
#endif /* __CMSIS_CLANG_A_H */

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/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions
*/
#ifndef __CMSIS_CP15_H
#define __CMSIS_CP15_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
/** \brief Get ACTLR
\return Auxiliary Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return(result);
}
/** \brief Set ACTLR
\param [in] actlr Auxiliary Control value to set
*/
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
{
__set_CP(15, 0, actlr, 1, 0, 1);
}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 2);
return result;
}
/** \brief Set CPACR
\param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
{
__set_CP(15, 0, cpacr, 1, 0, 2);
}
/** \brief Get DFSR
\return Data Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 0);
return result;
}
/** \brief Set DFSR
\param [in] dfsr Data Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
{
__set_CP(15, 0, dfsr, 5, 0, 0);
}
/** \brief Get IFSR
\return Instruction Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 1);
return result;
}
/** \brief Set IFSR
\param [in] ifsr Instruction Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
{
__set_CP(15, 0, ifsr, 5, 0, 1);
}
/** \brief Get ISR
\return Interrupt Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 1, 0);
return result;
}
/** \brief Get CBAR
\return Configuration Base Address register value
*/
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
{
uint32_t result;
__get_CP(15, 4, result, 15, 0, 0);
return result;
}
/** \brief Get TTBR0
This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
{
uint32_t result;
__get_CP(15, 0, result, 2, 0, 0);
return result;
}
/** \brief Set TTBR0
This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
{
__set_CP(15, 0, ttbr0, 2, 0, 0);
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 3, 0, 0);
return result;
}
/** \brief Set DACR
This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
{
__set_CP(15, 0, dacr, 3, 0, 0);
}
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register value to set
*/
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
{
__set_CP(15, 0, sctlr, 1, 0, 0);
}
/** \brief Get SCTLR
\return System Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 0);
return result;
}
/** \brief Get MPIDR
This function returns the value of the Multiprocessor Affinity Register.
\return Multiprocessor Affinity Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 5);
return result;
}
/** \brief Get VBAR
This function returns the value of the Vector Base Address Register.
\return Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 0);
return result;
}
/** \brief Set VBAR
This function assigns the given value to the Vector Base Address Register.
\param [in] vbar Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
{
__set_CP(15, 0, vbar, 12, 0, 0);
}
/** \brief Get MVBAR
This function returns the value of the Monitor Vector Base Address Register.
\return Monitor Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 1);
return result;
}
/** \brief Set MVBAR
This function assigns the given value to the Monitor Vector Base Address Register.
\param [in] mvbar Monitor Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
{
__set_CP(15, 0, mvbar, 12, 0, 1);
}
#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
defined(DOXYGEN)
/** \brief Set CNTFRQ
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\param [in] value CNTFRQ Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
{
__set_CP(15, 0, value, 14, 0, 0);
}
/** \brief Get CNTFRQ
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 0 , 0);
return result;
}
/** \brief Set CNTP_TVAL
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
\param [in] value CNTP_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 0);
}
/** \brief Get CNTP_TVAL
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
\return CNTP_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 0);
return result;
}
/** \brief Get CNTPCT
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
\return CNTPCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
{
uint64_t result;
__get_CP64(15, 0, result, 14);
return result;
}
/** \brief Set CNTP_CVAL
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\param [in] value CNTP_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
{
__set_CP64(15, 2, value, 14);
}
/** \brief Get CNTP_CVAL
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\return CNTP_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
{
uint64_t result;
__get_CP64(15, 2, result, 14);
return result;
}
/** \brief Set CNTP_CTL
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
\param [in] value CNTP_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 1);
}
/** \brief Get CNTP_CTL register
\return CNTP_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 1);
return result;
}
/******************************* VIRTUAL TIMER *******************************/
/** see [ARM DDI 0406C.d] :
. §B4.1.31 "CNTV_CTL, Counter-timer Virtual Timer Control register"
. §B4.1.32 "CNTV_CVAL, Counter-timer Virtual Timer CompareValue register"
. §B4.1.33 "CNTV_TVAL, Counter-timer Virtual Timer TimerValue register"
. §B4.1.34 "CNTVCT, Counter-timer Virtual Count register"
**/
/** \brief Set CNTV_TVAL
This function assigns the given value to VL1 Virtual Timer Value Register (CNTV_TVAL).
\param [in] value CNTV_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTV_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 3, 0);
}
/** \brief Get CNTV_TVAL
This function returns the value of the VL1 Virtual Timer Value Register (CNTV_TVAL).
\return CNTV_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTV_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 3, 0);
return result;
}
/** \brief Get CNTVCT
This function returns the value of the 64 bits VL1 Virtual Count Register (CNTVCT).
\return CNTVCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void)
{
uint64_t result;
__get_CP64(15, 1, result, 14);
return result;
}
/** \brief Set CNTV_CVAL
This function assigns the given value to 64bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL).
\param [in] value CNTV_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTV_CVAL(uint64_t value)
{
__set_CP64(15, 3, value, 14);
}
/** \brief Get CNTV_CVAL
This function returns the value of the 64 bits VL1 Virtual Timer CompareValue Register (CNTV_CVAL).
\return CNTV_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTV_CVAL(void)
{
uint64_t result;
__get_CP64(15, 3, result, 14);
return result;
}
/** \brief Set CNTV_CTL
This function assigns the given value to VL1 Virtual Timer Control Register (CNTV_CTL).
\param [in] value CNTV_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 3, 1);
}
/** \brief Get CNTV_CTL register
\return CNTV_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 3, 1);
return result;
}
/***************************** VIRTUAL TIMER END *****************************/
#endif
/** \brief Set TLBIALL
TLB Invalidate All
*/
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
{
__set_CP(15, 0, value, 8, 7, 0);
}
/** \brief Set BPIALL.
Branch Predictor Invalidate All
*/
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 6);
}
/** \brief Set ICIALLU
Instruction Cache Invalidate All
*/
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 0);
}
/** \brief Set ICIMVAC
Instruction Cache Invalidate
*/
__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 1);
}
/** \brief Set DCCMVAC
Data cache clean
*/
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCIMVAC
Data cache invalidate
*/
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCCIMVAC
Data cache clean and invalidate
*/
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set CSSELR
*/
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
{
__set_CP(15, 2, value, 0, 0, 0);
}
/** \brief Get CSSELR
\return CSSELR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
{
uint32_t result;
__get_CP(15, 2, result, 0, 0, 0);
return result;
}
/** \brief Get CCSIDR
\return CCSIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
{
uint32_t result;
__get_CP(15, 1, result, 0, 0, 0);
return result;
}
/** \brief Get CLIDR
\return CLIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
{
uint32_t result;
__get_CP(15, 1, result, 0, 0, 1);
return result;
}
/** \brief Set DCISW
*/
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 2);
}
/** \brief Set DCCSW
*/
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 2);
}
/** \brief Set DCCISW
*/
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 2);
}
#endif

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_A_H
#define __CMSIS_GCC_A_H
#ifndef __CMSIS_GCC_H
#error "This file must not be included directly"
#endif
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
Access to dedicated SIMD instructions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr = __get_CPSR();
uint32_t result;
__ASM volatile(
"CPS #0x1F \n"
"MOV %0, sp " : "=r"(result) : : "memory"
);
__set_CPSR(cpsr);
__ISB();
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr = __get_CPSR();
__ASM volatile(
"CPS #0x1F \n"
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
);
__set_CPSR(cpsr);
__ISB();
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
/* Permit access to VFP/NEON, registers by modifying CPACR */
const uint32_t cpacr = __get_CPACR();
__set_CPACR(cpacr | 0x00F00000ul);
__ISB();
/* Enable VFP/NEON */
const uint32_t fpexc = __get_FPEXC();
__set_FPEXC(fpexc | 0x40000000ul);
__ASM volatile(
/* Initialise VFP/NEON registers to 0 */
" MOV R2,#0 \n"
/* Initialise D16 registers to 0 */
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
/* Initialise D32 registers to 0 */
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
: : : "cc", "r2"
);
/* Initialise FPSCR to a known state */
const uint32_t fpscr = __get_FPSCR();
__set_FPSCR(fpscr & 0x00086060ul);
}
/*@} end of group CMSIS_Core_intrinsics */
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_A_H */

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/*
* Copyright (c) 2017-2018 IAR Systems
* Copyright (c) 2018-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File
*/
#ifndef __CMSIS_ICCARM_A_H__
#define __CMSIS_ICCARM_A_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#pragma language=extended
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_7A__
/* Macro already defined */
#else
#if defined(__ARM7A__)
#define __ARM_ARCH_7A__ 1
#endif
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_CPSR() (__arm_rsr("CPSR"))
#define __get_mode() (__get_CPSR() & 0x1FU)
#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
#define __get_FPEXC() (__arm_rsr("FPEXC"))
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#define __SSAT __iar_builtin_SSAT
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#define __USAT __iar_builtin_USAT
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
#define __get_FPSCR() (0)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __no_operation
#define __get_xPSR __get_PSR
__IAR_FT void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
__IAR_FT uint32_t __get_FPEXC(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
__IAR_FT void __set_FPEXC(uint32_t fpexc)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
__IAR_FT uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV %1, sp \n"
"MSR cpsr_c, %2 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
);
return result;
}
__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV sp, %1 \n"
"MSR cpsr_c, %2 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
);
}
#define __get_mode() (__get_CPSR() & 0x1FU)
__STATIC_INLINE
void __FPU_Enable(void)
{
__ASM volatile(
/* Permit access to VFP/NEON, registers by modifying CPACR */
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
/* Ensure that subsequent instructions occur in the context of VFP/NEON access permitted */
" ISB \n"
/* Enable VFP/NEON */
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
/* Initialise VFP/NEON registers to 0 */
" MOV R2,#0 \n"
/* Initialise D16 registers to 0 */
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#ifdef __ARM_ADVANCED_SIMD__
/* Initialise D32 registers to 0 */
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
/* Initialise FPSCR to a known state */
" VMRS R1,FPSCR \n"
" MOV32 R2,#0x00086060 \n" /* Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. */
" AND R1,R1,R2 \n"
" VMSR FPSCR,R1 \n"
: : : "cc", "r1", "r2"
);
}
#undef __IAR_FT
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_A_H__ */

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/*
* Copyright (c) 2017-2020 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(A) Interrupt Controller API Header File
*/
#ifndef IRQ_CTRL_H_
#define IRQ_CTRL_H_
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#include <stdint.h>
#ifndef IRQHANDLER_T
#define IRQHANDLER_T
/* / Interrupt handler data type */
typedef void (*IRQHandler_t) (void);
#endif
#ifndef IRQN_ID_T
#define IRQN_ID_T
/* / Interrupt ID number data type */
typedef int32_t IRQn_ID_t;
#endif
/* Interrupt mode bit-masks */
#define IRQ_MODE_TRIG_Pos (0U)
#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: level triggered interrupt */
#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: low level triggered interrupt */
#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: high level triggered interrupt */
#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: edge triggered interrupt */
#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: rising edge triggered interrupt */
#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: falling edge triggered interrupt */
#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) /* /< Trigger: rising and falling edge triggered interrupt */
#define IRQ_MODE_TYPE_Pos (3U)
#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) /* /< Type: interrupt source triggers CPU IRQ line */
#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) /* /< Type: interrupt source triggers CPU FIQ line */
#define IRQ_MODE_DOMAIN_Pos (4U)
#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) /* /< Domain: interrupt is targeting non-secure domain */
#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) /* /< Domain: interrupt is targeting secure domain */
#define IRQ_MODE_CPU_Pos (5U)
#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets all CPUs */
#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 0 */
#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 1 */
#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 2 */
#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 3 */
#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 4 */
#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 5 */
#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 6 */
#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) /* /< CPU: interrupt targets CPU 7 */
/* Encoding in some early GIC implementations */
#define IRQ_MODE_MODEL_Pos (13U)
#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos)
#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) /* /< Corresponding interrupt is handled using the N-N model */
#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) /* /< Corresponding interrupt is handled using the 1-N model */
#define IRQ_MODE_ERROR (0x80000000UL) /* /< Bit indicating mode value error */
/* Interrupt priority bit-masks */
#define IRQ_PRIORITY_Msk (0x0000FFFFUL) /* /< Interrupt priority value bit-mask */
#define IRQ_PRIORITY_ERROR (0x80000000UL) /* /< Bit indicating priority value error */
/* / Initialize interrupt controller. */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_Initialize (void);
/* / Register interrupt handler. */
/* / \param[in] irqn interrupt ID number */
/* / \param[in] handler interrupt handler function address */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
/* / Get the registered interrupt handler. */
/* / \param[in] irqn interrupt ID number */
/* / \return registered interrupt handler function address. */
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
/* / Enable interrupt. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_Enable (IRQn_ID_t irqn);
/* / Disable interrupt. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_Disable (IRQn_ID_t irqn);
/* / Get interrupt enable state. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 - interrupt is disabled, 1 - interrupt is enabled. */
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
/* / Configure interrupt request mode. */
/* / \param[in] irqn interrupt ID number */
/* / \param[in] mode mode configuration */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
/* / Get interrupt mode configuration. */
/* / \param[in] irqn interrupt ID number */
/* / \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. */
uint32_t IRQ_GetMode (IRQn_ID_t irqn);
/* / Get ID number of current interrupt request (IRQ). */
/* / \return interrupt ID number. */
IRQn_ID_t IRQ_GetActiveIRQ (void);
/* / Get ID number of current fast interrupt request (FIQ). */
/* / \return interrupt ID number. */
IRQn_ID_t IRQ_GetActiveFIQ (void);
/* / Signal end of interrupt processing. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
/* / Set interrupt pending flag. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetPending (IRQn_ID_t irqn);
/* / Get interrupt pending flag. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 - interrupt is not pending, 1 - interrupt is pending. */
uint32_t IRQ_GetPending (IRQn_ID_t irqn);
/* / Clear interrupt pending flag. */
/* / \param[in] irqn interrupt ID number */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_ClearPending (IRQn_ID_t irqn);
/* / Set interrupt priority value. */
/* / \param[in] irqn interrupt ID number */
/* / \param[in] priority interrupt priority value */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
/* / Get interrupt priority. */
/* / \param[in] irqn interrupt ID number */
/* / \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. */
uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
/* / Set priority masking threshold. */
/* / \param[in] priority priority masking threshold value */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetPriorityMask (uint32_t priority);
/* / Get priority masking threshold */
/* / \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. */
uint32_t IRQ_GetPriorityMask (void);
/* / Set priority grouping field split point */
/* / \param[in] bits number of MSB bits included in the group priority field comparison */
/* / \return 0 on success, -1 on error. */
int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
/* / Get priority grouping field split point */
/* / \return current number of MSB bits included in the group priority field comparison with */
/* / optional IRQ_PRIORITY_ERROR bit set. */
uint32_t IRQ_GetPriorityGroupBits (void);
#endif /* IRQ_CTRL_H_ */

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/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
* @version V6.0.0
* @date 27. July 2024
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCLANG_H
#define __CMSIS_ARMCLANG_H
#pragma clang system_header /* treat file as system include file */
#if (__ARM_ACLE >= 200)
#include <arm_acle.h>
#else
#error Compiler must support ACLE V2.0
#endif /* (__ARM_ACLE >= 200) */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_RW_REG(r) "+l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_RW_REG(r) "+r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP() __nop()
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI() __wfi()
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE() __wfe()
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV() __sev()
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV(value) __rev(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16(value) __rev16(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REVSH(value) __revsh(value)
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR(op1, op2) __ror(op1, op2)
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT(value) __rbit(value)
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ(value) __clz(value)
#if ((__ARM_FEATURE_SAT >= 1) && \
(__ARM_ARCH_ISA_THUMB >= 2) )
/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(value, sat) __ssat(value, sat)
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(value, sat) __usat(value, sat)
#else /* (__ARM_FEATURE_SAT >= 1) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return (max);
}
else if (val < min)
{
return (min);
}
}
return (val);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return (max);
}
else if (val < 0)
{
return (0U);
}
}
return ((uint32_t)val);
}
#endif /* (__ARM_FEATURE_SAT >= 1) */
#if (__ARM_FEATURE_LDREX >= 1)
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 1) */
#if (__ARM_FEATURE_LDREX >= 2)
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 2) */
#if (__ARM_FEATURE_LDREX >= 4)
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 4) */
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
return (result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t)result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t)result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return (result);
}
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
#if (__ARM_ARCH >= 8)
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return ((uint8_t)result); /* Add explicit type cast here */
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return ((uint16_t)result); /* Add explicit type cast here */
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return (result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDAEX (uint32_t)__builtin_arm_ldaex
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXB (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXH (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEX (uint32_t)__builtin_arm_stlex
#endif /* (__ARM_ARCH >= 8) */
/** @}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
#ifndef __ARM_COMPAT_H
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
#endif
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
#ifndef __ARM_COMPAT_H
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
#endif
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if (defined(__ARM_FP) && (__ARM_FP >= 1))
return (__builtin_arm_get_fpscr());
#else
return (0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if (defined(__ARM_FP) && (__ARM_FP >= 1))
__builtin_arm_set_fpscr(fpscr);
#else
(void)fpscr;
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/* Include the profile specific settings: */
#if __ARM_ARCH_PROFILE == 'A'
#include "./a-profile/cmsis_armclang_a.h"
#elif __ARM_ARCH_PROFILE == 'R'
#include "./r-profile/cmsis_armclang_r.h"
#elif __ARM_ARCH_PROFILE == 'M'
#include "./m-profile/cmsis_armclang_m.h"
#else
#error "Unknown Arm architecture profile"
#endif
#endif /* __CMSIS_ARMCLANG_H */

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/**************************************************************************//**
* @file cmsis_clang.h
* @brief CMSIS compiler LLVM/Clang header file
* @version V6.0.0
* @date 27. July 2024
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_CLANG_H
#define __CMSIS_CLANG_H
#pragma clang system_header /* treat file as system include file */
#if (__ARM_ACLE >= 200)
#include <arm_acle.h>
#else
#error Compiler must support ACLE V2.0
#endif /* (__ARM_ACLE >= 200) */
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constraint "l"
* Otherwise, use general registers, specified by constraint "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_RW_REG(r) "+l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_RW_REG(r) "+r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP() __nop()
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI() __wfi()
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE() __wfe()
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV() __sev()
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV(value) __rev(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16(value) __rev16(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REVSH(value) __revsh(value)
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR(op1, op2) __ror(op1, op2)
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT(value) __rbit(value)
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ(value) __clz(value)
#if ((__ARM_FEATURE_SAT >= 1) && \
(__ARM_ARCH_ISA_THUMB >= 2) )
/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(value, sat) __ssat(value, sat)
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(value, sat) __usat(value, sat)
#else /* (__ARM_FEATURE_SAT >= 1) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return (max);
}
else if (val < min)
{
return (min);
}
}
return (val);
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return (max);
}
else if (val < 0)
{
return (0U);
}
}
return ((uint32_t)val);
}
#endif /* (__ARM_FEATURE_SAT >= 1) */
#if (__ARM_FEATURE_LDREX >= 1)
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 1) */
#if (__ARM_FEATURE_LDREX >= 2)
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 2) */
#if (__ARM_FEATURE_LDREX >= 4)
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
#endif /* (__ARM_FEATURE_LDREX >= 4) */
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
return (result);
}
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint8_t)result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
return ((uint16_t)result); /* Add explicit type cast here */
}
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
return (result);
}
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
#if (__ARM_ARCH >= 8)
/**
\brief Load-Acquire (8 bit)
\details Executes a LDAB instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t result;
__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return ((uint8_t)result); /* Add explicit type cast here */
}
/**
\brief Load-Acquire (16 bit)
\details Executes a LDAH instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t result;
__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return ((uint16_t)result); /* Add explicit type cast here */
}
/**
\brief Load-Acquire (32 bit)
\details Executes a LDA instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t result;
__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
return (result);
}
/**
\brief Store-Release (8 bit)
\details Executes a STLB instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Store-Release (16 bit)
\details Executes a STLH instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Store-Release (32 bit)
\details Executes a STL instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
}
/**
\brief Load-Acquire Exclusive (8 bit)
\details Executes a LDAB exclusive instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDAEXB (uint8_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (16 bit)
\details Executes a LDAH exclusive instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDAEXH (uint16_t)__builtin_arm_ldaex
/**
\brief Load-Acquire Exclusive (32 bit)
\details Executes a LDA exclusive instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDAEX (uint32_t)__builtin_arm_ldaex
/**
\brief Store-Release Exclusive (8 bit)
\details Executes a STLB exclusive instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXB (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (16 bit)
\details Executes a STLH exclusive instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEXH (uint32_t)__builtin_arm_stlex
/**
\brief Store-Release Exclusive (32 bit)
\details Executes a STL exclusive instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STLEX (uint32_t)__builtin_arm_stlex
#endif /* (__ARM_ARCH >= 8) */
/** @}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
#endif
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if (defined(__ARM_FP) && (__ARM_FP >= 1))
return (__builtin_arm_get_fpscr());
#else
return (0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if (defined(__ARM_FP) && (__ARM_FP >= 1))
__builtin_arm_set_fpscr(fpscr);
#else
(void)fpscr;
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/* Include the profile specific settings: */
#if __ARM_ARCH_PROFILE == 'A'
#include "./a-profile/cmsis_clang_a.h"
#elif __ARM_ARCH_PROFILE == 'R'
#include "./r-profile/cmsis_clang_r.h"
#elif __ARM_ARCH_PROFILE == 'M'
#include "./m-profile/cmsis_clang_m.h"
#else
#error "Unknown Arm architecture profile"
#endif
#endif /* __CMSIS_CLANG_H */

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/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS Compiler Generic Header File
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* TI Arm Clang Compiler (tiarmclang)
*/
#elif defined (__ti__)
#include "cmsis_tiarmclang.h"
/*
* LLVM/Clang Compiler
*/
#elif defined ( __clang__ )
#include "cmsis_clang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#if __ARM_ARCH_PROFILE == 'A'
#include "a-profile/cmsis_iccarm_a.h"
#elif __ARM_ARCH_PROFILE == 'R'
#include "r-profile/cmsis_iccarm_r.h"
#elif __ARM_ARCH_PROFILE == 'M'
#include "m-profile/cmsis_iccarm_m.h"
#else
#error "Unknown Arm architecture profile"
#endif
/*
* TI Arm Compiler (armcl)
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
/* NO RETURN is automatically detected hence no warning here */
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#ifndef __NO_INIT
#define __NO_INIT __attribute__ ((section (".noinit")))
#endif
#ifndef __ALIAS
#define __ALIAS(x) __attribute__ ((alias(x)))
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/*
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS Core Version Definitions
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS-Core(M) Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */
/* CMSIS-Core(A) Version definitions */
#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */
#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
__CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
#endif

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS Cortex-M0 Core Peripheral Access Layer Header File
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined (__ARM_FP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ti__)
#if defined (__ARM_FP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined (__ARMVFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined (__TI_VFP_SUPPORT__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined (__FPU_VFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/** \brief CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/** \brief SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/** \brief SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/** \brief SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/** \brief SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/** \brief SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/** \brief SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/** \brief SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/** \brief SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/** \brief SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/**
\defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
\brief Alias definitions present for backwards compatibility for deprecated symbols.
@{
*/
#ifndef CMSIS_DISABLE_DEPRECATED
#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
#endif /* CMSIS_DISABLE_DEPRECATED */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/* NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS Cortex-M1 Core Peripheral Access Layer Header File
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#elif defined ( __GNUC__ )
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined (__TARGET_FPU_VFP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined (__ARM_FP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ti__)
#if defined (__ARM_FP)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined (__ARMVFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined (__TI_VFP_SUPPORT__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined (__FPU_VFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/** \brief CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RESERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/** \brief SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/** \brief SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/** \brief SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/** \brief SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/** \brief SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/** \brief SCnSCB Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/** \brief SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/** \brief SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/** \brief SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/** \brief SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/**
\defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
\brief Alias definitions present for backwards compatibility for deprecated symbols.
@{
*/
#ifndef CMSIS_DISABLE_DEPRECATED
#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
#endif /* CMSIS_DISABLE_DEPRECATED */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) Level 1 Cache API for Armv7-M and later
*/
#ifndef ARM_ARMV7M_CACHEL1_H
#define ARM_ARMV7M_CACHEL1_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 )
{
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
struct {
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
} locals
#if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
__ALIGNED(__SCB_DCACHE_LINE_SIZE)
#endif
;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
#if !defined(__OPTIMIZE__)
/*
* For the endless loop issue with no optimization builds.
* More details, see https://github.com/ARM-software/CMSIS_5/issues/620
*
* The issue only happens when local variables are in stack. If
* local variables are saved in general purpose register, then the function
* is OK.
*
* When local variables are in stack, after disabling the cache, flush the
* local variables cache line for data consistency.
*/
/* Clean and invalidate the local variable cache. */
#if defined(__ICCARM__)
/* As we can't align the stack to the cache line size, invalidate each of the variables */
SCB->DCCIMVAC = (uint32_t)&locals.sets;
SCB->DCCIMVAC = (uint32_t)&locals.ways;
SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
#else
SCB->DCCIMVAC = (uint32_t)&locals;
#endif
__DSB();
__ISB();
#endif
locals.ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
do {
locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
do {
SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (locals.ways-- != 0U);
} while(locals.sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_ARMV7M_CACHEL1_H */

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/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) MPU API for Armv7-M MPU
*/
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) /* /!< MPU Region Size 32 Bytes */
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) /* /!< MPU Region Size 64 Bytes */
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) /* /!< MPU Region Size 128 Bytes */
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) /* /!< MPU Region Size 256 Bytes */
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) /* /!< MPU Region Size 512 Bytes */
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /* /!< MPU Region Size 1 KByte */
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /* /!< MPU Region Size 2 KBytes */
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /* /!< MPU Region Size 4 KBytes */
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /* /!< MPU Region Size 8 KBytes */
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /* /!< MPU Region Size 16 KBytes */
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /* /!< MPU Region Size 32 KBytes */
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /* /!< MPU Region Size 64 KBytes */
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /* /!< MPU Region Size 128 KBytes */
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /* /!< MPU Region Size 256 KBytes */
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /* /!< MPU Region Size 512 KBytes */
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /* /!< MPU Region Size 1 MByte */
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /* /!< MPU Region Size 2 MBytes */
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /* /!< MPU Region Size 4 MBytes */
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /* /!< MPU Region Size 8 MBytes */
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /* /!< MPU Region Size 16 MBytes */
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /* /!< MPU Region Size 32 MBytes */
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /* /!< MPU Region Size 64 MBytes */
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /* /!< MPU Region Size 128 MBytes */
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /* /!< MPU Region Size 256 MBytes */
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /* /!< MPU Region Size 512 MBytes */
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /* /!< MPU Region Size 1 GByte */
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /* /!< MPU Region Size 2 GBytes */
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /* /!< MPU Region Size 4 GBytes */
#define ARM_MPU_AP_NONE 0U /* /!< MPU Access Permission no access */
#define ARM_MPU_AP_PRIV 1U /* /!< MPU Access Permission privileged access only */
#define ARM_MPU_AP_URO 2U /* /!< MPU Access Permission unprivileged access read-only */
#define ARM_MPU_AP_FULL 3U /* /!< MPU Access Permission full access */
#define ARM_MPU_AP_PRO 5U /* /!< MPU Access Permission privileged access read-only */
#define ARM_MPU_AP_RO 6U /* /!< MPU Access Permission read-only access */
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /* !< The region base address register value (RBAR) */
uint32_t RASR; /* !< The region attribute and size register value (RASR) \ref MPU_RASR */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES)
{
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/*
* Copyright (c) 2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension
*/
#ifndef PAC_ARMV81_H
#define PAC_ARMV81_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
/* ################### PAC Key functions ########################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
\brief Functions that access the PAC keys.
@{
*/
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
/**
\brief read the PAC key used for privileged mode
\details Reads the PAC key stored in the PAC_KEY_P registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey)
{
__ASM volatile (
"mrs r1, pac_key_p_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode
\details writes the given PAC key to the PAC_KEY_P registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey)
{
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode
\details Reads the PAC key stored in the PAC_KEY_U registers.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey)
{
__ASM volatile (
"mrs r1, pac_key_u_0\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode
\details writes the given PAC key to the PAC_KEY_U registers.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey)
{
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
/**
\brief read the PAC key used for privileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey)
{
__ASM volatile (
"mrs r1, pac_key_p_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_p_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_p_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_p_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for privileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey)
{
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_p_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_p_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_p_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_p_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief read the PAC key used for unprivileged mode (non-secure)
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
\param [out] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey)
{
__ASM volatile (
"mrs r1, pac_key_u_0_ns\n"
"str r1,[%0,#0]\n"
"mrs r1, pac_key_u_1_ns\n"
"str r1,[%0,#4]\n"
"mrs r1, pac_key_u_2_ns\n"
"str r1,[%0,#8]\n"
"mrs r1, pac_key_u_3_ns\n"
"str r1,[%0,#12]\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
/**
\brief write the PAC key used for unprivileged mode (non-secure)
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
\param [in] pPacKey 128bit PAC key
*/
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey)
{
__ASM volatile (
"ldr r1,[%0,#0]\n"
"msr pac_key_u_0_ns, r1\n"
"ldr r1,[%0,#4]\n"
"msr pac_key_u_1_ns, r1\n"
"ldr r1,[%0,#8]\n"
"msr pac_key_u_2_ns, r1\n"
"ldr r1,[%0,#12]\n"
"msr pac_key_u_3_ns, r1\n"
: : "r" (pPacKey) : "memory", "r1"
);
}
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
/*@} end of CMSIS_Core_PacKeyFunctions */
#endif /* PAC_ARMV81_H */

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/*
* Copyright (c) 2017-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU
*/
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for Normal memory, Outer and Inner cacheability.
* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Normal memory outer-cacheable and inner-cacheable attributes
* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
*/
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/* \brief Specifies MAIR_ATTR number */
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
/**
* Shareability
*/
/** \brief Normal memory, non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory, outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory, inner shareable */
#define ARM_MPU_SH_INNER (3U)
/**
* Access permissions
* AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
*/
/** \brief Normal memory, read/write */
#define ARM_MPU_AP_RW (0U)
/** \brief Normal memory, read-only */
#define ARM_MPU_AP_RO (1U)
/** \brief Normal memory, any privilege level */
#define ARM_MPU_AP_NP (1U)
/** \brief Normal memory, privileged access only */
#define ARM_MPU_AP_PO (0U)
/*
* Execute-never
* XN = Execute-never, EX = Executable
*/
/** \brief Normal memory, Execution only permitted if read permitted */
#define ARM_MPU_XN (1U)
/** \brief Normal memory, Execution only permitted if read permitted */
#define ARM_MPU_EX (0U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/**
\brief Read MPU Type Register
\return Number of MPU regions
*/
__STATIC_INLINE uint32_t ARM_MPU_TYPE()
{
return ((MPU->TYPE) >> 8);
}
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0])))
{
return; /* invalid index */
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U)
{
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES)
{
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) PMU API for Armv8.1-M PMU
*/
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File
*/
#ifndef __CMSIS_ARMCLANG_M_H
#define __CMSIS_ARMCLANG_M_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_ARMCLANG_H
#error "This file must not be included directly"
#endif
#if (__ARM_ACLE >= 200)
#include <arm_acle.h>
#else
#error Compiler must support ACLE V2.0
#endif /* (__ARM_ACLE >= 200) */
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START __main
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
#endif
#if (__ARM_FEATURE_CMSE == 3)
#ifndef __STACK_SEAL
#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
#endif
#ifndef __TZ_STACK_SEAL_SIZE
#define __TZ_STACK_SEAL_SIZE 8U
#endif
#ifndef __TZ_STACK_SEAL_VALUE
#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
__ISB();
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
__ISB();
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return (result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return (result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return (result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return (result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
#if (__ARM_ARCH >= 8)
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return (result);
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return (result);
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* (__ARM_ARCH >= 8) */
/** @} end of CMSIS_Core_RegAccFunctions */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return (result);
}
#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
/** @} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCLANG_M_H */

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/*
* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) Compiler LLVM/Clang Header File
*/
#ifndef __CMSIS_CLANG_M_H
#define __CMSIS_CLANG_M_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_CLANG_H
#error "This file must not be included directly"
#endif
#if (__ARM_ACLE >= 200)
#include <arm_acle.h>
#else
#error Compiler must support ACLE V2.0
#endif /* (__ARM_ACLE >= 200) */
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
#define __PROGRAM_START _start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP __stack
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT __stack_limit
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
#endif
#if (__ARM_FEATURE_CMSE == 3)
#ifndef __STACK_SEAL
#define __STACK_SEAL __stack_seal
#endif
#ifndef __TZ_STACK_SEAL_SIZE
#define __TZ_STACK_SEAL_SIZE 8U
#endif
#ifndef __TZ_STACK_SEAL_VALUE
#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
__ISB();
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
__ISB();
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return (result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return (result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return (result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return (result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return (result);
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
#if (__ARM_ARCH >= 8)
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return (result);
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return (result);
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
(__ARM_FEATURE_CMSE < 3) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
(__ARM_ARCH_8_1M_MAIN__ < 1) )
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* (__ARM_ARCH >= 8) */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return (result);
}
#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
/** @} end of group CMSIS_SIMD_intrinsics */
/** @} end of CMSIS_Core_RegAccFunctions */
#endif /* __CMSIS_CLANG_M_H */

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/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS-Core(M) Compiler GCC Header File
*/
#ifndef __CMSIS_GCC_M_H
#define __CMSIS_GCC_M_H
#ifndef __CMSIS_GCC_H
#error "This file must not be included directly"
#endif
#include <arm_acle.h>
/* ######################### Startup and Lowlevel Init ######################## */
#ifndef __PROGRAM_START
/**
\brief Initializes data and bss sections
\details This default implementations initialized all data and additional bss
sections relying on .copy.table and .zero.table specified properly
in the used linker script.
*/
__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
{
extern void _start(void) __NO_RETURN;
typedef struct __copy_table {
uint32_t const* src;
uint32_t* dest;
uint32_t wlen;
} __copy_table_t;
typedef struct __zero_table {
uint32_t* dest;
uint32_t wlen;
} __zero_table_t;
extern const __copy_table_t __copy_table_start__;
extern const __copy_table_t __copy_table_end__;
extern const __zero_table_t __zero_table_start__;
extern const __zero_table_t __zero_table_end__;
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = pTable->src[i];
}
}
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = 0u;
}
}
_start();
}
#define __PROGRAM_START __cmsis_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP __StackTop
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT __StackLimit
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __Vectors
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
#ifndef __STACK_SEAL
#define __STACK_SEAL __StackSeal
#endif
#ifndef __TZ_STACK_SEAL_SIZE
#define __TZ_STACK_SEAL_SIZE 8U
#endif
#ifndef __TZ_STACK_SEAL_VALUE
#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Control Register (non-secure)
\details Returns the content of the non-secure Control Register when in secure mode.
\return non-secure Control Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
__ISB();
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Control Register (non-secure)
\details Writes the given value to the non-secure Control Register when in secure state.
\param [in] control Control Register value to set
*/
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
__ISB();
}
#endif
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return (result);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return (result);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return (result);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer (non-secure)
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
\return PSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
}
#endif
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSP(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer (non-secure)
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
\return MSP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
}
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Stack Pointer (non-secure)
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
\return SP Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
return (result);
}
/**
\brief Set Stack Pointer (non-secure)
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
\param [in] topOfStack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
{
__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
}
#endif
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Priority Mask (non-secure)
\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
\return Priority Mask value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Priority Mask (non-secure)
\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
{
__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
}
#endif
#if (__ARM_ARCH_ISA_THUMB >= 2)
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Base Priority (non-secure)
\details Returns the current value of the non-secure Base Priority register when in secure state.
\return Base Priority register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
{
__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Base Priority (non-secure)
\details Assigns the given value to the non-secure Base Priority register when in secure state.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
{
__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
}
#endif
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return (result);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Fault Mask (non-secure)
\details Returns the current value of the non-secure Fault Mask register when in secure state.
\return Fault Mask register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
return (result);
}
#endif
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Fault Mask (non-secure)
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
}
#endif
#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
#if (__ARM_ARCH >= 8)
/**
\brief Get Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always in non-secure
mode.
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
return (result);
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Process Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\return PSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Process Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored in non-secure
mode.
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Process Stack Pointer (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
#endif
}
#endif
/**
\brief Get Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
return (result);
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Get Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence zero is returned always.
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
\return MSPLIM Register value
*/
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
return (0U);
#else
uint32_t result;
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
return (result);
#endif
}
#endif
/**
\brief Set Main Stack Pointer Limit
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
*/
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
#endif
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
/**
\brief Set Main Stack Pointer Limit (non-secure)
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
Stack Pointer Limit register hence the write is silently ignored.
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
\param [in] MainStackPtrLimit Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
#endif
}
#endif
#endif /* (__ARM_ARCH >= 8) */
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CMSIS_GCC_M_H */

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/**************************************************************************//**
* @file cmsis_armclang_r.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
* @version V6.0.0
* @date 04. December 2024
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCLANG_R_H
#define __CMSIS_ARMCLANG_R_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_ARMCLANG_H
#error "This file must not be included directly"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV %1, sp \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV sp, %1 \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#endif /* __CMSIS_ARMCLANG_R_H */

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/**************************************************************************//**
* @file cmsis_clang_r.h
* @brief CMSIS compiler armclang (Arm Compiler 6) header file
* @version V6.0.0
* @date 04. December 2024
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_CLANG_CORER_H
#define __CMSIS_CLANG_CORER_H
#pragma clang system_header /* treat file as system include file */
#ifndef __CMSIS_CLANG_H
#error "This file must not be included directly"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV %1, sp \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" /* no effect in USR mode */
"MOV sp, %1 \n"
"MSR cpsr_c, %0 \n" /* no effect in USR mode */
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/** @} end of CMSIS_Core_RegAccFunctions */
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#endif /* __CMSIS_CLANG_COREA_H */

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/**************************************************************************//**
* @file cmsis_gcc_r.h
* @brief CMSIS compiler GCC header file
* @version V6.0.0
* @date 4. August 2024
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_R_H
#define __CMSIS_GCC_R_H
#ifndef __CMSIS_GCC_H
#error "This file must not be included directly"
#endif
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
Access to dedicated SIMD instructions
@{
*/
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr = __get_CPSR();
uint32_t result;
__ASM volatile(
"CPS #0x1F \n"
"MOV %0, sp " : "=r"(result) : : "memory"
);
__set_CPSR(cpsr);
__ISB();
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr = __get_CPSR();
__ASM volatile(
"CPS #0x1F \n"
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
);
__set_CPSR(cpsr);
__ISB();
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
/*@} end of group CMSIS_Core_intrinsics */
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_R_H */

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/*
* Copyright (c) 2017-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* CMSIS Core(M) Context Management for Armv8-M TrustZone
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/* / \details Data type that identifies secure software modules called by a process. */
typedef uint32_t TZ_ModuleId_t;
#endif
/* / \details TZ Memory ID identifies an allocated memory slot. */
typedef uint32_t TZ_MemoryId_t;
/* / Initialize secure context memory system */
/* / \return execution status (1: success, 0: error) */
uint32_t TZ_InitContextSystem_S (void);
/* / Allocate context memory for calling secure software modules in TrustZone */
/* / \param[in] module identifies software modules called from non-secure mode */
/* / \return value != 0 id TrustZone memory slot identifier */
/* / \return value 0 no memory available or internal error */
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/* / Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S */
/* / \param[in] id TrustZone memory slot identifier */
/* / \return execution status (1: success, 0: error) */
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/* / Load secure context (called on RTOS thread context switch) */
/* / \param[in] id TrustZone memory slot identifier */
/* / \return execution status (1: success, 0: error) */
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/* / Store secure context (called on RTOS thread context switch) */
/* / \param[in] id TrustZone memory slot identifier */
/* / \return execution status (1: success, 0: error) */
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif /* TZ_CONTEXT_H */

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48
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @ingroup BOARDS
* @defgroup BOARD_RA4E2_FPB for the RA4E2-FPB board
* @brief BSP for the RA4E2-FPB Board
*
* The RA4E2_FPB is a development kit for the Renesas R7FA4E2B93CFM microcontroller in a LQFP64 package.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_H
#define BOARD_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP Board Specific Includes. */
#include "board_init.h"
#include "board_leds.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BOARD_RA4E2_FPB
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end defgroup BOARD_RA4E2_FPB) */
#endif

49
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA4E2_FPB
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RA4E2_FPB)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Performs any initialization specific to this BSP.
*
* @param[in] p_args Pointer to arguments of the user's choice.
**********************************************************************************************************************/
void bsp_init (void * p_args)
{
FSP_PARAMETER_NOT_USED(p_args);
}
#endif
/** @} (end addtogroup BOARD_RA4E2_FPB) */

45
bsp/renesas/ra4e2-eco/ra/board/ra4e2_fpb/board_init.h Normal file
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA4E2_FPB
* @brief Board specific code for the RA4E2-FPB Board
*
* This include file is specific to the RA4E2-FPB board.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_INIT_H
#define BOARD_INIT_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void bsp_init(void * p_args);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end addtogroup BOARD_RA4E2_FPB) */

57
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RA4E2_FPB_LEDS
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RA4E2_FPB)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Array of LED IOPORT pins. */
static const uint16_t g_bsp_prv_leds[] =
{
(uint16_t) BSP_IO_PORT_02_PIN_07, /* /< LED1 */
(uint16_t) BSP_IO_PORT_02_PIN_06, /* /< LED2 */
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** Structure with LED information for this board. */
const bsp_leds_t g_bsp_leds =
{
.led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
.p_leds = &g_bsp_prv_leds[0]
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#endif
/** @} (end addtogroup BOARD_RA4E2_FPB_LEDS) */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @ingroup BOARD_RA4E2_FPB
* @defgroup BOARD_RA4E2_FPB_LEDS Board LEDs
* @brief LED information for this board.
*
* This is code specific to the FPB board. It includes info on the number of LEDs and which pins are they
* are on.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_LEDS_H
#define BOARD_LEDS_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Information on how many LEDs and what pins they are on. */
typedef struct st_bsp_leds
{
uint16_t led_count; /* /< The number of LEDs on this board */
uint16_t const * p_leds; /* /< Pointer to an array of IOPORT pins for controlling LEDs */
} bsp_leds_t;
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
* found in the bsp_leds_t structure. */
typedef enum e_bsp_led
{
BSP_LED_LED1, /* /< LED1 */
BSP_LED_LED2, /* /< LED2 */
} bsp_led_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RA4E2_FPB_LEDS) */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic push
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "../../src/bsp/mcu/all/bsp_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
#if defined(BSP_API_OVERRIDE)
#include BSP_API_OVERRIDE
#else
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
#if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h")
#include "../../src/bsp/mcu/all/internal/bsp_internal.h"
#endif
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSP_COMMON_API_H
#define FSP_COMMON_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <assert.h>
#include <stdint.h>
/* Includes FSP version macros. */
#include "fsp_version.h"
/*******************************************************************************************************************//**
* @ingroup RENESAS_COMMON
* @defgroup RENESAS_ERROR_CODES Common Error Codes
* All FSP modules share these common error codes.
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
* about using this implementation is that it does not take any extra RAM or ROM. */
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
/** Determine if a C++ compiler is being used.
* If so, ensure that standard C is used to process the API information. */
#if defined(__cplusplus)
#define FSP_CPP_HEADER extern "C" {
#define FSP_CPP_FOOTER }
#else
#define FSP_CPP_HEADER
#define FSP_CPP_FOOTER
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
#define FSP_SECURE_ARGUMENT (NULL)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Common error codes */
typedef enum e_fsp_err
{
FSP_SUCCESS = 0,
FSP_ERR_ASSERTION = 1, /* /< A critical assertion has failed */
FSP_ERR_INVALID_POINTER = 2, /* /< Pointer points to invalid memory location */
FSP_ERR_INVALID_ARGUMENT = 3, /* /< Invalid input parameter */
FSP_ERR_INVALID_CHANNEL = 4, /* /< Selected channel does not exist */
FSP_ERR_INVALID_MODE = 5, /* /< Unsupported or incorrect mode */
FSP_ERR_UNSUPPORTED = 6, /* /< Selected mode not supported by this API */
FSP_ERR_NOT_OPEN = 7, /* /< Requested channel is not configured or API not open */
FSP_ERR_IN_USE = 8, /* /< Channel/peripheral is running/busy */
FSP_ERR_OUT_OF_MEMORY = 9, /* /< Allocate more memory in the driver's cfg.h */
FSP_ERR_HW_LOCKED = 10, /* /< Hardware is locked */
FSP_ERR_IRQ_BSP_DISABLED = 11, /* /< IRQ not enabled in BSP */
FSP_ERR_OVERFLOW = 12, /* /< Hardware overflow */
FSP_ERR_UNDERFLOW = 13, /* /< Hardware underflow */
FSP_ERR_ALREADY_OPEN = 14, /* /< Requested channel is already open in a different configuration */
FSP_ERR_APPROXIMATION = 15, /* /< Could not set value to exact result */
FSP_ERR_CLAMPED = 16, /* /< Value had to be limited for some reason */
FSP_ERR_INVALID_RATE = 17, /* /< Selected rate could not be met */
FSP_ERR_ABORTED = 18, /* /< An operation was aborted */
FSP_ERR_NOT_ENABLED = 19, /* /< Requested operation is not enabled */
FSP_ERR_TIMEOUT = 20, /* /< Timeout error */
FSP_ERR_INVALID_BLOCKS = 21, /* /< Invalid number of blocks supplied */
FSP_ERR_INVALID_ADDRESS = 22, /* /< Invalid address supplied */
FSP_ERR_INVALID_SIZE = 23, /* /< Invalid size/length supplied for operation */
FSP_ERR_WRITE_FAILED = 24, /* /< Write operation failed */
FSP_ERR_ERASE_FAILED = 25, /* /< Erase operation failed */
FSP_ERR_INVALID_CALL = 26, /* /< Invalid function call is made */
FSP_ERR_INVALID_HW_CONDITION = 27, /* /< Detected hardware is in invalid condition */
FSP_ERR_INVALID_FACTORY_FLASH = 28, /* /< Factory flash is not available on this MCU */
FSP_ERR_INVALID_STATE = 30, /* /< API or command not valid in the current state */
FSP_ERR_NOT_ERASED = 31, /* /< Erase verification failed */
FSP_ERR_SECTOR_RELEASE_FAILED = 32, /* /< Sector release failed */
FSP_ERR_NOT_INITIALIZED = 33, /* /< Required initialization not complete */
FSP_ERR_NOT_FOUND = 34, /* /< The requested item could not be found */
FSP_ERR_NO_CALLBACK_MEMORY = 35, /* /< Non-secure callback memory not provided for non-secure callback */
FSP_ERR_BUFFER_EMPTY = 36, /* /< No data available in buffer */
FSP_ERR_INVALID_DATA = 37, /* /< Accuracy of data is not guaranteed */
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, /* /< Internal error */
FSP_ERR_WAIT_ABORTED = 101, /* /< Wait aborted */
/* Start of UART specific */
FSP_ERR_FRAMING = 200, /* /< Framing error occurs */
FSP_ERR_BREAK_DETECT = 201, /* /< Break signal detects */
FSP_ERR_PARITY = 202, /* /< Parity error occurs */
FSP_ERR_RXBUF_OVERFLOW = 203, /* /< Receive queue overflow */
FSP_ERR_QUEUE_UNAVAILABLE = 204, /* /< Can't open s/w queue */
FSP_ERR_INSUFFICIENT_SPACE = 205, /* /< Not enough space in transmission circular buffer */
FSP_ERR_INSUFFICIENT_DATA = 206, /* /< Not enough data in receive circular buffer */
/* Start of SPI specific */
FSP_ERR_TRANSFER_ABORTED = 300, /* /< The data transfer was aborted. */
FSP_ERR_MODE_FAULT = 301, /* /< Mode fault error. */
FSP_ERR_READ_OVERFLOW = 302, /* /< Read overflow. */
FSP_ERR_SPI_PARITY = 303, /* /< Parity error. */
FSP_ERR_OVERRUN = 304, /* /< Overrun error. */
/* Start of CGC Specific */
FSP_ERR_CLOCK_INACTIVE = 400, /* /< Inactive clock specified as system clock. */
FSP_ERR_CLOCK_ACTIVE = 401, /* /< Active clock source cannot be modified without stopping first. */
FSP_ERR_NOT_STABILIZED = 403, /* /< Clock has not stabilized after its been turned on/off */
FSP_ERR_PLL_SRC_INACTIVE = 404, /* /< PLL initialization attempted when PLL source is turned off */
FSP_ERR_OSC_STOP_DET_ENABLED = 405, /* /< Illegal attempt to stop LOCO when Oscillation stop is enabled */
FSP_ERR_OSC_STOP_DETECTED = 406, /* /< The Oscillation stop detection status flag is set */
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, /* /< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active */
FSP_ERR_CLKOUT_EXCEEDED = 408, /* /< Output on target output clock pin exceeds maximum supported limit */
FSP_ERR_USB_MODULE_ENABLED = 409, /* /< USB clock configure request with USB Module enabled */
FSP_ERR_HARDWARE_TIMEOUT = 410, /* /< A register read or write timed out */
FSP_ERR_LOW_VOLTAGE_MODE = 411, /* /< Invalid clock setting attempted in low voltage mode */
/* Start of FLASH Specific */
FSP_ERR_PE_FAILURE = 500, /* /< Unable to enter Programming mode. */
FSP_ERR_CMD_LOCKED = 501, /* /< Peripheral in command locked state */
FSP_ERR_FCLK = 502, /* /< FCLK must be >= 4 MHz */
FSP_ERR_INVALID_LINKED_ADDRESS = 503, /* /< Function or data are linked at an invalid region of memory */
FSP_ERR_BLANK_CHECK_FAILED = 504, /* /< Blank check operation failed */
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, /* /< Measured clock rate < reference clock rate */
/* Start of IIRFA Specific */
FSP_ERR_INVALID_RESULT = 700, /* /< The result of one or more calculations was +/- infinity. */
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, /* /< Clock cannot be specified as system clock */
FSP_ERR_INVALID_TIMING_SETTING = 1001, /* /< Invalid timing parameter */
FSP_ERR_INVALID_LAYER_SETTING = 1002, /* /< Invalid layer parameter */
FSP_ERR_INVALID_ALIGNMENT = 1003, /* /< Invalid memory alignment found */
FSP_ERR_INVALID_GAMMA_SETTING = 1004, /* /< Invalid gamma correction parameter */
FSP_ERR_INVALID_LAYER_FORMAT = 1005, /* /< Invalid color format in layer */
FSP_ERR_INVALID_UPDATE_TIMING = 1006, /* /< Invalid timing for register update */
FSP_ERR_INVALID_CLUT_ACCESS = 1007, /* /< Invalid access to CLUT entry */
FSP_ERR_INVALID_FADE_SETTING = 1008, /* /< Invalid fade-in/fade-out setting */
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, /* /< Invalid gamma correction parameter */
/* Start of JPEG Specific */
FSP_ERR_JPEG_ERR = 1100, /* /< JPEG error */
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, /* /< SOI not detected until EOI detected. */
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, /* /< SOF1 to SOFF detected. */
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, /* /< Unprovided pixel format detected. */
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, /* /< SOF accuracy error: other than 8 detected. */
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, /* /< DQT accuracy error: other than 0 detected. */
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, /* /< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. */
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, /* /< Component error 2: the number of components differs between SOF0 header and SOS. */
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, /* /< SOF0, DQT, and DHT not detected when SOS detected. */
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, /* /< SOS not detected: SOS not detected until EOI detected. */
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, /* /< EOI not detected (default) */
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, /* /< Restart interval data number error detected. */
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, /* /< Image size error detected. */
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, /* /< Last MCU data number error detected. */
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, /* /< Block data number error detected. */
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, /* /< User provided buffer size not enough */
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, /* /< JPEG Image size is not aligned with MCU */
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, /* /< Calibration failed */
/* Start of IIRFA specific */
FSP_ERR_IIRFA_ECC_1BIT = 1300, /* /< 1-bit ECC error detected */
FSP_ERR_IIRFA_ECC_2BIT = 1301, /* /< 2-bit ECC error detected */
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, /* /< Requested IP does not exist on this device */
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, /* /< Requested unit does not exist on this device */
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, /* /< Requested channel does not exist on this device */
/* Start of USB specific */
FSP_ERR_USB_FAILED = 1500,
FSP_ERR_USB_BUSY = 1501,
FSP_ERR_USB_SIZE_SHORT = 1502,
FSP_ERR_USB_SIZE_OVER = 1503,
FSP_ERR_USB_NOT_OPEN = 1504,
FSP_ERR_USB_NOT_SUSPEND = 1505,
FSP_ERR_USB_PARAMETER = 1506,
/* Start of Message framework specific */
FSP_ERR_NO_MORE_BUFFER = 2000, /* /< No more buffer found in the memory block pool */
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, /* /< Buffer address is out of block memory pool */
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, /* /< Work buffer size is invalid */
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, /* /< Message buffer size is invalid */
FSP_ERR_TOO_MANY_BUFFERS = 2004, /* /< Number of buffer is too many */
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, /* /< No message subscriber found */
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, /* /< No message found in the message queue */
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, /* /< No room for new message in the message queue */
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, /* /< Message subscriber lists is illegal */
FSP_ERR_BUFFER_RELEASED = 2009, /* /< Buffer has been released */
/* Start of 2DG Driver specific */
FSP_ERR_D2D_ERROR_INIT = 3000, /* /< D/AVE 2D has an error in the initialization */
FSP_ERR_D2D_ERROR_DEINIT = 3001, /* /< D/AVE 2D has an error in the initialization */
FSP_ERR_D2D_ERROR_RENDERING = 3002, /* /< D/AVE 2D has an error in the rendering */
FSP_ERR_D2D_ERROR_SIZE = 3003, /* /< D/AVE 2D has an error in the rendering */
/* Start of ETHER Driver specific */
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, /* /< No Data in Receive buffer. */
FSP_ERR_ETHER_ERROR_LINK = 4001, /* /< ETHERC/EDMAC has an error in the Auto-negotiation */
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, /* /< As a Magic Packet is being detected, and transmission/reception is not enabled */
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, /* /< Transmit buffer is not empty */
FSP_ERR_ETHER_ERROR_FILTERING = 4004, /* /< Detect multicast frame when multicast frame filtering enable */
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, /* /< ETHERC/EDMAC has an error in the phy communication */
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, /* /< Receive buffer is active. */
/* Start of ETHER_PHY Driver specific */
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, /* /< PHY is not link up. */
FSP_ERR_ETHER_PHY_NOT_READY = 5001, /* /< PHY has an error in the Auto-negotiation */
/* Start of BYTEQ library specific */
FSP_ERR_QUEUE_FULL = 10000, /* /< Queue is full, cannot queue another data */
FSP_ERR_QUEUE_EMPTY = 10001, /* /< Queue is empty, no data to dequeue */
/* Start of CTSU Driver specific */
FSP_ERR_CTSU_SCANNING = 6000, /* /< Scanning. */
FSP_ERR_CTSU_NOT_GET_DATA = 6001, /* /< Not processed previous scan data. */
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, /* /< Incomplete initial offset tuning. */
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, /* /< Diagnosis of data collected no yet. */
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, /* /< Diagnosis of LDO over voltage failed. */
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, /* /< Diagnosis of CCO into 19.2uA failed. */
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, /* /< Diagnosis of CCO into 2.4uA failed. */
FSP_ERR_CTSU_DIAG_SSCG = 6007, /* /< Diagnosis of SSCG frequency failed. */
FSP_ERR_CTSU_DIAG_DAC = 6008, /* /< Diagnosis of non-touch count value failed. */
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, /* /< Diagnosis of LDO output voltage failed. */
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, /* /< Diagnosis of over voltage detection circuit failed. */
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, /* /< Diagnosis of over current detection circuit failed. */
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, /* /< Diagnosis of LDO internal resistance value failed. */
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, /* /< Diagnosis of Current source value failed. */
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, /* /< Diagnosis of SENSCLK frequency gain failed. */
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, /* /< Diagnosis of SUCLK frequency gain failed. */
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, /* /< Diagnosis of SUCLK clock recovery function failed. */
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, /* /< Diagnosis of CFC oscillator gain failed. */
/* Start of SDMMC specific */
FSP_ERR_CARD_INIT_FAILED = 40000, /* /< SD card or eMMC device failed to initialize. */
FSP_ERR_CARD_NOT_INSERTED = 40001, /* /< SD card not installed. */
FSP_ERR_DEVICE_BUSY = 40002, /* /< Device is holding DAT0 low or another operation is ongoing. */
FSP_ERR_CARD_NOT_INITIALIZED = 40004, /* /< SD card was removed. */
FSP_ERR_CARD_WRITE_PROTECTED = 40005, /* /< Media is write protected. */
FSP_ERR_TRANSFER_BUSY = 40006, /* /< Transfer in progress. */
FSP_ERR_RESPONSE = 40007, /* /< Card did not respond or responded with an error. */
/* Start of FX_IO specific */
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, /* /< Media format failed. */
FSP_ERR_MEDIA_OPEN_FAILED = 50001, /* /< Media open failed. */
/* Start of CAN specific */
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, /* /< No data available. */
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, /* /< Switching operation modes failed. */
FSP_ERR_CAN_INIT_FAILED = 60002, /* /< Hardware initialization failed. */
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, /* /< Transmit in progress. */
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, /* /< Mailbox is setup as a receive mailbox. */
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, /* /< Mailbox is setup as a transmit mailbox. */
FSP_ERR_CAN_MESSAGE_LOST = 60006, /* /< Receive message has been overwritten or overrun. */
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, /* /< Transmit FIFO is full. */
/* Start of SF_WIFI Specific */
FSP_ERR_WIFI_CONFIG_FAILED = 70000, /* /< WiFi module Configuration failed. */
FSP_ERR_WIFI_INIT_FAILED = 70001, /* /< WiFi module initialization failed. */
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, /* /< Transmission failed */
FSP_ERR_WIFI_INVALID_MODE = 70003, /* /< API called when provisioned in client mode */
FSP_ERR_WIFI_FAILED = 70004, /* /< WiFi Failed. */
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, /* /< Wifi scan has completed. */
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, /* /< WiFi module is not connected to access point */
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, /* /< DA16XXX Unknown AT command Error */
FSP_ERR_WIFI_INSUF_PARAM = 70008, /* /< DA16XXX Insufficient parameter */
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, /* /< DA16XXX Too many parameters */
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, /* /< DA16XXX Wrong parameter value */
FSP_ERR_WIFI_NO_RESULT = 70011, /* /< DA16XXX No result */
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, /* /< DA16XXX Response buffer overflow */
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, /* /< DA16XXX Function is not configured */
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, /* /< DA16XXX NVRAM write failure */
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, /* /< DA16XXX Retention memory write failure */
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, /* /< DA16XXX unknown error */
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, /* /< Cellular module Configuration failed. */
FSP_ERR_CELLULAR_INIT_FAILED = 80001, /* /< Cellular module initialization failed. */
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, /* /< Transmission failed */
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, /* /< Firmware is uptodate */
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, /* /< Firmware upgrade failed */
FSP_ERR_CELLULAR_FAILED = 80005, /* /< Cellular Failed. */
FSP_ERR_CELLULAR_INVALID_STATE = 80006, /* /< API Called in invalid state. */
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, /* /< Cellular Network registration failed */
/* Start of SF_BLE specific */
FSP_ERR_BLE_FAILED = 90001, /* /< BLE operation failed */
FSP_ERR_BLE_INIT_FAILED = 90002, /* /< BLE device initialization failed */
FSP_ERR_BLE_CONFIG_FAILED = 90003, /* /< BLE device configuration failed */
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, /* /< BLE device Profile already enabled */
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, /* /< BLE device not enabled */
/* Start of SF_BLE_ABS specific */
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, /* /< Invalid operation is executed. */
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, /* /< Valid data or free space is not found. */
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
FSP_ERR_CRYPTO_CONTINUE = 0x10000, /* /< Continue executing function */
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, /* /< Hardware resource busy */
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, /* /< Internal I/O buffer is not empty */
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, /* /< Invalid index */
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, /* /< Retry */
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, /* /< Verify is failed */
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, /* /< HW SCE module is already opened */
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, /* /< Hardware module is not initialized */
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, /* /< Some unknown error occurred */
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, /* /< Null pointer input as a parameter */
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, /* /< Algorithm/size not implemented */
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, /* /< An invalid parameter is specified */
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, /* /< A fatal error occurred */
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, /* /< Size specified is invalid */
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, /* /< Function used in an valid state */
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, /* /< control block is already opened */
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, /* /< Specified input key is invalid. */
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, /* /< Authentication failed */
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, /* /< Failure to Init Cipher */
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, /* /< Authentication failed */
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, /* /< Input date is illegal. */
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, /* /< An invalid function call occurred. */
/* Start of Crypto RSIP specific (0x10100) */
FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, /* /< Hardware resource is busy */
FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, /* /< Hardware fatal error or unexpected return */
FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, /* /< Internal error */
FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, /* /< Input key type is illegal */
FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, /* /< Authentication failed */
/* Start of SF_CRYPTO specific */
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, /* /< Crypto Framework Common is not opened */
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, /* /< Cryoto HAL module returned an error */
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, /* /< Key buffer size is not enough to generate a key */
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, /* /< Attempt to write data larger than what the buffer can hold */
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, /* /< Invalid operation mode. */
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, /* /< Message for RSA encryption is too long. */
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, /* /< RSA Decryption error. */
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
* Refer to sf_cryoto_err.h for Crypto error codes.
*/
/* Start of Sensor specific */
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, /* /< Data is invalid. */
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, /* /< Sensor is stabilizing. */
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, /* /< Measurement is not finished. */
/* Start of COMMS specific */
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, /* /< Bus is not open. */
} fsp_err_t;
/** @} */
/***********************************************************************************************************************
* Function prototypes
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @ingroup RENESAS_SYSTEM_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
* @brief Interface for accessing I/O ports and configuring I/O functionality.
*
* @section IOPORT_API_SUMMARY Summary
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
* Port and pin direction can be changed.
*
*
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_API_H
#define R_IOPORT_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_IOPORT_SIZE_T
/** IO port type used with ports */
typedef uint16_t ioport_size_t; /* /< IO port size */
#endif
/** Pin identifier and pin configuration value */
typedef struct st_ioport_pin_cfg
{
uint32_t pin_cfg; /* /< Pin configuration - Use ioport_cfg_options_t parameters to configure */
bsp_io_port_pin_t pin; /* /< Pin identifier */
} ioport_pin_cfg_t;
/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */
typedef struct st_ioport_cfg
{
uint16_t number_of_pins; /* /< Number of pins for which there is configuration data */
ioport_pin_cfg_t const * p_pin_cfg_data; /* /< Pin configuration data */
const void * p_extend; /* /< Pointer to hardware extend configuration */
} ioport_cfg_t;
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
*/
typedef void ioport_ctrl_t;
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
typedef struct st_ioport_api
{
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
* multiple pins.
*
* @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Close the API.
*
* @param[in] p_ctrl Pointer to control structure.
**/
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
/** Configure multiple pins.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Configure settings for an individual pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] cfg Configuration options for the pin.
*/
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
/** Read the event input data of the specified pin and return the level.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_event Pointer to return the event data.
*/
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
/** Write pin event data.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin event data is to be written to.
* @param[in] pin_value Level to be written to pin output event.
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/** Read level of a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_value Pointer to return the pin level.
*/
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
/** Write specified level to a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be written to.
* @param[in] level State to be written to the pin.
*/
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
/** Set the direction of one or more pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port being configured.
* @param[in] direction_values Value controlling direction of pins on port.
* @param[in] mask Mask controlling which pins on the port are to be configured.
*/
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
ioport_size_t mask);
/** Read captured event data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_event_data Pointer to return the event data.
*/
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
/** Write event output data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port event data will be written to.
* @param[in] event_data Data to be written as event data to specified port.
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
* being written to port.
*/
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
ioport_size_t mask_value);
/** Read states of pins on the specified port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_port_value Pointer to return the port value.
*/
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
/** Write to multiple pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be written to.
* @param[in] value Value to be written to the port.
* @param[in] mask Mask controlling which pins on the port are written to.
*/
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
} ioport_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_ioport_instance
{
ioport_ctrl_t * p_ctrl; /* /< Pointer to the control structure for this instance */
ioport_cfg_t const * p_cfg; /* /< Pointer to the configuration structure for this instance */
ioport_api_t const * p_api; /* /< Pointer to the API structure for this instance */
} ioport_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT_API)
**********************************************************************************************************************/

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @ingroup RENESAS_TRANSFER_INTERFACES
* @defgroup TRANSFER_API Transfer Interface
*
* @brief Interface for data transfer functions.
*
* @section TRANSFER_API_SUMMARY Summary
* The transfer interface supports background data transfer (no CPU intervention).
*
*
* @{
**********************************************************************************************************************/
#ifndef R_TRANSFER_API_H
#define R_TRANSFER_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define TRANSFER_SETTINGS_MODE_BITS (30U)
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
*/
typedef void transfer_ctrl_t;
#ifndef BSP_OVERRIDE_TRANSFER_MODE_T
/** Transfer mode describes what will happen when a transfer request occurs. */
typedef enum e_transfer_mode
{
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
* the destination pointer. The transfer length is decremented and the source and address pointers are
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
* will not cause any further transfers. */
TRANSFER_MODE_NORMAL = 0,
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
TRANSFER_MODE_REPEAT = 1,
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
* After each individual transfer, the source and destination pointers are updated according to
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
* further transfers. */
TRANSFER_MODE_BLOCK = 2,
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
* within a block (to split blocks into arrays of their first data, second data, etc.) */
TRANSFER_MODE_REPEAT_BLOCK = 3
} transfer_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T
/** Transfer size specifies the size of each individual transfer.
* Total transfer length = transfer_size_t * transfer_length_t
*/
typedef enum e_transfer_size
{
TRANSFER_SIZE_1_BYTE = 0, /* /< Each transfer transfers a 8-bit value */
TRANSFER_SIZE_2_BYTE = 1, /* /< Each transfer transfers a 16-bit value */
TRANSFER_SIZE_4_BYTE = 2, /* /< Each transfer transfers a 32-bit value */
TRANSFER_SIZE_8_BYTE = 3 /* /< Each transfer transfers a 64-bit value */
} transfer_size_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
typedef enum e_transfer_addr_mode
{
/** Address pointer remains fixed after each transfer. */
TRANSFER_ADDR_MODE_FIXED = 0,
/** Offset is added to the address pointer after each transfer. */
TRANSFER_ADDR_MODE_OFFSET = 1,
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_INCREMENTED = 2,
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_DECREMENTED = 3
} transfer_addr_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
* the selected pointer returns to its original value after each transfer. */
typedef enum e_transfer_repeat_area
{
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_DESTINATION = 0,
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_SOURCE = 1
} transfer_repeat_area_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T
/** Chain transfer mode options.
* @note Only applies for DTC. */
typedef enum e_transfer_chain_mode
{
/** Chain mode not used. */
TRANSFER_CHAIN_MODE_DISABLED = 0,
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
TRANSFER_CHAIN_MODE_EACH = 2,
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
TRANSFER_CHAIN_MODE_END = 3
} transfer_chain_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T
/** Interrupt options. */
typedef enum e_transfer_irq
{
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
* the interrupt will occur only after subsequent chained transfer(s) are complete.
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
* prevent activation source interrupts until the transfer is complete. */
TRANSFER_IRQ_END = 0,
/** Interrupt occurs after each transfer.
* @note Not available in all HAL drivers. See HAL driver for details. */
TRANSFER_IRQ_EACH = 1
} transfer_irq_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T
/** Callback function parameter data. */
typedef struct st_transfer_callback_args_t
{
void const * p_context; /* /< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. */
} transfer_callback_args_t;
#endif
/** Driver specific information. */
typedef struct st_transfer_properties
{
uint32_t block_count_max; /* /< Maximum number of blocks */
uint32_t block_count_remaining; /* /< Number of blocks remaining */
uint32_t transfer_length_max; /* /< Maximum number of transfers */
uint32_t transfer_length_remaining; /* /< Number of transfers remaining */
} transfer_properties_t;
#ifndef BSP_OVERRIDE_TRANSFER_INFO_T
/** This structure specifies the properties of the transfer.
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
* have a unique transfer_info_t.
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
* structure must remain in scope until the transfer it is used for is closed.
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
typedef struct st_transfer_info
{
union
{
struct
{
uint32_t : 16;
uint32_t : 2;
/** Select what happens to destination pointer after each transfer. */
transfer_addr_mode_t dest_addr_mode : 2;
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
transfer_repeat_area_t repeat_area : 1;
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
* transfers. */
transfer_irq_t irq : 1;
/** Select when the chain transfer ends. */
transfer_chain_mode_t chain_mode : 2;
uint32_t : 2;
/** Select what happens to source pointer after each transfer. */
transfer_addr_mode_t src_addr_mode : 2;
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
transfer_size_t size : 2;
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
} transfer_settings_word_b;
uint32_t transfer_settings_word;
};
void const * volatile p_src; /* /< Source pointer */
void * volatile p_dest; /* /< Destination pointer */
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
volatile uint16_t num_blocks;
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
* and @ref TRANSFER_MODE_REPEAT_BLOCK
* see HAL driver for details. */
volatile uint16_t length;
} transfer_info_t;
#endif
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
* initialized. */
typedef struct st_transfer_cfg
{
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
* an array of chained transfers that will be completed in order. */
transfer_info_t * p_info;
void const * p_extend; /* /< Extension parameter for hardware specific settings. */
} transfer_cfg_t;
/** Select whether to start single or repeated transfer with software start. */
typedef enum e_transfer_start_mode
{
TRANSFER_START_MODE_SINGLE = 0, /* /< Software start triggers single transfer. */
TRANSFER_START_MODE_REPEAT = 1 /* /< Software start transfer continues until transfer is complete. */
} transfer_start_mode_t;
/** Transfer functions implemented at the HAL layer will follow this API. */
typedef struct st_transfer_api
{
/** Initial configuration.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
* must be set by user.
*/
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
/** Reconfigure the transfer.
* Enable the transfer if p_info is valid.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_info Pointer to a new transfer info structure.
*/
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
* Enable the transfer if p_src, p_dest, and length are valid.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
* repeat mode. Not used in repeat mode for DTC.
*/
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint16_t const num_transfers);
/** Enable transfer. Transfers occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source).
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
/** Disable transfer. Transfers do not occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source).
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
* transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
/** Start transfer in software.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
* @note Not supported for DTC.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] mode Select mode from @ref transfer_start_mode_t.
*/
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
* @note Not supported for DTC.
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
/** Provides information about this transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[out] p_properties Driver specific information.
*/
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
/** To update next transfer information without interruption during transfer.
* Allow further transfer continuation.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or block mode.
*/
fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint32_t const num_transfers);
/** Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_callback Callback function to register
* @param[in] p_context Pointer to send to callback function
* @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *),
void const * const p_context, transfer_callback_args_t * const p_callback_memory);
} transfer_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_transfer_instance
{
transfer_ctrl_t * p_ctrl; /* /< Pointer to the control structure for this instance */
transfer_cfg_t const * p_cfg; /* /< Pointer to the configuration structure for this instance */
transfer_api_t const * p_api; /* /< Pointer to the API structure for this instance */
} transfer_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup TRANSFER_API)
**********************************************************************************************************************/

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @ingroup RENESAS_CONNECTIVITY_INTERFACES
* @defgroup UART_API UART Interface
* @brief Interface for UART communications.
*
* @section UART_INTERFACE_SUMMARY Summary
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
* - Full-duplex UART communication
* - Interrupt driven transmit/receive processing
* - Callback function with returned event code
* - Runtime baud-rate change
* - Hardware resource locking during a transaction
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
*
*
* @{
**********************************************************************************************************************/
#ifndef R_UART_API_H
#define R_UART_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** UART Event codes */
#ifndef BSP_OVERRIDE_UART_EVENT_T
typedef enum e_sf_event
{
UART_EVENT_RX_COMPLETE = (1UL << 0), /* /< Receive complete event */
UART_EVENT_TX_COMPLETE = (1UL << 1), /* /< Transmit complete event */
UART_EVENT_RX_CHAR = (1UL << 2), /* /< Character received */
UART_EVENT_ERR_PARITY = (1UL << 3), /* /< Parity error event */
UART_EVENT_ERR_FRAMING = (1UL << 4), /* /< Mode fault error event */
UART_EVENT_ERR_OVERFLOW = (1UL << 5), /* /< FIFO Overflow error event */
UART_EVENT_BREAK_DETECT = (1UL << 6), /* /< Break detect error event */
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), /* /< Last byte is transmitting, ready for more data */
} uart_event_t;
#endif
#ifndef BSP_OVERRIDE_UART_DATA_BITS_T
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
UART_DATA_BITS_9 = 0U, /* /< Data bits 9-bit */
UART_DATA_BITS_8 = 2U, /* /< Data bits 8-bit */
UART_DATA_BITS_7 = 3U, /* /< Data bits 7-bit */
} uart_data_bits_t;
#endif
#ifndef BSP_OVERRIDE_UART_PARITY_T
/** UART Parity definition */
typedef enum e_uart_parity
{
UART_PARITY_OFF = 0U, /* /< No parity */
UART_PARITY_ZERO = 1U, /* /< Zero parity */
UART_PARITY_EVEN = 2U, /* /< Even parity */
UART_PARITY_ODD = 3U, /* /< Odd parity */
} uart_parity_t;
#endif
/** UART Stop bits definition */
typedef enum e_uart_stop_bits
{
UART_STOP_BITS_1 = 0U, /* /< Stop bit 1-bit */
UART_STOP_BITS_2 = 1U, /* /< Stop bits 2-bit */
} uart_stop_bits_t;
/** UART transaction definition */
typedef enum e_uart_dir
{
UART_DIR_RX_TX = 3U, /* /< Both RX and TX */
UART_DIR_RX = 1U, /* /< Only RX */
UART_DIR_TX = 2U, /* /< Only TX */
} uart_dir_t;
/** UART driver specific information */
typedef struct st_uart_info
{
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
uint32_t write_bytes_max;
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
uint32_t read_bytes_max;
} uart_info_t;
/** UART Callback parameter definition */
typedef struct st_uart_callback_arg
{
uint32_t channel; /* /< Device channel number */
uart_event_t event; /* /< Event code */
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
uint32_t data;
void const * p_context; /* /< Context provided to user during callback */
} uart_callback_args_t;
/** UART Configuration */
typedef struct st_uart_cfg
{
/* UART generic configuration */
uint8_t channel; /* /< Select a channel corresponding to the channel number of the hardware. */
uart_data_bits_t data_bits; /* /< Data bit length (8 or 7 or 9) */
uart_parity_t parity; /* /< Parity type (none or odd or even) */
uart_stop_bits_t stop_bits; /* /< Stop bit length (1 or 2) */
uint8_t rxi_ipl; /* /< Receive interrupt priority */
IRQn_Type rxi_irq; /* /< Receive interrupt IRQ number */
uint8_t txi_ipl; /* /< Transmit interrupt priority */
IRQn_Type txi_irq; /* /< Transmit interrupt IRQ number */
uint8_t tei_ipl; /* /< Transmit end interrupt priority */
IRQn_Type tei_irq; /* /< Transmit end interrupt IRQ number */
uint8_t eri_ipl; /* /< Error interrupt priority */
IRQn_Type eri_irq; /* /< Error interrupt IRQ number */
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
transfer_instance_t const * p_transfer_rx;
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
transfer_instance_t const * p_transfer_tx;
/* Configuration for UART Event processing */
void (* p_callback)(uart_callback_args_t * p_args); /* /< Pointer to callback function */
void const * p_context; /* /< User defined context passed into callback function */
/* Pointer to UART peripheral specific configuration */
void const * p_extend; /* /< UART hardware dependent configuration */
} uart_cfg_t;
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
*/
typedef void uart_ctrl_t;
/** Shared Interface definition for UART */
typedef struct st_uart_api
{
/** Open UART device.
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
* user.
*/
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
* the callback function with event UART_EVENT_RX_CHAR.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
* @param[in] bytes Read data length.
*/
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
* the callback called with event UART_EVENT_TX_COMPLETE.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
* @param[in] bytes Write data length.
*/
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
/** Change baud rate.
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
* settings have been applied.
*
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
*/
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
/** Get the driver specific information.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[out] p_info Pointer to UART information structure.
*/
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
/**
* Abort ongoing transfer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
*/
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
/**
* Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *),
void const * const p_context, uart_callback_args_t * const p_callback_memory);
/** Close UART device.
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
/** Stop ongoing read and return the number of bytes remaining in the read.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
*/
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_uart_instance
{
uart_ctrl_t * p_ctrl; /* /< Pointer to the control structure for this instance */
uart_cfg_t const * p_cfg; /* /< Pointer to the configuration structure for this instance */
uart_api_t const * p_api; /* /< Pointer to the API structure for this instance */
} uart_instance_t;
/** @} (end defgroup UART_API) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSP_FEATURES_H
#define FSP_FEATURES_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
/* Different compiler support. */
#include "fsp_common_api.h"
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Available modules. */
typedef enum e_fsp_ip
{
FSP_IP_CFLASH = 0, /* /< Code Flash */
FSP_IP_DFLASH = 1, /* /< Data Flash */
FSP_IP_RAM = 2, /* /< RAM */
FSP_IP_LVD = 3, /* /< Low Voltage Detection */
FSP_IP_CGC = 3, /* /< Clock Generation Circuit */
FSP_IP_LPM = 3, /* /< Low Power Modes */
FSP_IP_FCU = 4, /* /< Flash Control Unit */
FSP_IP_ICU = 6, /* /< Interrupt Control Unit */
FSP_IP_DMAC = 7, /* /< DMA Controller */
FSP_IP_DTC = 8, /* /< Data Transfer Controller */
FSP_IP_IOPORT = 9, /* /< I/O Ports */
FSP_IP_PFS = 10, /* /< Pin Function Select */
FSP_IP_ELC = 11, /* /< Event Link Controller */
FSP_IP_MPU = 13, /* /< Memory Protection Unit */
FSP_IP_MSTP = 14, /* /< Module Stop */
FSP_IP_MMF = 15, /* /< Memory Mirror Function */
FSP_IP_KEY = 16, /* /< Key Interrupt Function */
FSP_IP_CAC = 17, /* /< Clock Frequency Accuracy Measurement Circuit */
FSP_IP_DOC = 18, /* /< Data Operation Circuit */
FSP_IP_CRC = 19, /* /< Cyclic Redundancy Check Calculator */
FSP_IP_SCI = 20, /* /< Serial Communications Interface */
FSP_IP_IIC = 21, /* /< I2C Bus Interface */
FSP_IP_SPI = 22, /* /< Serial Peripheral Interface */
FSP_IP_CTSU = 23, /* /< Capacitive Touch Sensing Unit */
FSP_IP_SCE = 24, /* /< Secure Cryptographic Engine */
FSP_IP_SLCDC = 25, /* /< Segment LCD Controller */
FSP_IP_AES = 26, /* /< Advanced Encryption Standard */
FSP_IP_TRNG = 27, /* /< True Random Number Generator */
FSP_IP_FCACHE = 30, /* /< Flash Cache */
FSP_IP_SRAM = 31, /* /< SRAM */
FSP_IP_ADC = 32, /* /< A/D Converter */
FSP_IP_DAC = 33, /* /< 12-Bit D/A Converter */
FSP_IP_TSN = 34, /* /< Temperature Sensor */
FSP_IP_DAAD = 35, /* /< D/A A/D Synchronous Unit */
FSP_IP_ACMPHS = 36, /* /< High Speed Analog Comparator */
FSP_IP_ACMPLP = 37, /* /< Low Power Analog Comparator */
FSP_IP_OPAMP = 38, /* /< Operational Amplifier */
FSP_IP_SDADC = 39, /* /< Sigma Delta A/D Converter */
FSP_IP_RTC = 40, /* /< Real Time Clock */
FSP_IP_WDT = 41, /* /< Watch Dog Timer */
FSP_IP_IWDT = 42, /* /< Independent Watch Dog Timer */
FSP_IP_GPT = 43, /* /< General PWM Timer */
FSP_IP_POEG = 44, /* /< Port Output Enable for GPT */
FSP_IP_OPS = 45, /* /< Output Phase Switch */
FSP_IP_AGT = 47, /* /< Asynchronous General-Purpose Timer */
FSP_IP_CAN = 48, /* /< Controller Area Network */
FSP_IP_IRDA = 49, /* /< Infrared Data Association */
FSP_IP_QSPI = 50, /* /< Quad Serial Peripheral Interface */
FSP_IP_USBFS = 51, /* /< USB Full Speed */
FSP_IP_SDHI = 52, /* /< SD/MMC Host Interface */
FSP_IP_SRC = 53, /* /< Sampling Rate Converter */
FSP_IP_SSI = 54, /* /< Serial Sound Interface */
FSP_IP_DALI = 55, /* /< Digital Addressable Lighting Interface */
FSP_IP_ETHER = 64, /* /< Ethernet MAC Controller */
FSP_IP_EDMAC = 64, /* /< Ethernet DMA Controller */
FSP_IP_EPTPC = 65, /* /< Ethernet PTP Controller */
FSP_IP_PDC = 66, /* /< Parallel Data Capture Unit */
FSP_IP_GLCDC = 67, /* /< Graphics LCD Controller */
FSP_IP_DRW = 68, /* /< 2D Drawing Engine */
FSP_IP_JPEG = 69, /* /< JPEG */
FSP_IP_DAC8 = 70, /* /< 8-Bit D/A Converter */
FSP_IP_USBHS = 71, /* /< USB High Speed */
FSP_IP_OSPI = 72, /* /< Octa Serial Peripheral Interface */
FSP_IP_CEC = 73, /* /< HDMI CEC */
FSP_IP_TFU = 74, /* /< Trigonometric Function Unit */
FSP_IP_IIRFA = 75, /* /< IIR Filter Accelerator */
FSP_IP_CANFD = 76, /* /< CAN-FD */
FSP_IP_ULPT = 77, /* /< Ultra Low Power Timer ULPT */
FSP_IP_SAU = 78, /* /< Serial Array Unit */
FSP_IP_IICA = 79, /* /< Serial Interface IICA */
FSP_IP_UARTA = 80, /* /< Serial Interface UARTA */
FSP_IP_TAU = 81, /* /< Timer Array Unit */
FSP_IP_TML = 82, /* /< 32-bit Interval Timer */
FSP_IP_MACL = 83, /* /< 32-bit Multiply-Accumulator */
FSP_IP_USBCC = 84, /* /< USB Type-C Controller */
} fsp_ip_t;
/** Signals that can be mapped to an interrupt. */
typedef enum e_fsp_signal
{
FSP_SIGNAL_ADC_COMPARE_MATCH = 0, /* /< ADC COMPARE MATCH */
FSP_SIGNAL_ADC_COMPARE_MISMATCH, /* /< ADC COMPARE MISMATCH */
FSP_SIGNAL_ADC_SCAN_END, /* /< ADC SCAN END */
FSP_SIGNAL_ADC_SCAN_END_B, /* /< ADC SCAN END B */
FSP_SIGNAL_ADC_WINDOW_A, /* /< ADC WINDOW A */
FSP_SIGNAL_ADC_WINDOW_B, /* /< ADC WINDOW B */
FSP_SIGNAL_AES_RDREQ = 0, /* /< AES RDREQ */
FSP_SIGNAL_AES_WRREQ, /* /< AES WRREQ */
FSP_SIGNAL_AGT_COMPARE_A = 0, /* /< AGT COMPARE A */
FSP_SIGNAL_AGT_COMPARE_B, /* /< AGT COMPARE B */
FSP_SIGNAL_AGT_INT, /* /< AGT INT */
FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, /* /< CAC FREQUENCY ERROR */
FSP_SIGNAL_CAC_MEASUREMENT_END, /* /< CAC MEASUREMENT END */
FSP_SIGNAL_CAC_OVERFLOW, /* /< CAC OVERFLOW */
FSP_SIGNAL_CAN_ERROR = 0, /* /< CAN ERROR */
FSP_SIGNAL_CAN_FIFO_RX, /* /< CAN FIFO RX */
FSP_SIGNAL_CAN_FIFO_TX, /* /< CAN FIFO TX */
FSP_SIGNAL_CAN_MAILBOX_RX, /* /< CAN MAILBOX RX */
FSP_SIGNAL_CAN_MAILBOX_TX, /* /< CAN MAILBOX TX */
FSP_SIGNAL_CGC_MOSC_STOP = 0, /* /< CGC MOSC STOP */
FSP_SIGNAL_LPM_SNOOZE_REQUEST, /* /< LPM SNOOZE REQUEST */
FSP_SIGNAL_LVD_LVD1, /* /< LVD LVD1 */
FSP_SIGNAL_LVD_LVD2, /* /< LVD LVD2 */
FSP_SIGNAL_VBATT_LVD, /* /< VBATT LVD */
FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, /* /< LVD VBATT */
FSP_SIGNAL_ACMPHS_INT = 0, /* /< ACMPHS INT */
FSP_SIGNAL_ACMPLP_INT = 0, /* /< ACMPLP INT */
FSP_SIGNAL_CTSU_END = 0, /* /< CTSU END */
FSP_SIGNAL_CTSU_READ, /* /< CTSU READ */
FSP_SIGNAL_CTSU_WRITE, /* /< CTSU WRITE */
FSP_SIGNAL_DALI_DEI = 0, /* /< DALI DEI */
FSP_SIGNAL_DALI_CLI, /* /< DALI CLI */
FSP_SIGNAL_DALI_SDI, /* /< DALI SDI */
FSP_SIGNAL_DALI_BPI, /* /< DALI BPI */
FSP_SIGNAL_DALI_FEI, /* /< DALI FEI */
FSP_SIGNAL_DALI_SDI_OR_BPI, /* /< DALI SDI OR BPI */
FSP_SIGNAL_DMAC_INT = 0, /* /< DMAC INT */
FSP_SIGNAL_DOC_INT = 0, /* /< DOC INT */
FSP_SIGNAL_DRW_INT = 0, /* /< DRW INT */
FSP_SIGNAL_DTC_COMPLETE = 0, /* /< DTC COMPLETE */
FSP_SIGNAL_DTC_END, /* /< DTC END */
FSP_SIGNAL_EDMAC_EINT = 0, /* /< EDMAC EINT */
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, /* /< ELC SOFTWARE EVENT 0 */
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, /* /< ELC SOFTWARE EVENT 1 */
FSP_SIGNAL_EPTPC_IPLS = 0, /* /< EPTPC IPLS */
FSP_SIGNAL_EPTPC_MINT, /* /< EPTPC MINT */
FSP_SIGNAL_EPTPC_PINT, /* /< EPTPC PINT */
FSP_SIGNAL_EPTPC_TIMER0_FALL, /* /< EPTPC TIMER0 FALL */
FSP_SIGNAL_EPTPC_TIMER0_RISE, /* /< EPTPC TIMER0 RISE */
FSP_SIGNAL_EPTPC_TIMER1_FALL, /* /< EPTPC TIMER1 FALL */
FSP_SIGNAL_EPTPC_TIMER1_RISE, /* /< EPTPC TIMER1 RISE */
FSP_SIGNAL_EPTPC_TIMER2_FALL, /* /< EPTPC TIMER2 FALL */
FSP_SIGNAL_EPTPC_TIMER2_RISE, /* /< EPTPC TIMER2 RISE */
FSP_SIGNAL_EPTPC_TIMER3_FALL, /* /< EPTPC TIMER3 FALL */
FSP_SIGNAL_EPTPC_TIMER3_RISE, /* /< EPTPC TIMER3 RISE */
FSP_SIGNAL_EPTPC_TIMER4_FALL, /* /< EPTPC TIMER4 FALL */
FSP_SIGNAL_EPTPC_TIMER4_RISE, /* /< EPTPC TIMER4 RISE */
FSP_SIGNAL_EPTPC_TIMER5_FALL, /* /< EPTPC TIMER5 FALL */
FSP_SIGNAL_EPTPC_TIMER5_RISE, /* /< EPTPC TIMER5 RISE */
FSP_SIGNAL_FCU_FIFERR = 0, /* /< FCU FIFERR */
FSP_SIGNAL_FCU_FRDYI, /* /< FCU FRDYI */
FSP_SIGNAL_GLCDC_LINE_DETECT = 0, /* /< GLCDC LINE DETECT */
FSP_SIGNAL_GLCDC_UNDERFLOW_1, /* /< GLCDC UNDERFLOW 1 */
FSP_SIGNAL_GLCDC_UNDERFLOW_2, /* /< GLCDC UNDERFLOW 2 */
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, /* /< GPT CAPTURE COMPARE A */
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, /* /< GPT CAPTURE COMPARE B */
FSP_SIGNAL_GPT_COMPARE_C, /* /< GPT COMPARE C */
FSP_SIGNAL_GPT_COMPARE_D, /* /< GPT COMPARE D */
FSP_SIGNAL_GPT_COMPARE_E, /* /< GPT COMPARE E */
FSP_SIGNAL_GPT_COMPARE_F, /* /< GPT COMPARE F */
FSP_SIGNAL_GPT_COUNTER_OVERFLOW, /* /< GPT COUNTER OVERFLOW */
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, /* /< GPT COUNTER UNDERFLOW */
FSP_SIGNAL_GPT_AD_TRIG_A, /* /< GPT AD TRIG A */
FSP_SIGNAL_GPT_AD_TRIG_B, /* /< GPT AD TRIG B */
FSP_SIGNAL_OPS_UVW_EDGE, /* /< OPS UVW EDGE */
FSP_SIGNAL_ICU_IRQ0 = 0, /* /< ICU IRQ0 */
FSP_SIGNAL_ICU_IRQ1, /* /< ICU IRQ1 */
FSP_SIGNAL_ICU_IRQ2, /* /< ICU IRQ2 */
FSP_SIGNAL_ICU_IRQ3, /* /< ICU IRQ3 */
FSP_SIGNAL_ICU_IRQ4, /* /< ICU IRQ4 */
FSP_SIGNAL_ICU_IRQ5, /* /< ICU IRQ5 */
FSP_SIGNAL_ICU_IRQ6, /* /< ICU IRQ6 */
FSP_SIGNAL_ICU_IRQ7, /* /< ICU IRQ7 */
FSP_SIGNAL_ICU_IRQ8, /* /< ICU IRQ8 */
FSP_SIGNAL_ICU_IRQ9, /* /< ICU IRQ9 */
FSP_SIGNAL_ICU_IRQ10, /* /< ICU IRQ10 */
FSP_SIGNAL_ICU_IRQ11, /* /< ICU IRQ11 */
FSP_SIGNAL_ICU_IRQ12, /* /< ICU IRQ12 */
FSP_SIGNAL_ICU_IRQ13, /* /< ICU IRQ13 */
FSP_SIGNAL_ICU_IRQ14, /* /< ICU IRQ14 */
FSP_SIGNAL_ICU_IRQ15, /* /< ICU IRQ15 */
FSP_SIGNAL_ICU_SNOOZE_CANCEL, /* /< ICU SNOOZE CANCEL */
FSP_SIGNAL_IIC_ERI = 0, /* /< IIC ERI */
FSP_SIGNAL_IIC_RXI, /* /< IIC RXI */
FSP_SIGNAL_IIC_TEI, /* /< IIC TEI */
FSP_SIGNAL_IIC_TXI, /* /< IIC TXI */
FSP_SIGNAL_IIC_WUI, /* /< IIC WUI */
FSP_SIGNAL_IOPORT_EVENT_1 = 0, /* /< IOPORT EVENT 1 */
FSP_SIGNAL_IOPORT_EVENT_2, /* /< IOPORT EVENT 2 */
FSP_SIGNAL_IOPORT_EVENT_3, /* /< IOPORT EVENT 3 */
FSP_SIGNAL_IOPORT_EVENT_4, /* /< IOPORT EVENT 4 */
FSP_SIGNAL_IOPORT_EVENT_B = 0, /* /< IOPORT EVENT B */
FSP_SIGNAL_IOPORT_EVENT_C, /* /< IOPORT EVENT C */
FSP_SIGNAL_IOPORT_EVENT_D, /* /< IOPORT EVENT D */
FSP_SIGNAL_IOPORT_EVENT_E, /* /< IOPORT EVENT E */
FSP_SIGNAL_IWDT_UNDERFLOW = 0, /* /< IWDT UNDERFLOW */
FSP_SIGNAL_JPEG_JDTI = 0, /* /< JPEG JDTI */
FSP_SIGNAL_JPEG_JEDI, /* /< JPEG JEDI */
FSP_SIGNAL_KEY_INT = 0, /* /< KEY INT */
FSP_SIGNAL_PDC_FRAME_END = 0, /* /< PDC FRAME END */
FSP_SIGNAL_PDC_INT, /* /< PDC INT */
FSP_SIGNAL_PDC_RECEIVE_DATA_READY, /* /< PDC RECEIVE DATA READY */
FSP_SIGNAL_POEG_EVENT = 0, /* /< POEG EVENT */
FSP_SIGNAL_QSPI_INT = 0, /* /< QSPI INT */
FSP_SIGNAL_RTC_ALARM = 0, /* /< RTC ALARM */
FSP_SIGNAL_RTC_PERIOD, /* /< RTC PERIOD */
FSP_SIGNAL_RTC_CARRY, /* /< RTC CARRY */
FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, /* /< SCE INTEGRATE RDRDY */
FSP_SIGNAL_SCE_INTEGRATE_WRRDY, /* /< SCE INTEGRATE WRRDY */
FSP_SIGNAL_SCE_LONG_PLG, /* /< SCE LONG PLG */
FSP_SIGNAL_SCE_PROC_BUSY, /* /< SCE PROC BUSY */
FSP_SIGNAL_SCE_RDRDY_0, /* /< SCE RDRDY 0 */
FSP_SIGNAL_SCE_RDRDY_1, /* /< SCE RDRDY 1 */
FSP_SIGNAL_SCE_ROMOK, /* /< SCE ROMOK */
FSP_SIGNAL_SCE_TEST_BUSY, /* /< SCE TEST BUSY */
FSP_SIGNAL_SCE_WRRDY_0, /* /< SCE WRRDY 0 */
FSP_SIGNAL_SCE_WRRDY_1, /* /< SCE WRRDY 1 */
FSP_SIGNAL_SCE_WRRDY_4, /* /< SCE WRRDY 4 */
FSP_SIGNAL_SCI_AM = 0, /* /< SCI AM */
FSP_SIGNAL_SCI_ERI, /* /< SCI ERI */
FSP_SIGNAL_SCI_RXI, /* /< SCI RXI */
FSP_SIGNAL_SCI_RXI_OR_ERI, /* /< SCI RXI OR ERI */
FSP_SIGNAL_SCI_TEI, /* /< SCI TEI */
FSP_SIGNAL_SCI_TXI, /* /< SCI TXI */
FSP_SIGNAL_SDADC_ADI = 0, /* /< SDADC ADI */
FSP_SIGNAL_SDADC_SCANEND, /* /< SDADC SCANEND */
FSP_SIGNAL_SDADC_CALIEND, /* /< SDADC CALIEND */
FSP_SIGNAL_SDHIMMC_ACCS = 0, /* /< SDHIMMC ACCS */
FSP_SIGNAL_SDHIMMC_CARD, /* /< SDHIMMC CARD */
FSP_SIGNAL_SDHIMMC_DMA_REQ, /* /< SDHIMMC DMA REQ */
FSP_SIGNAL_SDHIMMC_SDIO, /* /< SDHIMMC SDIO */
FSP_SIGNAL_SPI_ERI = 0, /* /< SPI ERI */
FSP_SIGNAL_SPI_IDLE, /* /< SPI IDLE */
FSP_SIGNAL_SPI_RXI, /* /< SPI RXI */
FSP_SIGNAL_SPI_TEI, /* /< SPI TEI */
FSP_SIGNAL_SPI_TXI, /* /< SPI TXI */
FSP_SIGNAL_SRC_CONVERSION_END = 0, /* /< SRC CONVERSION END */
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, /* /< SRC INPUT FIFO EMPTY */
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, /* /< SRC OUTPUT FIFO FULL */
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, /* /< SRC OUTPUT FIFO OVERFLOW */
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, /* /< SRC OUTPUT FIFO UNDERFLOW */
FSP_SIGNAL_SSI_INT = 0, /* /< SSI INT */
FSP_SIGNAL_SSI_RXI, /* /< SSI RXI */
FSP_SIGNAL_SSI_TXI, /* /< SSI TXI */
FSP_SIGNAL_SSI_TXI_RXI, /* /< SSI TXI RXI */
FSP_SIGNAL_TRNG_RDREQ = 0, /* /< TRNG RDREQ */
FSP_SIGNAL_USB_FIFO_0 = 0, /* /< USB FIFO 0 */
FSP_SIGNAL_USB_FIFO_1, /* /< USB FIFO 1 */
FSP_SIGNAL_USB_INT, /* /< USB INT */
FSP_SIGNAL_USB_RESUME, /* /< USB RESUME */
FSP_SIGNAL_USB_USB_INT_RESUME, /* /< USB USB INT RESUME */
FSP_SIGNAL_WDT_UNDERFLOW = 0, /* /< WDT UNDERFLOW */
FSP_SIGNAL_ULPT_COMPARE_A = 0, /* /< ULPT COMPARE A */
FSP_SIGNAL_ULPT_COMPARE_B, /* /< ULPT COMPARE B */
FSP_SIGNAL_ULPT_INT, /* /< ULPT INT */
} fsp_signal_t;
typedef void (* fsp_vector_t)(void);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (5U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (9U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("5.9.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 5.9.0")
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** FSP Pack version structure */
typedef union st_fsp_pack_version
{
/** Version id */
uint32_t version_id;
/**
* Code version parameters, little endian order.
*/
struct version_id_b_s
{
uint8_t build; /* /< Build version of FSP Pack */
uint8_t patch; /* /< Patch version of FSP Pack */
uint8_t minor; /* /< Minor version of FSP Pack */
uint8_t major; /* /< Major version of FSP Pack */
} version_id_b;
} fsp_pack_version_t;
/** @} */
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_H
#define R_IOPORT_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "r_ioport_api.h"
#if __has_include("r_ioport_cfg.h")
#include "r_ioport_cfg.h"
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Private definition to set enumeration values. */
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
typedef struct st_ioport_instance_ctrl
{
uint32_t open;
void const * p_context;
} ioport_instance_ctrl_t;
/* This typedef is here temporarily. See SWFLEX-144 for details. */
/** Superset list of all possible IO port pins. */
typedef enum e_ioport_port_pin_t
{
IOPORT_PORT_00_PIN_00 = 0x0000, /* /< IO port 0 pin 0 */
IOPORT_PORT_00_PIN_01 = 0x0001, /* /< IO port 0 pin 1 */
IOPORT_PORT_00_PIN_02 = 0x0002, /* /< IO port 0 pin 2 */
IOPORT_PORT_00_PIN_03 = 0x0003, /* /< IO port 0 pin 3 */
IOPORT_PORT_00_PIN_04 = 0x0004, /* /< IO port 0 pin 4 */
IOPORT_PORT_00_PIN_05 = 0x0005, /* /< IO port 0 pin 5 */
IOPORT_PORT_00_PIN_06 = 0x0006, /* /< IO port 0 pin 6 */
IOPORT_PORT_00_PIN_07 = 0x0007, /* /< IO port 0 pin 7 */
IOPORT_PORT_00_PIN_08 = 0x0008, /* /< IO port 0 pin 8 */
IOPORT_PORT_00_PIN_09 = 0x0009, /* /< IO port 0 pin 9 */
IOPORT_PORT_00_PIN_10 = 0x000A, /* /< IO port 0 pin 10 */
IOPORT_PORT_00_PIN_11 = 0x000B, /* /< IO port 0 pin 11 */
IOPORT_PORT_00_PIN_12 = 0x000C, /* /< IO port 0 pin 12 */
IOPORT_PORT_00_PIN_13 = 0x000D, /* /< IO port 0 pin 13 */
IOPORT_PORT_00_PIN_14 = 0x000E, /* /< IO port 0 pin 14 */
IOPORT_PORT_00_PIN_15 = 0x000F, /* /< IO port 0 pin 15 */
IOPORT_PORT_01_PIN_00 = 0x0100, /* /< IO port 1 pin 0 */
IOPORT_PORT_01_PIN_01 = 0x0101, /* /< IO port 1 pin 1 */
IOPORT_PORT_01_PIN_02 = 0x0102, /* /< IO port 1 pin 2 */
IOPORT_PORT_01_PIN_03 = 0x0103, /* /< IO port 1 pin 3 */
IOPORT_PORT_01_PIN_04 = 0x0104, /* /< IO port 1 pin 4 */
IOPORT_PORT_01_PIN_05 = 0x0105, /* /< IO port 1 pin 5 */
IOPORT_PORT_01_PIN_06 = 0x0106, /* /< IO port 1 pin 6 */
IOPORT_PORT_01_PIN_07 = 0x0107, /* /< IO port 1 pin 7 */
IOPORT_PORT_01_PIN_08 = 0x0108, /* /< IO port 1 pin 8 */
IOPORT_PORT_01_PIN_09 = 0x0109, /* /< IO port 1 pin 9 */
IOPORT_PORT_01_PIN_10 = 0x010A, /* /< IO port 1 pin 10 */
IOPORT_PORT_01_PIN_11 = 0x010B, /* /< IO port 1 pin 11 */
IOPORT_PORT_01_PIN_12 = 0x010C, /* /< IO port 1 pin 12 */
IOPORT_PORT_01_PIN_13 = 0x010D, /* /< IO port 1 pin 13 */
IOPORT_PORT_01_PIN_14 = 0x010E, /* /< IO port 1 pin 14 */
IOPORT_PORT_01_PIN_15 = 0x010F, /* /< IO port 1 pin 15 */
IOPORT_PORT_02_PIN_00 = 0x0200, /* /< IO port 2 pin 0 */
IOPORT_PORT_02_PIN_01 = 0x0201, /* /< IO port 2 pin 1 */
IOPORT_PORT_02_PIN_02 = 0x0202, /* /< IO port 2 pin 2 */
IOPORT_PORT_02_PIN_03 = 0x0203, /* /< IO port 2 pin 3 */
IOPORT_PORT_02_PIN_04 = 0x0204, /* /< IO port 2 pin 4 */
IOPORT_PORT_02_PIN_05 = 0x0205, /* /< IO port 2 pin 5 */
IOPORT_PORT_02_PIN_06 = 0x0206, /* /< IO port 2 pin 6 */
IOPORT_PORT_02_PIN_07 = 0x0207, /* /< IO port 2 pin 7 */
IOPORT_PORT_02_PIN_08 = 0x0208, /* /< IO port 2 pin 8 */
IOPORT_PORT_02_PIN_09 = 0x0209, /* /< IO port 2 pin 9 */
IOPORT_PORT_02_PIN_10 = 0x020A, /* /< IO port 2 pin 10 */
IOPORT_PORT_02_PIN_11 = 0x020B, /* /< IO port 2 pin 11 */
IOPORT_PORT_02_PIN_12 = 0x020C, /* /< IO port 2 pin 12 */
IOPORT_PORT_02_PIN_13 = 0x020D, /* /< IO port 2 pin 13 */
IOPORT_PORT_02_PIN_14 = 0x020E, /* /< IO port 2 pin 14 */
IOPORT_PORT_02_PIN_15 = 0x020F, /* /< IO port 2 pin 15 */
IOPORT_PORT_03_PIN_00 = 0x0300, /* /< IO port 3 pin 0 */
IOPORT_PORT_03_PIN_01 = 0x0301, /* /< IO port 3 pin 1 */
IOPORT_PORT_03_PIN_02 = 0x0302, /* /< IO port 3 pin 2 */
IOPORT_PORT_03_PIN_03 = 0x0303, /* /< IO port 3 pin 3 */
IOPORT_PORT_03_PIN_04 = 0x0304, /* /< IO port 3 pin 4 */
IOPORT_PORT_03_PIN_05 = 0x0305, /* /< IO port 3 pin 5 */
IOPORT_PORT_03_PIN_06 = 0x0306, /* /< IO port 3 pin 6 */
IOPORT_PORT_03_PIN_07 = 0x0307, /* /< IO port 3 pin 7 */
IOPORT_PORT_03_PIN_08 = 0x0308, /* /< IO port 3 pin 8 */
IOPORT_PORT_03_PIN_09 = 0x0309, /* /< IO port 3 pin 9 */
IOPORT_PORT_03_PIN_10 = 0x030A, /* /< IO port 3 pin 10 */
IOPORT_PORT_03_PIN_11 = 0x030B, /* /< IO port 3 pin 11 */
IOPORT_PORT_03_PIN_12 = 0x030C, /* /< IO port 3 pin 12 */
IOPORT_PORT_03_PIN_13 = 0x030D, /* /< IO port 3 pin 13 */
IOPORT_PORT_03_PIN_14 = 0x030E, /* /< IO port 3 pin 14 */
IOPORT_PORT_03_PIN_15 = 0x030F, /* /< IO port 3 pin 15 */
IOPORT_PORT_04_PIN_00 = 0x0400, /* /< IO port 4 pin 0 */
IOPORT_PORT_04_PIN_01 = 0x0401, /* /< IO port 4 pin 1 */
IOPORT_PORT_04_PIN_02 = 0x0402, /* /< IO port 4 pin 2 */
IOPORT_PORT_04_PIN_03 = 0x0403, /* /< IO port 4 pin 3 */
IOPORT_PORT_04_PIN_04 = 0x0404, /* /< IO port 4 pin 4 */
IOPORT_PORT_04_PIN_05 = 0x0405, /* /< IO port 4 pin 5 */
IOPORT_PORT_04_PIN_06 = 0x0406, /* /< IO port 4 pin 6 */
IOPORT_PORT_04_PIN_07 = 0x0407, /* /< IO port 4 pin 7 */
IOPORT_PORT_04_PIN_08 = 0x0408, /* /< IO port 4 pin 8 */
IOPORT_PORT_04_PIN_09 = 0x0409, /* /< IO port 4 pin 9 */
IOPORT_PORT_04_PIN_10 = 0x040A, /* /< IO port 4 pin 10 */
IOPORT_PORT_04_PIN_11 = 0x040B, /* /< IO port 4 pin 11 */
IOPORT_PORT_04_PIN_12 = 0x040C, /* /< IO port 4 pin 12 */
IOPORT_PORT_04_PIN_13 = 0x040D, /* /< IO port 4 pin 13 */
IOPORT_PORT_04_PIN_14 = 0x040E, /* /< IO port 4 pin 14 */
IOPORT_PORT_04_PIN_15 = 0x040F, /* /< IO port 4 pin 15 */
IOPORT_PORT_05_PIN_00 = 0x0500, /* /< IO port 5 pin 0 */
IOPORT_PORT_05_PIN_01 = 0x0501, /* /< IO port 5 pin 1 */
IOPORT_PORT_05_PIN_02 = 0x0502, /* /< IO port 5 pin 2 */
IOPORT_PORT_05_PIN_03 = 0x0503, /* /< IO port 5 pin 3 */
IOPORT_PORT_05_PIN_04 = 0x0504, /* /< IO port 5 pin 4 */
IOPORT_PORT_05_PIN_05 = 0x0505, /* /< IO port 5 pin 5 */
IOPORT_PORT_05_PIN_06 = 0x0506, /* /< IO port 5 pin 6 */
IOPORT_PORT_05_PIN_07 = 0x0507, /* /< IO port 5 pin 7 */
IOPORT_PORT_05_PIN_08 = 0x0508, /* /< IO port 5 pin 8 */
IOPORT_PORT_05_PIN_09 = 0x0509, /* /< IO port 5 pin 9 */
IOPORT_PORT_05_PIN_10 = 0x050A, /* /< IO port 5 pin 10 */
IOPORT_PORT_05_PIN_11 = 0x050B, /* /< IO port 5 pin 11 */
IOPORT_PORT_05_PIN_12 = 0x050C, /* /< IO port 5 pin 12 */
IOPORT_PORT_05_PIN_13 = 0x050D, /* /< IO port 5 pin 13 */
IOPORT_PORT_05_PIN_14 = 0x050E, /* /< IO port 5 pin 14 */
IOPORT_PORT_05_PIN_15 = 0x050F, /* /< IO port 5 pin 15 */
IOPORT_PORT_06_PIN_00 = 0x0600, /* /< IO port 6 pin 0 */
IOPORT_PORT_06_PIN_01 = 0x0601, /* /< IO port 6 pin 1 */
IOPORT_PORT_06_PIN_02 = 0x0602, /* /< IO port 6 pin 2 */
IOPORT_PORT_06_PIN_03 = 0x0603, /* /< IO port 6 pin 3 */
IOPORT_PORT_06_PIN_04 = 0x0604, /* /< IO port 6 pin 4 */
IOPORT_PORT_06_PIN_05 = 0x0605, /* /< IO port 6 pin 5 */
IOPORT_PORT_06_PIN_06 = 0x0606, /* /< IO port 6 pin 6 */
IOPORT_PORT_06_PIN_07 = 0x0607, /* /< IO port 6 pin 7 */
IOPORT_PORT_06_PIN_08 = 0x0608, /* /< IO port 6 pin 8 */
IOPORT_PORT_06_PIN_09 = 0x0609, /* /< IO port 6 pin 9 */
IOPORT_PORT_06_PIN_10 = 0x060A, /* /< IO port 6 pin 10 */
IOPORT_PORT_06_PIN_11 = 0x060B, /* /< IO port 6 pin 11 */
IOPORT_PORT_06_PIN_12 = 0x060C, /* /< IO port 6 pin 12 */
IOPORT_PORT_06_PIN_13 = 0x060D, /* /< IO port 6 pin 13 */
IOPORT_PORT_06_PIN_14 = 0x060E, /* /< IO port 6 pin 14 */
IOPORT_PORT_06_PIN_15 = 0x060F, /* /< IO port 6 pin 15 */
IOPORT_PORT_07_PIN_00 = 0x0700, /* /< IO port 7 pin 0 */
IOPORT_PORT_07_PIN_01 = 0x0701, /* /< IO port 7 pin 1 */
IOPORT_PORT_07_PIN_02 = 0x0702, /* /< IO port 7 pin 2 */
IOPORT_PORT_07_PIN_03 = 0x0703, /* /< IO port 7 pin 3 */
IOPORT_PORT_07_PIN_04 = 0x0704, /* /< IO port 7 pin 4 */
IOPORT_PORT_07_PIN_05 = 0x0705, /* /< IO port 7 pin 5 */
IOPORT_PORT_07_PIN_06 = 0x0706, /* /< IO port 7 pin 6 */
IOPORT_PORT_07_PIN_07 = 0x0707, /* /< IO port 7 pin 7 */
IOPORT_PORT_07_PIN_08 = 0x0708, /* /< IO port 7 pin 8 */
IOPORT_PORT_07_PIN_09 = 0x0709, /* /< IO port 7 pin 9 */
IOPORT_PORT_07_PIN_10 = 0x070A, /* /< IO port 7 pin 10 */
IOPORT_PORT_07_PIN_11 = 0x070B, /* /< IO port 7 pin 11 */
IOPORT_PORT_07_PIN_12 = 0x070C, /* /< IO port 7 pin 12 */
IOPORT_PORT_07_PIN_13 = 0x070D, /* /< IO port 7 pin 13 */
IOPORT_PORT_07_PIN_14 = 0x070E, /* /< IO port 7 pin 14 */
IOPORT_PORT_07_PIN_15 = 0x070F, /* /< IO port 7 pin 15 */
IOPORT_PORT_08_PIN_00 = 0x0800, /* /< IO port 8 pin 0 */
IOPORT_PORT_08_PIN_01 = 0x0801, /* /< IO port 8 pin 1 */
IOPORT_PORT_08_PIN_02 = 0x0802, /* /< IO port 8 pin 2 */
IOPORT_PORT_08_PIN_03 = 0x0803, /* /< IO port 8 pin 3 */
IOPORT_PORT_08_PIN_04 = 0x0804, /* /< IO port 8 pin 4 */
IOPORT_PORT_08_PIN_05 = 0x0805, /* /< IO port 8 pin 5 */
IOPORT_PORT_08_PIN_06 = 0x0806, /* /< IO port 8 pin 6 */
IOPORT_PORT_08_PIN_07 = 0x0807, /* /< IO port 8 pin 7 */
IOPORT_PORT_08_PIN_08 = 0x0808, /* /< IO port 8 pin 8 */
IOPORT_PORT_08_PIN_09 = 0x0809, /* /< IO port 8 pin 9 */
IOPORT_PORT_08_PIN_10 = 0x080A, /* /< IO port 8 pin 10 */
IOPORT_PORT_08_PIN_11 = 0x080B, /* /< IO port 8 pin 11 */
IOPORT_PORT_08_PIN_12 = 0x080C, /* /< IO port 8 pin 12 */
IOPORT_PORT_08_PIN_13 = 0x080D, /* /< IO port 8 pin 13 */
IOPORT_PORT_08_PIN_14 = 0x080E, /* /< IO port 8 pin 14 */
IOPORT_PORT_08_PIN_15 = 0x080F, /* /< IO port 8 pin 15 */
IOPORT_PORT_09_PIN_00 = 0x0900, /* /< IO port 9 pin 0 */
IOPORT_PORT_09_PIN_01 = 0x0901, /* /< IO port 9 pin 1 */
IOPORT_PORT_09_PIN_02 = 0x0902, /* /< IO port 9 pin 2 */
IOPORT_PORT_09_PIN_03 = 0x0903, /* /< IO port 9 pin 3 */
IOPORT_PORT_09_PIN_04 = 0x0904, /* /< IO port 9 pin 4 */
IOPORT_PORT_09_PIN_05 = 0x0905, /* /< IO port 9 pin 5 */
IOPORT_PORT_09_PIN_06 = 0x0906, /* /< IO port 9 pin 6 */
IOPORT_PORT_09_PIN_07 = 0x0907, /* /< IO port 9 pin 7 */
IOPORT_PORT_09_PIN_08 = 0x0908, /* /< IO port 9 pin 8 */
IOPORT_PORT_09_PIN_09 = 0x0909, /* /< IO port 9 pin 9 */
IOPORT_PORT_09_PIN_10 = 0x090A, /* /< IO port 9 pin 10 */
IOPORT_PORT_09_PIN_11 = 0x090B, /* /< IO port 9 pin 11 */
IOPORT_PORT_09_PIN_12 = 0x090C, /* /< IO port 9 pin 12 */
IOPORT_PORT_09_PIN_13 = 0x090D, /* /< IO port 9 pin 13 */
IOPORT_PORT_09_PIN_14 = 0x090E, /* /< IO port 9 pin 14 */
IOPORT_PORT_09_PIN_15 = 0x090F, /* /< IO port 9 pin 15 */
IOPORT_PORT_10_PIN_00 = 0x0A00, /* /< IO port 10 pin 0 */
IOPORT_PORT_10_PIN_01 = 0x0A01, /* /< IO port 10 pin 1 */
IOPORT_PORT_10_PIN_02 = 0x0A02, /* /< IO port 10 pin 2 */
IOPORT_PORT_10_PIN_03 = 0x0A03, /* /< IO port 10 pin 3 */
IOPORT_PORT_10_PIN_04 = 0x0A04, /* /< IO port 10 pin 4 */
IOPORT_PORT_10_PIN_05 = 0x0A05, /* /< IO port 10 pin 5 */
IOPORT_PORT_10_PIN_06 = 0x0A06, /* /< IO port 10 pin 6 */
IOPORT_PORT_10_PIN_07 = 0x0A07, /* /< IO port 10 pin 7 */
IOPORT_PORT_10_PIN_08 = 0x0A08, /* /< IO port 10 pin 8 */
IOPORT_PORT_10_PIN_09 = 0x0A09, /* /< IO port 10 pin 9 */
IOPORT_PORT_10_PIN_10 = 0x0A0A, /* /< IO port 10 pin 10 */
IOPORT_PORT_10_PIN_11 = 0x0A0B, /* /< IO port 10 pin 11 */
IOPORT_PORT_10_PIN_12 = 0x0A0C, /* /< IO port 10 pin 12 */
IOPORT_PORT_10_PIN_13 = 0x0A0D, /* /< IO port 10 pin 13 */
IOPORT_PORT_10_PIN_14 = 0x0A0E, /* /< IO port 10 pin 14 */
IOPORT_PORT_10_PIN_15 = 0x0A0F, /* /< IO port 10 pin 15 */
IOPORT_PORT_11_PIN_00 = 0x0B00, /* /< IO port 11 pin 0 */
IOPORT_PORT_11_PIN_01 = 0x0B01, /* /< IO port 11 pin 1 */
IOPORT_PORT_11_PIN_02 = 0x0B02, /* /< IO port 11 pin 2 */
IOPORT_PORT_11_PIN_03 = 0x0B03, /* /< IO port 11 pin 3 */
IOPORT_PORT_11_PIN_04 = 0x0B04, /* /< IO port 11 pin 4 */
IOPORT_PORT_11_PIN_05 = 0x0B05, /* /< IO port 11 pin 5 */
IOPORT_PORT_11_PIN_06 = 0x0B06, /* /< IO port 11 pin 6 */
IOPORT_PORT_11_PIN_07 = 0x0B07, /* /< IO port 11 pin 7 */
IOPORT_PORT_11_PIN_08 = 0x0B08, /* /< IO port 11 pin 8 */
IOPORT_PORT_11_PIN_09 = 0x0B09, /* /< IO port 11 pin 9 */
IOPORT_PORT_11_PIN_10 = 0x0B0A, /* /< IO port 11 pin 10 */
IOPORT_PORT_11_PIN_11 = 0x0B0B, /* /< IO port 11 pin 11 */
IOPORT_PORT_11_PIN_12 = 0x0B0C, /* /< IO port 11 pin 12 */
IOPORT_PORT_11_PIN_13 = 0x0B0D, /* /< IO port 11 pin 13 */
IOPORT_PORT_11_PIN_14 = 0x0B0E, /* /< IO port 11 pin 14 */
IOPORT_PORT_11_PIN_15 = 0x0B0F, /* /< IO port 11 pin 15 */
IOPORT_PORT_12_PIN_00 = 0x0C00, /* /< IO port 12 pin 0 */
IOPORT_PORT_12_PIN_01 = 0x0C01, /* /< IO port 12 pin 1 */
IOPORT_PORT_12_PIN_02 = 0x0C02, /* /< IO port 12 pin 2 */
IOPORT_PORT_12_PIN_03 = 0x0C03, /* /< IO port 12 pin 3 */
IOPORT_PORT_12_PIN_04 = 0x0C04, /* /< IO port 12 pin 4 */
IOPORT_PORT_12_PIN_05 = 0x0C05, /* /< IO port 12 pin 5 */
IOPORT_PORT_12_PIN_06 = 0x0C06, /* /< IO port 12 pin 6 */
IOPORT_PORT_12_PIN_07 = 0x0C07, /* /< IO port 12 pin 7 */
IOPORT_PORT_12_PIN_08 = 0x0C08, /* /< IO port 12 pin 8 */
IOPORT_PORT_12_PIN_09 = 0x0C09, /* /< IO port 12 pin 9 */
IOPORT_PORT_12_PIN_10 = 0x0C0A, /* /< IO port 12 pin 10 */
IOPORT_PORT_12_PIN_11 = 0x0C0B, /* /< IO port 12 pin 11 */
IOPORT_PORT_12_PIN_12 = 0x0C0C, /* /< IO port 12 pin 12 */
IOPORT_PORT_12_PIN_13 = 0x0C0D, /* /< IO port 12 pin 13 */
IOPORT_PORT_12_PIN_14 = 0x0C0E, /* /< IO port 12 pin 14 */
IOPORT_PORT_12_PIN_15 = 0x0C0F, /* /< IO port 12 pin 15 */
IOPORT_PORT_13_PIN_00 = 0x0D00, /* /< IO port 13 pin 0 */
IOPORT_PORT_13_PIN_01 = 0x0D01, /* /< IO port 13 pin 1 */
IOPORT_PORT_13_PIN_02 = 0x0D02, /* /< IO port 13 pin 2 */
IOPORT_PORT_13_PIN_03 = 0x0D03, /* /< IO port 13 pin 3 */
IOPORT_PORT_13_PIN_04 = 0x0D04, /* /< IO port 13 pin 4 */
IOPORT_PORT_13_PIN_05 = 0x0D05, /* /< IO port 13 pin 5 */
IOPORT_PORT_13_PIN_06 = 0x0D06, /* /< IO port 13 pin 6 */
IOPORT_PORT_13_PIN_07 = 0x0D07, /* /< IO port 13 pin 7 */
IOPORT_PORT_13_PIN_08 = 0x0D08, /* /< IO port 13 pin 8 */
IOPORT_PORT_13_PIN_09 = 0x0D09, /* /< IO port 13 pin 9 */
IOPORT_PORT_13_PIN_10 = 0x0D0A, /* /< IO port 13 pin 10 */
IOPORT_PORT_13_PIN_11 = 0x0D0B, /* /< IO port 13 pin 11 */
IOPORT_PORT_13_PIN_12 = 0x0D0C, /* /< IO port 13 pin 12 */
IOPORT_PORT_13_PIN_13 = 0x0D0D, /* /< IO port 13 pin 13 */
IOPORT_PORT_13_PIN_14 = 0x0D0E, /* /< IO port 13 pin 14 */
IOPORT_PORT_13_PIN_15 = 0x0D0F, /* /< IO port 13 pin 15 */
IOPORT_PORT_14_PIN_00 = 0x0E00, /* /< IO port 14 pin 0 */
IOPORT_PORT_14_PIN_01 = 0x0E01, /* /< IO port 14 pin 1 */
IOPORT_PORT_14_PIN_02 = 0x0E02, /* /< IO port 14 pin 2 */
IOPORT_PORT_14_PIN_03 = 0x0E03, /* /< IO port 14 pin 3 */
IOPORT_PORT_14_PIN_04 = 0x0E04, /* /< IO port 14 pin 4 */
IOPORT_PORT_14_PIN_05 = 0x0E05, /* /< IO port 14 pin 5 */
IOPORT_PORT_14_PIN_06 = 0x0E06, /* /< IO port 14 pin 6 */
IOPORT_PORT_14_PIN_07 = 0x0E07, /* /< IO port 14 pin 7 */
IOPORT_PORT_14_PIN_08 = 0x0E08, /* /< IO port 14 pin 8 */
IOPORT_PORT_14_PIN_09 = 0x0E09, /* /< IO port 14 pin 9 */
IOPORT_PORT_14_PIN_10 = 0x0E0A, /* /< IO port 14 pin 10 */
IOPORT_PORT_14_PIN_11 = 0x0E0B, /* /< IO port 14 pin 11 */
IOPORT_PORT_14_PIN_12 = 0x0E0C, /* /< IO port 14 pin 12 */
IOPORT_PORT_14_PIN_13 = 0x0E0D, /* /< IO port 14 pin 13 */
IOPORT_PORT_14_PIN_14 = 0x0E0E, /* /< IO port 14 pin 14 */
IOPORT_PORT_14_PIN_15 = 0x0E0F, /* /< IO port 14 pin 15 */
} ioport_port_pin_t;
#ifndef BSP_OVERRIDE_IOPORT_PERIPHERAL_T
/** Superset of all peripheral functions. */
typedef enum e_ioport_peripheral
{
/** Pin will functions as an IO pin */
IOPORT_PERIPHERAL_IO = 0x00,
/** Pin will function as a DEBUG pin */
IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an AGT peripheral pin */
IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI peripheral pin */
IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a SPI peripheral pin */
IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a IIC peripheral pin */
IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a KEY peripheral pin */
IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a clock/comparator/RTC peripheral pin */
IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAC/ADC peripheral pin */
IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a BUS peripheral pin */
IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CTSU peripheral pin */
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CMPHS peripheral pin */
IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a segment LCD peripheral pin */
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#if BSP_FEATURE_SCI_UART_DE_IS_INVERTED
/** Pin will function as an SCI peripheral DEn pin */
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#else
/** Pin will function as an SCI peripheral DEn pin */
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SCI DEn peripheral pin */
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
#endif
/** Pin will function as a DALI peripheral pin */
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CEU peripheral pin */
IOPORT_PERIPHERAL_CEU = (0x0FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAN peripheral pin */
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a QSPI peripheral pin */
IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SSI peripheral pin */
IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB full speed peripheral pin */
IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a USB high speed peripheral pin */
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an SD/MMC peripheral pin */
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet MMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a GPT peripheral pin */
IOPORT_PERIPHERAL_GPT5 = (0x1BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an Ethernet RMMI peripheral pin */
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PDC peripheral pin */
IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a graphics LCD peripheral pin */
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CAC peripheral pin */
IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a debug trace peripheral pin */
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a OSPI peripheral pin */
IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a CEC peripheral pin */
IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a PGAOUT peripheral pin */
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a ULPT peripheral pin */
IOPORT_PERIPHERAL_ULPT = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as a MIPI DSI peripheral pin */
IOPORT_PERIPHERAL_MIPI = (0x1FUL << IOPORT_PRV_PFS_PSEL_OFFSET),
/** Pin will function as an UARTA peripheral pin */
IOPORT_PERIPHERAL_UARTA = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
} ioport_peripheral_t;
#endif
#ifndef BSP_OVERRIDE_IOPORT_CFG_OPTIONS_T
/** Options to configure pin functions */
typedef enum e_ioport_cfg_options
{
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, /* /< Sets the pin direction to input (default) */
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, /* /< Sets the pin direction to output */
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, /* /< Sets the pin level to low */
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, /* /< Sets the pin level to high */
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, /* /< Enables the pin's internal pull-up */
IOPORT_CFG_PIM_TTL = 0x00000020, /* /< Enables the pin's input mode */
IOPORT_CFG_NMOS_ENABLE = 0x00000040, /* /< Enables the pin's NMOS open-drain output */
IOPORT_CFG_PMOS_ENABLE = 0x00000080, /* /< Enables the pin's PMOS open-drain ouput */
IOPORT_CFG_DRIVE_MID = 0x00000400, /* /< Sets pin drive output to medium */
IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, /* /< Sets pin drive output to high along with supporting high speed */
IOPORT_CFG_DRIVE_MID_IIC = 0x00000800, /* /< Sets pin to drive output needed for IIC on a 20mA port */
IOPORT_CFG_DRIVE_HIGH = 0x00000C00, /* /< Sets pin drive output to high */
IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, /* /< Sets pin event trigger to rising edge */
IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, /* /< Sets pin event trigger to falling edge */
IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, /* /< Sets pin event trigger to both edges */
IOPORT_CFG_IRQ_ENABLE = 0x00004000, /* /< Sets pin as an IRQ pin */
IOPORT_CFG_ANALOG_ENABLE = 0x00008000, /* /< Enables pin to operate as an analog pin */
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 /* /< Enables pin to operate as a peripheral pin */
} ioport_cfg_options_t;
#endif
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const ioport_api_t g_ioport_on_ioport;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask);
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif /* R_IOPORT_H */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef R_SCI_UART_H
#define R_SCI_UART_H
/*******************************************************************************************************************//**
* @addtogroup SCI_UART
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_uart_api.h"
#include "r_sci_uart_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Enumeration for SCI clock source */
typedef enum e_sci_clk_src
{
SCI_UART_CLOCK_INT, /* /< Use internal clock for baud generation */
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, /* /< Use internal clock for baud generation and output on SCK */
SCI_UART_CLOCK_EXT8X, /* /< Use external clock 8x baud rate */
SCI_UART_CLOCK_EXT16X /* /< Use external clock 16x baud rate */
} sci_clk_src_t;
/** UART flow control mode definition */
typedef enum e_sci_uart_flow_control
{
SCI_UART_FLOW_CONTROL_RTS = 0U, /* /< Use SCI pin for RTS */
SCI_UART_FLOW_CONTROL_CTS = 1U, /* /< Use SCI pin for CTS */
SCI_UART_FLOW_CONTROL_CTSRTS = 3U, /* /< Use SCI pin for CTS, external pin for RTS */
SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, /* /< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options */
} sci_uart_flow_control_t;
/** UART instance control block. */
typedef struct st_sci_uart_instance_ctrl
{
/* Parameters to control UART peripheral device */
uint8_t fifo_depth; /* FIFO depth of the UART channel */
uint8_t rx_transfer_in_progress; /* Set to 1 if a receive transfer is in progress, 0 otherwise */
uint8_t data_bytes : 2; /* 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data */
uint8_t bitrate_modulation : 1; /* 1 if bit rate modulation is enabled, 0 otherwise */
uint32_t open; /* Used to determine if the channel is configured */
bsp_io_port_pin_t flow_pin;
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint8_t const * p_tx_src;
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint32_t tx_src_bytes;
/* Destination buffer pointer used for receiving data. */
uint8_t const * p_rx_dest;
/* Size of destination buffer pointer used for receiving data. */
uint32_t rx_dest_bytes;
/* Pointer to the configuration block. */
uart_cfg_t const * p_cfg;
/* Base register for this channel */
R_SCI0_Type * p_reg;
void (* p_callback)(uart_callback_args_t *); /* Pointer to callback that is called when a uart_event_t occurs. */
uart_callback_args_t * p_callback_memory; /* Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. */
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_uart_instance_ctrl_t;
/** Receive FIFO trigger configuration. */
typedef enum e_sci_uart_rx_fifo_trigger
{
SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, /* /< Callback after each byte is received without buffering */
SCI_UART_RX_FIFO_TRIGGER_2 = 0x2, /* /< Callback when FIFO having 2 bytes */
SCI_UART_RX_FIFO_TRIGGER_3 = 0x3, /* /< Callback when FIFO having 3 bytes */
SCI_UART_RX_FIFO_TRIGGER_4 = 0x4, /* /< Callback when FIFO having 4 bytes */
SCI_UART_RX_FIFO_TRIGGER_5 = 0x5, /* /< Callback when FIFO having 5 bytes */
SCI_UART_RX_FIFO_TRIGGER_6 = 0x6, /* /< Callback when FIFO having 6 bytes */
SCI_UART_RX_FIFO_TRIGGER_7 = 0x7, /* /< Callback when FIFO having 7 bytes */
SCI_UART_RX_FIFO_TRIGGER_8 = 0x8, /* /< Callback when FIFO having 8 bytes */
SCI_UART_RX_FIFO_TRIGGER_9 = 0x9, /* /< Callback when FIFO having 9 bytes */
SCI_UART_RX_FIFO_TRIGGER_10 = 0xA, /* /< Callback when FIFO having 10 bytes */
SCI_UART_RX_FIFO_TRIGGER_11 = 0xB, /* /< Callback when FIFO having 11 bytes */
SCI_UART_RX_FIFO_TRIGGER_12 = 0xC, /* /< Callback when FIFO having 12 bytes */
SCI_UART_RX_FIFO_TRIGGER_13 = 0xD, /* /< Callback when FIFO having 13 bytes */
SCI_UART_RX_FIFO_TRIGGER_14 = 0xE, /* /< Callback when FIFO having 14 bytes */
SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, /* /< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) */
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_uart_start_bit_t
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, /* /< Detect low level on RXDn pin as start bit */
SCI_UART_START_BIT_FALLING_EDGE = 0x1, /* /< Detect falling level on RXDn pin as start bit */
} sci_uart_start_bit_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
{
SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, /* /< Disable noise cancellation */
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, /* /< Enable noise cancellation */
} sci_uart_noise_cancellation_t;
/** RS-485 Enable/Disable. */
typedef enum e_sci_uart_rs485_enable
{
SCI_UART_RS485_DISABLE = 0, /* /< RS-485 disabled. */
SCI_UART_RS485_ENABLE = 1, /* /< RS-485 enabled. */
} sci_uart_rs485_enable_t;
/** The polarity of the RS-485 DE signal. */
typedef enum e_sci_uart_rs485_de_polarity
{
SCI_UART_RS485_DE_POLARITY_HIGH = 0, /* /< The DE signal is high when a write transfer is in progress. */
SCI_UART_RS485_DE_POLARITY_LOW = 1, /* /< The DE signal is low when a write transfer is in progress. */
} sci_uart_rs485_de_polarity_t;
/** Register settings to acheive a desired baud rate and modulation duty. */
typedef struct st_baud_setting_t
{
union
{
uint8_t semr_baudrate_bits;
struct
{
uint8_t : 2;
uint8_t brme : 1; /* /< Bit Rate Modulation Enable */
uint8_t abcse : 1; /* /< Asynchronous Mode Extended Base Clock Select 1 */
uint8_t abcs : 1; /* /< Asynchronous Mode Base Clock Select */
uint8_t : 1;
uint8_t bgdm : 1; /* /< Baud Rate Generator Double-Speed Mode Select */
uint8_t : 1;
} semr_baudrate_bits_b;
};
uint8_t cks : 2; /* /< CKS value to get divisor (CKS = N) */
uint8_t brr; /* /< Bit Rate Register setting */
uint8_t mddr; /* /< Modulation Duty Register setting */
} baud_setting_t;
/** Configuration settings for controlling the DE signal for RS-485. */
typedef struct st_sci_uart_rs485_setting
{
sci_uart_rs485_enable_t enable; /* /< Enable the DE signal. */
sci_uart_rs485_de_polarity_t polarity; /* /< DE signal polarity. */
bsp_io_port_pin_t de_control_pin; /* /< UART Driver Enable pin. */
} sci_uart_rs485_setting_t;
/** IrDA Enable/Disable. */
typedef enum e_sci_uart_irda_enable
{
SCI_UART_IRDA_DISABLED = 0, /* /< IrDA disabled. */
SCI_UART_IRDA_ENABLED = 1, /* /< IrDA enabled. */
} sci_uart_irda_enable_t;
/** IrDA Polarity Switching. */
typedef enum e_sci_uart_irda_polarity
{
SCI_UART_IRDA_POLARITY_NORMAL = 0, /* /< IrDA Tx/Rx polarity not inverted. */
SCI_UART_IRDA_POLARITY_INVERTED = 1, /* /< IrDA Tx/Rx polarity inverted. */
} sci_uart_irda_polarity_t;
/** Configuration settings for IrDA interface. */
typedef struct st_sci_uart_irda_setting
{
union
{
uint8_t ircr_bits;
struct
{
uint8_t : 2;
uint8_t irrxinv : 1; /* /< IRRXD Polarity Switching */
uint8_t irtxinv : 1; /* /< IRTXD Polarity Switching */
uint8_t : 3;
uint8_t ire : 1; /* /< Enable IrDA pulse encoding and decoding. */
} ircr_bits_b;
};
} sci_uart_irda_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_clk_src_t clock; /* /< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK */
sci_uart_start_bit_t rx_edge_start; /* /< Start reception on falling edge */
sci_uart_noise_cancellation_t noise_cancel; /* /< Noise cancellation setting */
baud_setting_t * p_baud_setting; /* /< Register settings for a desired baud rate. */
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; /* /< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. */
bsp_io_port_pin_t flow_control_pin; /* /< UART Driver Enable pin */
sci_uart_flow_control_t flow_control; /* /< CTS/RTS function of the SSn pin */
sci_uart_rs485_setting_t rs485_setting; /* /< RS-485 settings. */
sci_uart_irda_setting_t irda_setting; /* /< IrDA settings */
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const uart_api_t g_uart_on_sci;
/** @endcond */
fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg);
fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes);
fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes);
fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting);
fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info);
fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl);
fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort);
fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate,
bool bitrate_modulation,
uint32_t baud_rate_error_x_1000,
baud_setting_t * const p_baud_setting);
fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_UART)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* Ensure Renesas MCU variation definitions are included to ensure MCU
* specific register variations are handled correctly. */
#ifndef BSP_FEATURE_H
#error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
#endif
/** @addtogroup Renesas
* @{
*/
/** @addtogroup RA
* @{
*/
#ifndef RA_H
#define RA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cmsis_compiler.h"
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
/* IRQn_Type is provided in bsp_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */
/** @} */ /* End of group Configuration_of_CMSIS */
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
#if BSP_MCU_GROUP_RA0E1
#include "R7FA0E107.h"
#elif BSP_MCU_GROUP_RA0E2
#include "R7FA0E209.h"
#elif BSP_MCU_GROUP_RA2A1
#include "R7FA2A1AB.h"
#elif BSP_MCU_GROUP_RA2A2
#include "R7FA2A2AD.h"
#elif BSP_MCU_GROUP_RA2E1
#include "R7FA2E1A9.h"
#elif BSP_MCU_GROUP_RA2E2
#include "R7FA2E2A7.h"
#elif BSP_MCU_GROUP_RA2E3
#include "R7FA2E307.h"
#elif BSP_MCU_GROUP_RA2L1
#include "R7FA2L1AB.h"
#elif BSP_MCU_GROUP_RA2L2
#include "R7FA2L209.h"
#elif BSP_MCU_GROUP_RA4E1
#include "R7FA4E10D.h"
#elif BSP_MCU_GROUP_RA4E2
#include "R7FA4E2B9.h"
#elif BSP_MCU_GROUP_RA4M1
#include "R7FA4M1AB.h"
#elif BSP_MCU_GROUP_RA4M2
#include "R7FA4M2AD.h"
#elif BSP_MCU_GROUP_RA4M3
#include "R7FA4M3AF.h"
#elif BSP_MCU_GROUP_RA4T1
#include "R7FA4T1BB.h"
#elif BSP_MCU_GROUP_RA4W1
#include "R7FA4W1AD.h"
#elif BSP_MCU_GROUP_RA4L1
#include "R7FA4L1BD.h"
#elif BSP_MCU_GROUP_RA6E1
#include "R7FA6E10F.h"
#elif BSP_MCU_GROUP_RA6E2
#include "R7FA6E2BB.h"
#elif BSP_MCU_GROUP_RA6M1
#include "R7FA6M1AD.h"
#elif BSP_MCU_GROUP_RA6M2
#include "R7FA6M2AF.h"
#elif BSP_MCU_GROUP_RA6M3
#include "R7FA6M3AH.h"
#elif BSP_MCU_GROUP_RA6M4
#include "R7FA6M4AF.h"
#elif BSP_MCU_GROUP_RA6M5
#include "R7FA6M5BH.h"
#elif BSP_MCU_GROUP_RA6T1
#include "R7FA6T1AD.h"
#elif BSP_MCU_GROUP_RA6T2
#include "R7FA6T2BD.h"
#elif BSP_MCU_GROUP_RA6T3
#include "R7FA6T3BB.h"
#elif BSP_MCU_GROUP_RA8M1
#include "R7FA8M1AH.h"
#elif BSP_MCU_GROUP_RA8D1
#include "R7FA8D1BH.h"
#elif BSP_MCU_GROUP_RA8T1
#include "R7FA8T1AH.h"
#elif BSP_MCU_GROUP_RA8E1
#include "R7FA8E1AF.h"
#elif BSP_MCU_GROUP_RA8E2
#include "R7FA8E2AF.h"
#else
#if __has_include("renesas_internal.h")
#include "renesas_internal.h"
#else
#warning "Unsupported MCU"
#endif
#endif
/*
* ARM has advised to no longer use the __ARM_ARCH_8_1M_MAIN__ type macro and to instead use the __ARM_ARCH and __ARM_ARCH_ISA_THUMB
* macros for differentiating architectures. However, with all of our toolchains, neither paradigm is being correctly produced for Cortex-M85
* and thus we still need a workaround. Below is a summary of the current macros produced by each toolchain for CM85:
*
* | Toolchain | __ARM_ARCH | _ARM_ARCH_xx__ |
* |-----------|------------|------------------------|
* | GCC | 8 | __ARM_ARCH_8M_MAIN__ |
* | LLVM | 8 | __ARM_ARCH_8_1M_MAIN__ |
* | AC6 | 8 | __ARM_ARCH_8_1M_MAIN__ |
* | IAR | 801 | __ARM_ARCH_8M_MAIN__ |
*
* The expected output for CM85 should be __ARM_ARCH == 801, __ARM_ARCH_ISA_THUMB == 2, and __ARM_ARCH_8_1M_MAIN__
*
* IAR is currently the only toolchain producing the correct __ARM_ARCH value.
*
*- See https://github.com/ARM-software/CMSIS_6/issues/159
*/
#if BSP_CFG_MCU_PART_SERIES == 8 && !defined(__ICCARM__) && BSP_CFG_CPU_CORE != 1
#undef __ARM_ARCH
#define __ARM_ARCH 801
#endif
#if (__ARM_ARCH == 7) && (__ARM_ARCH_ISA_THUMB == 2)
#define RENESAS_CORTEX_M4
#elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 1)
#define RENESAS_CORTEX_M23
#elif (__ARM_ARCH == 8) && (__ARM_ARCH_ISA_THUMB == 2)
#define RENESAS_CORTEX_M33
#elif (__ARM_ARCH == 801) && (__ARM_ARCH_ISA_THUMB == 2)
#define RENESAS_CORTEX_M85
#else
#warning Unsupported Architecture
#endif
#ifdef __cplusplus
}
#endif
#endif /* RA_H */
/** @} */ /* End of group RA */
/** @} */ /* End of group Renesas */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SYSTEM_RENESAS_ARM_H
#define SYSTEM_RENESAS_ARM_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if BSP_TZ_SECURE_BUILD
#define BSP_TZ_STACK_SEAL_SIZE (8U)
#else
#define BSP_TZ_STACK_SEAL_SIZE (0U)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/* Defines function pointers to be used with vector table. */
typedef void (* exc_ptr_t)(void);
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
void Reset_Handler(void);
void Default_Handler(void);
int32_t main(void);
/*******************************************************************************************************************//**
* MCU starts executing here out of reset. Main stack pointer is set up already.
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP void Reset_Handler (void)
{
/* Initialize system using BSP. */
SystemInit();
/* Call user application. */
#ifdef __ARMCC_VERSION
main();
#elif defined(__GNUC__)
extern int entry(void);
entry();
#endif
while (1)
{
/* Infinite Loop. */
}
}
/*******************************************************************************************************************//**
* Default exception handler.
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP void Default_Handler (void)
{
/** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption
* or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status
* registers for more information.
*/
BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
}
/* Main stack */
static uint8_t g_main_stack[BSP_CFG_STACK_MAIN_BYTES + BSP_TZ_STACK_SEAL_SIZE] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT)
BSP_PLACE_IN_SECTION(BSP_SECTION_STACK);
/* Heap */
#if (BSP_CFG_HEAP_BYTES > 0)
BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \
BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP);
#endif
/* All system exceptions in the vector table are weak references to Default_Handler. If the user wishes to handle
* these exceptions in their code they should define their own function with the same name.
*/
#if defined(__ICCARM__)
#define WEAK_REF_ATTRIBUTE
#pragma weak HardFault_Handler = Default_Handler
#pragma weak MemManage_Handler = Default_Handler
#pragma weak BusFault_Handler = Default_Handler
#pragma weak UsageFault_Handler = Default_Handler
#pragma weak SecureFault_Handler = Default_Handler
#pragma weak SVC_Handler = Default_Handler
#pragma weak DebugMon_Handler = Default_Handler
#pragma weak PendSV_Handler = Default_Handler
#pragma weak SysTick_Handler = Default_Handler
#elif defined(__GNUC__)
#define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler")))
#endif
void NMI_Handler(void); /* NMI has many sources and is handled by BSP */
void HardFault_Handler(void) WEAK_REF_ATTRIBUTE;
void MemManage_Handler(void) WEAK_REF_ATTRIBUTE;
void BusFault_Handler(void) WEAK_REF_ATTRIBUTE;
void UsageFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SecureFault_Handler(void) WEAK_REF_ATTRIBUTE;
void SVC_Handler(void) WEAK_REF_ATTRIBUTE;
void DebugMon_Handler(void) WEAK_REF_ATTRIBUTE;
void PendSV_Handler(void) WEAK_REF_ATTRIBUTE;
void SysTick_Handler(void) WEAK_REF_ATTRIBUTE;
/* Vector table. */
BSP_DONT_REMOVE const exc_ptr_t __Vectors[BSP_CORTEX_VECTOR_TABLE_ENTRIES] BSP_PLACE_IN_SECTION(
BSP_SECTION_FIXED_VECTORS) =
{
(exc_ptr_t) (&g_main_stack[0] + BSP_CFG_STACK_MAIN_BYTES), /* Initial Stack Pointer */
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
SecureFault_Handler, /* Secure Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
};
/** @} (end addtogroup BSP_MCU) */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include <string.h>
#if defined(__GNUC__) && defined(__llvm__) && !defined(__ARMCC_VERSION) && !defined(__CLANG_TIDY__)
#include <picotls.h>
#endif
#if defined(__ARMCC_VERSION)
#if defined(__ARMCC_USING_STANDARDLIB)
#include <rt_misc.h>
#endif
#endif
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* Mask to select CP bits( 0xF00000 ) */
#define CP_MASK (0xFU << 20)
/* Startup value for CCR to enable instruction cache, branch prediction and LOB extension */
#define CCR_CACHE_ENABLE (0x000E0201)
/* Value to write to OAD register of MPU stack monitor to enable NMI when a stack overflow is detected. */
#define BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION (0xA500U)
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
#define BSP_PRV_STACK_LIMIT ((uint32_t) __Vectors[0] - BSP_CFG_STACK_MAIN_BYTES)
#define BSP_PRV_STACK_TOP ((uint32_t) __Vectors[0])
#define BSP_TZ_STACK_SEAL_VALUE (0xFEF5EDA5)
#define ARMV8_MPU_REGION_MIN_SIZE (32U)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$BSS$$ZI$$Base;
extern uint32_t Image$$BSS$$ZI$$Length;
extern uint32_t Load$$DATA$$Base;
extern uint32_t Image$$DATA$$Base;
extern uint32_t Image$$DATA$$Length;
#if defined(__ARMCC_USING_STANDARDLIB)
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base;
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length;
#endif
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t Load$$ITCM_DATA$$Base;
extern uint32_t Load$$ITCM_PAD$$Limit;
extern uint32_t Image$$ITCM_DATA$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t Load$$DTCM_DATA$$Base;
extern uint32_t Load$$DTCM_PAD$$Limit;
extern uint32_t Image$$DTCM_DATA$$Base;
extern uint32_t Image$$DTCM_BSS$$Base;
extern uint32_t Image$$DTCM_BSS_PAD$$ZI$$Limit;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t Image$$NOCACHE$$ZI$$Base;
extern uint32_t Image$$NOCACHE_PAD$$ZI$$Limit;
extern uint32_t Image$$NOCACHE_SDRAM$$ZI$$Base;
extern uint32_t Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit;
#endif
#elif defined(__GNUC__)
/* Generated by linker. */
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackLimit;
extern uint32_t __StackTop;
/* Nested in __GNUC__ because LLVM generates both __GNUC__ and __llvm__*/
#if defined(__llvm__) && !defined(__CLANG_TIDY__)
extern uint32_t __tls_base;
#endif
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t __itcm_data_init_start;
extern uint32_t __itcm_data_init_end;
extern uint32_t __itcm_data_start;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t __dtcm_data_init_start;
extern uint32_t __dtcm_data_init_end;
extern uint32_t __dtcm_data_start;
extern uint32_t __dtcm_bss_start;
extern uint32_t __dtcm_bss_end;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t __nocache_start;
extern uint32_t __nocache_end;
extern uint32_t __nocache_sdram_start;
extern uint32_t __nocache_sdram_end;
#endif
#elif defined(__ICCARM__)
#pragma section=".bss"
#pragma section=".data"
#pragma section=".data_init"
#pragma section=".stack"
#if BSP_FEATURE_BSP_HAS_ITCM
extern uint32_t ITCM_DATA_INIT$$Base;
extern uint32_t ITCM_DATA_INIT$$Limit;
extern uint32_t ITCM_DATA$$Base;
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
extern uint32_t DTCM_DATA_INIT$$Base;
extern uint32_t DTCM_DATA_INIT$$Limit;
extern uint32_t DTCM_DATA$$Base;
extern uint32_t DTCM_BSS$$Base;
extern uint32_t DTCM_BSS$$Limit;
#endif
#if BSP_CFG_DCACHE_ENABLED
extern uint32_t NOCACHE$$Base;
extern uint32_t NOCACHE$$Limit;
extern uint32_t NOCACHE_SDRAM$$Base;
extern uint32_t NOCACHE_SDRAM$$Limit;
#endif
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
extern void (* Image$$INIT_ARRAY$$Base[])(void);
extern void (* Image$$INIT_ARRAY$$Limit[])(void);
#elif defined(__GNUC__)
extern void (* __init_array_start[])(void);
extern void (* __init_array_end[])(void);
#elif defined(__ICCARM__)
extern void __call_ctors(void const *, void const *);
#pragma section = "SHT$$PREINIT_ARRAY" const
#pragma section = "SHT$$INIT_ARRAY" const
#endif
extern void * __Vectors[];
extern void R_BSP_SecurityInit(void);
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit(void);
#endif
#if defined(__ICCARM__)
void R_BSP_WarmStart(bsp_warm_start_event_t event);
#pragma weak R_BSP_WarmStart
#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak));
#endif
#if BSP_CFG_EARLY_INIT
static void bsp_init_uninitialized_vars(void);
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM
static void memcpy_64(uint64_t * destination, const uint64_t * source, size_t count);
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
static void memset_64(uint64_t * destination, const uint64_t value, size_t count);
#endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM
static void bsp_init_itcm(void);
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
static void bsp_init_dtcm(void);
#endif
#endif
#if BSP_CFG_DCACHE_ENABLED
static void bsp_init_mpu(void);
#endif
/*******************************************************************************************************************//**
* Initialize the MCU and the runtime environment.
**********************************************************************************************************************/
void SystemInit (void)
{
#if defined(RENESAS_CORTEX_M85)
/* Enable the instruction cache, branch prediction, and the branch cache (required for Low Overhead Branch (LOB) extension).
* See sections 6.5, 6.6, and 6.7 in the Arm Cortex-M85 Processor Technical Reference Manual (Document ID: 101924_0002_05_en, Issue: 05)
* See section D1.2.9 in the Armv8-M Architecture Reference Manual (Document number: DDI0553B.w, Document version: ID07072023) */
SCB->CCR = (uint32_t) CCR_CACHE_ENABLE;
__DSB();
__ISB();
#if !BSP_TZ_NONSECURE_BUILD
/* Apply Arm Cortex-M85 errata workarounds for D-Cache.
* See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641 Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0, Document ID: SDEN-2236668). */
MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
__DSB();
__ISB();
ICB->ACTLR |= (1U << 16U);
__DSB();
__ISB();
#endif
#endif
#if __FPU_USED
/* Enable the FPU only when it is used.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C) */
/* Set bits 20-23 (CP10 and CP11) to enable FPU. */
SCB->CPACR = (uint32_t) CP_MASK;
#endif
#if BSP_TZ_SECURE_BUILD
/* Seal the main stack for secure projects. Reference:
* https://developer.arm.com/documentation/100720/0300
* https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing */
uint32_t * p_main_stack_top = (uint32_t *) __Vectors[0];
*p_main_stack_top = BSP_TZ_STACK_SEAL_VALUE;
#endif
#if !BSP_TZ_NONSECURE_BUILD
/* VTOR is in undefined state out of RESET:
* https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/system-control-block-registers-summary?lang=en.
* Set the Secure/Non-Secure VTOR to the vector table address based on the build. This is skipped for non-secure
* projects because SCB_NS->VTOR is set by the secure project before the non-secure project runs. */
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if !BSP_TZ_CFG_SKIP_INIT && !BSP_CFG_SKIP_INIT
#if BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP
/* Unlock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
/* The VBTCR1.BPWSWSTP must be set after reset on MCUs that have VBTCR1.BPWSWSTP. Reference section 11.2.1
* "VBATT Control Register 1 (VBTCR1)" and Figure 11.2 "Setting flow of the VBTCR1.BPWSWSTP bit" in the RA4M1 manual
* R01UM0007EU0110. This must be done before bsp_clock_init because LOCOCR, LOCOUTCR, SOSCCR, and SOMCR cannot
* be accessed until VBTSR.VBTRVLD is set. */
R_SYSTEM->VBTCR1 = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->VBTSR_b.VBTRVLD, 1U);
/* Lock VBTCR1 register. */
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
#endif
#endif
#if BSP_FEATURE_TFU_SUPPORTED
R_BSP_MODULE_START(FSP_IP_TFU, 0U);
#endif
#if BSP_FEATURE_MACL_SUPPORTED
#if __has_include("arm_math_types.h")
R_BSP_MODULE_START(FSP_IP_MACL, 0U);
#endif
#endif
#if BSP_CFG_EARLY_INIT
/* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */
bsp_init_uninitialized_vars();
#endif
/* Call pre clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_RESET);
#if BSP_TZ_CFG_SKIP_INIT || BSP_CFG_SKIP_INIT
/* Initialize clock variables to be used with R_BSP_SoftwareDelay. */
bsp_clock_freq_var_init();
#if BSP_CFG_SKIP_INIT && (defined(R_CACHE) || BSP_FEATURE_BSP_FLASH_CACHE)
/* Flush cache before enabling */
R_CACHE->CCAFCT_b.FC = 1;
/* Enable cache */
R_BSP_FlashCacheEnable();
#endif
#else
/* Configure system clocks. */
bsp_clock_init();
#if BSP_FEATURE_BSP_RESET_TRNG
/* To prevent an undesired current draw, this MCU requires a reset
* of the TRNG circuit after the clocks are initialized */
bsp_reset_trng_circuit();
#endif
#endif
/* Call post clock initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK);
#if BSP_FEATURE_BSP_HAS_SP_MON
/* Disable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 0;
/* Setup NMI interrupt */
R_MPU_SPMON->SP[0].OAD = BSP_STACK_POINTER_MONITOR_NMI_ON_DETECTION;
/* Setup start address */
R_MPU_SPMON->SP[0].SA = BSP_PRV_STACK_LIMIT;
/* Setup end address */
R_MPU_SPMON->SP[0].EA = BSP_PRV_STACK_TOP;
/* Set SPEEN bit to enable NMI on stack monitor exception. NMIER bits cannot be cleared after reset, so no need
* to read-modify-write. */
R_ICU->NMIER = R_ICU_NMIER_SPEEN_Msk;
/* Enable MSP monitoring */
R_MPU_SPMON->SP[0].CTL = 1U;
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE
__set_MSPLIM(BSP_PRV_STACK_LIMIT);
#endif
#if BSP_CFG_C_RUNTIME_INIT
/* Initialize C runtime environment. */
/* Zero out BSS */
#if defined(__ARMCC_VERSION)
memset((uint8_t *) &Image$$BSS$$ZI$$Base, 0U, (uint32_t) &Image$$BSS$$ZI$$Length);
#elif defined(__GNUC__)
memset(&__bss_start__, 0U, ((uint32_t) &__bss_end__ - (uint32_t) &__bss_start__));
#elif defined(__ICCARM__)
memset((uint32_t *) __section_begin(".bss"), 0U, (uint32_t) __section_size(".bss"));
#endif
/* Copy initialized RAM data from ROM to RAM. */
#if defined(__ARMCC_VERSION)
memcpy((uint8_t *) &Image$$DATA$$Base, (uint8_t *) &Load$$DATA$$Base, (uint32_t) &Image$$DATA$$Length);
#elif defined(__GNUC__)
memcpy(&__data_start__, &__etext, ((uint32_t) &__data_end__ - (uint32_t) &__data_start__));
#elif defined(__ICCARM__)
memcpy((uint32_t *) __section_begin(".data"), (uint32_t *) __section_begin(".data_init"),
(uint32_t) __section_size(".data"));
/* Copy functions to be executed from RAM. */
#pragma section=".code_in_ram"
#pragma section=".code_in_ram_init"
memcpy((uint32_t *) __section_begin(".code_in_ram"),
(uint32_t *) __section_begin(".code_in_ram_init"),
(uint32_t) __section_size(".code_in_ram"));
/* Copy main thread TLS to RAM. */
#pragma section="__DLIB_PERTHREAD_init"
#pragma section="__DLIB_PERTHREAD"
memcpy((uint32_t *) __section_begin("__DLIB_PERTHREAD"), (uint32_t *) __section_begin("__DLIB_PERTHREAD_init"),
(uint32_t) __section_size("__DLIB_PERTHREAD_init"));
#endif
/* Initialize TCM memory. */
#if BSP_FEATURE_BSP_HAS_ITCM
bsp_init_itcm();
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
bsp_init_dtcm();
#endif
#if defined(RENESAS_CORTEX_M85)
/* Invalidate I-Cache after initializing the .code_in_ram section. */
SCB_InvalidateICache();
#endif
#if defined(__GNUC__) && defined(__llvm__) && !defined(__CLANG_TIDY__) && !(defined __ARMCC_VERSION)
/* Initialize TLS memory. */
_init_tls(&__tls_base);
_set_tls(&__tls_base);
#endif
/* Initialize static constructors */
#if defined(__ARMCC_VERSION)
#if defined(__ARMCC_USING_STANDARDLIB)
__rt_lib_init((uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Base,
(uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Base + (uint32_t) &Image$$ARM_LIB_HEAP$$ZI$$Length);
#else
int32_t count = Image$$INIT_ARRAY$$Limit - Image$$INIT_ARRAY$$Base;
for (int32_t i = 0; i < count; i++)
{
void (* p_init_func)(void) =
(void (*)(void))((uint32_t) &Image$$INIT_ARRAY$$Base + (uint32_t) Image$$INIT_ARRAY$$Base[i]);
p_init_func();
}
#endif
#elif defined(__GNUC__)
int32_t count = __init_array_end - __init_array_start;
for (int32_t i = 0; i < count; i++)
{
__init_array_start[i]();
}
#elif defined(__ICCARM__)
void const * pibase = __section_begin("SHT$$PREINIT_ARRAY");
void const * ilimit = __section_end("SHT$$INIT_ARRAY");
__call_ctors(pibase, ilimit);
#endif
#endif /* BSP_CFG_C_RUNTIME_INIT */
/* Initialize SystemCoreClock variable. */
SystemCoreClockUpdate();
#if BSP_FEATURE_RTC_IS_AVAILABLE || BSP_FEATURE_RTC_HAS_TCEN || BSP_FEATURE_SYSC_HAS_VBTICTLR
/* For TZ project, it should be called by the secure application, whether RTC module is to be configured as secure or not. */
#if !BSP_TZ_NONSECURE_BUILD && !BSP_CFG_BOOT_IMAGE && !BSP_CFG_SKIP_INIT
/* Perform RTC reset sequence to avoid unintended operation. */
R_BSP_Init_RTC();
#endif
#endif
#if !BSP_CFG_PFS_PROTECT && defined(R_PMISC) && !BSP_CFG_SKIP_INIT
#if BSP_TZ_SECURE_BUILD || (BSP_FEATURE_TZ_VERSION == 2 && FSP_PRIV_TZ_USE_SECURE_REGS)
R_PMISC->PWPRS = 0; /* /< Clear BOWI bit - writing to PFSWE bit enabled */
R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; /* /< Set PFSWE bit - writing to PFS register enabled */
#else
R_PMISC->PWPR = 0; /* /< Clear BOWI bit - writing to PFSWE bit enabled */
R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; /* /< Set PFSWE bit - writing to PFS register enabled */
#endif
#endif
#if FSP_PRIV_TZ_USE_SECURE_REGS && !BSP_CFG_SKIP_INIT
/* Ensure that the PMSAR registers are set to their default value. */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
{
#if BSP_FEATURE_TZ_VERSION == 2
R_PMISC->PMSAR[i].PMSAR = 0U;
#else
R_PMISC->PMSAR[i].PMSAR = UINT16_MAX;
#endif
}
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
#if BSP_TZ_SECURE_BUILD
/* Initialize security features. */
R_BSP_SecurityInit();
#else
#if FSP_PRIV_TZ_USE_SECURE_REGS
/* Initialize peripherals to secure mode for flat projects */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
R_PSCU->PSARB = 0;
R_PSCU->PSARC = 0;
R_PSCU->PSARD = 0;
R_PSCU->PSARE = 0;
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
#endif
#endif
#if BSP_CFG_DCACHE_ENABLED
bsp_init_mpu();
SCB_EnableDCache();
#endif
#if BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN && !BSP_CFG_SKIP_INIT
if ((((0 == R_SYSTEM->PGCSAR) && FSP_PRIV_TZ_USE_SECURE_REGS) ||
((1 == R_SYSTEM->PGCSAR) && BSP_TZ_NONSECURE_BUILD)) && (0 != R_SYSTEM->PDCTRGD))
{
/* Turn on graphics power domain.
* This requires MOCO to be enabled, but MOCO is always enabled after bsp_clock_init(). */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)),
R_SYSTEM_PDCTRGD_PDPGSF_Msk);
R_SYSTEM->PDCTRGD = 0;
FSP_HARDWARE_REGISTER_WAIT((R_SYSTEM->PDCTRGD & (R_SYSTEM_PDCTRGD_PDCSF_Msk | R_SYSTEM_PDCTRGD_PDPGSF_Msk)), 0);
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
#if BSP_FEATURE_CGC_HAS_EXTRACLK2 && !BSP_CFG_SKIP_INIT
bsp_internal_prv_enable_extra_power_domain();
#endif
/* Call Post C runtime initialization hook. */
R_BSP_WarmStart(BSP_WARM_START_POST_C);
/* Initialize ELC events that will be used to trigger NVIC interrupts. */
bsp_irq_cfg();
/* Call any BSP specific code. No arguments are needed so NULL is sent. */
bsp_init(NULL);
}
/*******************************************************************************************************************//**
* This function is called at various points during the startup process.
* This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user
* implemented version. One of the main uses for this function is to call functional safety code during the startup
* process. To use this function just copy this function into your own code and modify it to meet your needs.
*
* @param[in] event Where the code currently is in the start up process
**********************************************************************************************************************/
void R_BSP_WarmStart (bsp_warm_start_event_t event)
{
if (BSP_WARM_START_RESET == event)
{
/* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */
}
if (BSP_WARM_START_POST_CLOCK == event)
{
/* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */
}
else if (BSP_WARM_START_POST_C == event)
{
/* C runtime environment, system clocks, and pins are all setup. */
}
else
{
/* Do nothing */
}
}
/*******************************************************************************************************************//**
* Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module
* is not in use.
**********************************************************************************************************************/
#if BSP_FEATURE_BSP_RESET_TRNG
static void bsp_reset_trng_circuit (void)
{
volatile uint8_t read_port = 0U;
FSP_PARAMETER_NOT_USED(read_port); /* / Prevent compiler 'unused' warning */
/* Release register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT);
/* Enable TRNG function (disable stop function) */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_START(FSP_IP_TRNG, 0); /* /< TRNG Module Stop needs to be started/stopped for RA2 series. */
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_START(FSP_IP_SCE, 0); /* /< TRNG Module Stop needs to be started/stopped for RA4 series. */
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Wait for at least 3 PCLKB cycles */
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
read_port = R_PFS->PORT[0].PIN[0].PmnPFS_b.PODR;
/* Disable TRNG function */
#if BSP_FEATURE_BSP_HAS_SCE_ON_RA2
R_BSP_MODULE_STOP(FSP_IP_TRNG, 0); /* /< TRNG Module Stop needs to be started/stopped for RA2 series. */
#elif BSP_FEATURE_BSP_HAS_SCE5
R_BSP_MODULE_STOP(FSP_IP_SCE, 0); /* /< TRNG Module Stop needs to be started/stopped for RA4 series. */
#else
#error "BSP_FEATURE_BSP_RESET_TRNG is defined but not handled."
#endif
/* Reapply register protection for low power modes (per RA2A1 User's Manual (R01UH0888EJ0100) Figure 11.13 "Example
* of initial setting flow for an unused circuit") */
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
}
#endif
#if BSP_CFG_EARLY_INIT
/*******************************************************************************************************************//**
* Initialize BSP variables not handled by C runtime startup.
**********************************************************************************************************************/
static void bsp_init_uninitialized_vars (void)
{
g_protect_pfswe_counter = 0;
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++)
{
g_protect_counters[i] = 0;
}
extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
for (uint32_t i = 0; i < 16; i++)
{
g_bsp_group_irq_sources[i] = 0;
}
#if BSP_CFG_EARLY_INIT
/* Set SystemCoreClock to MOCO */
SystemCoreClock = BSP_MOCO_HZ;
#endif
}
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if (BSP_FEATURE_BSP_HAS_ITCM || BSP_FEATURE_BSP_HAS_DTCM)
/*******************************************************************************************************************//**
* 64-bit memory copy for Armv8.1-M using low overhead loop instructions.
*
* @param[in] destination copy destination start address, word aligned
* @param[in] source copy source start address, word aligned
* @param[in] count number of doublewords to copy
**********************************************************************************************************************/
static void memcpy_64 (uint64_t * destination, const uint64_t * source, size_t count)
{
uint64_t temp;
__asm volatile (
"wls lr, %[count], memcpy_64_loop_end_%=\n"
#if (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */
/* IAR does not support alignment control within inline assembly. */
".balign 8\n"
#endif
"memcpy_64_loop_start_%=:\n"
"ldrd %Q[temp], %R[temp], [%[source]], #+8\n"
"strd %Q[temp], %R[temp], [%[destination]], #+8\n"
"le lr, memcpy_64_loop_start_%=\n"
"memcpy_64_loop_end_%=:"
:[destination] "+&r" (destination), [source] "+&r" (source), [temp] "=r" (temp)
:[count] "r" (count)
: "lr", "memory"
);
/* Suppress IAR warning: "Error[Pe550]: variable "temp" was set but never used" */
/* "temp" triggers this warning when it lacks an early-clobber modifier, which was removed to allow register reuse with "count". */
(void) temp;
}
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
/*******************************************************************************************************************//**
* 64-bit memory set for Armv8.1-M using low overhead loop instructions.
*
* @param[in] destination set destination start address, word aligned
* @param[in] value value to set
* @param[in] count number of doublewords to set
**********************************************************************************************************************/
static void memset_64 (uint64_t * destination, const uint64_t value, size_t count)
{
__asm volatile (
"wls lr, %[count], memset_64_loop_end_%=\n"
#if (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */
/* IAR does not support alignment control within inline assembly. */
".balign 8\n"
#endif
"memset_64_loop_start_%=:\n"
"strd %Q[value], %R[value], [%[destination]], #+8\n"
"le lr, memset_64_loop_start_%=\n"
"memset_64_loop_end_%=:"
:[destination] "+&r" (destination)
:[count] "r" (count), [value] "r" (value)
: "lr", "memory"
);
}
#endif
#endif
#if BSP_CFG_C_RUNTIME_INIT
#if BSP_FEATURE_BSP_HAS_ITCM
/*******************************************************************************************************************//**
* Initialize ITCM RAM from ROM image.
**********************************************************************************************************************/
static void bsp_init_itcm (void)
{
uint64_t * itcm_destination;
const uint64_t * itcm_source;
size_t count;
#if defined(__ARMCC_VERSION)
itcm_destination = (uint64_t *) &Image$$ITCM_DATA$$Base;
itcm_source = (uint64_t *) &Load$$ITCM_DATA$$Base;
count = ((uint32_t) &Load$$ITCM_PAD$$Limit - (uint32_t) &Load$$ITCM_DATA$$Base) / sizeof(uint64_t);
#elif defined(__GNUC__)
itcm_destination = (uint64_t *) &__itcm_data_start;
itcm_source = (uint64_t *) &__itcm_data_init_start;
count = ((uint32_t) &__itcm_data_init_end - (uint32_t) &__itcm_data_init_start) / sizeof(uint64_t);
#elif defined(__ICCARM__)
itcm_destination = (uint64_t *) &ITCM_DATA$$Base;
itcm_source = (uint64_t *) &ITCM_DATA_INIT$$Base;
count = ((uint32_t) &ITCM_DATA_INIT$$Limit - (uint32_t) &ITCM_DATA_INIT$$Base) / sizeof(uint64_t);
#endif
memcpy_64(itcm_destination, itcm_source, count);
}
#endif
#if BSP_FEATURE_BSP_HAS_DTCM
/*******************************************************************************************************************//**
* Initialize DTCM RAM from ROM image and zero initialize DTCM RAM BSS section.
**********************************************************************************************************************/
static void bsp_init_dtcm (void)
{
uint64_t * dtcm_destination;
const uint64_t * dtcm_source;
size_t count;
uint64_t * dtcm_zero_destination;
size_t count_zero;
#if defined(__ARMCC_VERSION)
dtcm_destination = (uint64_t *) &Image$$DTCM_DATA$$Base;
dtcm_source = (uint64_t *) &Load$$DTCM_DATA$$Base;
count = ((uint32_t) &Load$$DTCM_PAD$$Limit - (uint32_t) &Load$$DTCM_DATA$$Base) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &Image$$DTCM_BSS$$Base;
count_zero = ((uint32_t) &Image$$DTCM_BSS_PAD$$ZI$$Limit - (uint32_t) &Image$$DTCM_BSS$$Base) /
sizeof(uint64_t);
#elif defined(__GNUC__)
dtcm_destination = (uint64_t *) &__dtcm_data_start;
dtcm_source = (uint64_t *) &__dtcm_data_init_start;
count = ((uint32_t) &__dtcm_data_init_end - (uint32_t) &__dtcm_data_init_start) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &__dtcm_bss_start;
count_zero = ((uint32_t) &__dtcm_bss_end - (uint32_t) &__dtcm_bss_start) / sizeof(uint64_t);
#elif defined(__ICCARM__)
dtcm_destination = (uint64_t *) &DTCM_DATA$$Base;
dtcm_source = (uint64_t *) &DTCM_DATA_INIT$$Base;
count = ((uint32_t) &DTCM_DATA_INIT$$Limit - (uint32_t) &DTCM_DATA_INIT$$Base) / sizeof(uint64_t);
dtcm_zero_destination = (uint64_t *) &DTCM_BSS$$Base;
count_zero = ((uint32_t) &DTCM_BSS$$Limit - (uint32_t) &DTCM_BSS$$Base) / sizeof(uint64_t);
#endif
memcpy_64(dtcm_destination, dtcm_source, count);
memset_64(dtcm_zero_destination, 0, count_zero);
}
#endif
#endif
#if BSP_CFG_DCACHE_ENABLED
/*******************************************************************************************************************//**
* Initialize MPU for Armv8-M devices.
**********************************************************************************************************************/
static void bsp_init_mpu (void)
{
uint32_t nocache_start;
uint32_t nocache_end;
#if BSP_FEATURE_SDRAM_START_ADDRESS
uint32_t nocache_sdram_start;
uint32_t nocache_sdram_end;
#endif
#if defined(__ARMCC_VERSION)
nocache_start = (uint32_t) &Image$$NOCACHE$$ZI$$Base;
nocache_end = (uint32_t) &Image$$NOCACHE_PAD$$ZI$$Limit;
#if BSP_FEATURE_SDRAM_START_ADDRESS
nocache_sdram_start = (uint32_t) &Image$$NOCACHE_SDRAM$$ZI$$Base;
nocache_sdram_end = (uint32_t) &Image$$NOCACHE_SDRAM_PAD$$ZI$$Limit;
#endif
#elif defined(__GNUC__)
nocache_start = (uint32_t) &__nocache_start;
nocache_end = (uint32_t) &__nocache_end;
#if BSP_FEATURE_SDRAM_START_ADDRESS
nocache_sdram_start = (uint32_t) &__nocache_sdram_start;
nocache_sdram_end = (uint32_t) &__nocache_sdram_end;
#endif
#elif defined(__ICCARM__)
nocache_start = (uint32_t) &NOCACHE$$Base;
nocache_end = (uint32_t) &NOCACHE$$Limit;
#if BSP_FEATURE_SDRAM_START_ADDRESS
nocache_sdram_start = (uint32_t) &NOCACHE_SDRAM$$Base;
nocache_sdram_end = (uint32_t) &NOCACHE_SDRAM$$Limit;
#endif
#endif
/* Maximum of eight attributes. */
const uint8_t bsp_mpu_mair_attributes[] =
{
/* Normal, Non-cacheable */
ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)
};
/* Maximum of eight regions. */
/* A region start address and end address must each be aligned to 32 bytes. A region must be a minimum of 32 bytes to be valid. */
/* A region end address is inclusive. */
const ARM_MPU_Region_t bsp_mpu_regions[] =
{
/* No-Cache Section */
{
.RBAR = ARM_MPU_RBAR(nocache_start, ARM_MPU_SH_NON, 0U, 0U, 1U),
.RLAR = ARM_MPU_RLAR((nocache_end - ARMV8_MPU_REGION_MIN_SIZE), 0U)
},
#if BSP_FEATURE_SDRAM_START_ADDRESS
/* SDRAM No-Cache Section */
{
.RBAR = ARM_MPU_RBAR(nocache_sdram_start, ARM_MPU_SH_NON, 0U, 0U, 1U),
.RLAR = ARM_MPU_RLAR((nocache_sdram_end - ARMV8_MPU_REGION_MIN_SIZE), 0U)
}
#endif
};
/* Initialize MPU_MAIR0 and MPU_MAIR1 from attributes table. */
uint8_t num_attr = (sizeof(bsp_mpu_mair_attributes) / sizeof(bsp_mpu_mair_attributes[0]));
for (uint8_t i = 0; i < num_attr; i++)
{
ARM_MPU_SetMemAttr(i, bsp_mpu_mair_attributes[i]);
}
/* Initialize MPU from configuration table. */
uint8_t num_regions = (sizeof(bsp_mpu_regions) / sizeof(bsp_mpu_regions[0]));
for (uint8_t i = 0; i < num_regions; i++)
{
uint32_t rbar = bsp_mpu_regions[i].RBAR;
uint32_t rlar = bsp_mpu_regions[i].RLAR;
/* Only configure regions of non-zero size. */
if ((((rlar & MPU_RLAR_LIMIT_Msk) >> MPU_RLAR_LIMIT_Pos) + ARMV8_MPU_REGION_MIN_SIZE) >
((rbar & MPU_RBAR_BASE_Msk) >> MPU_RBAR_BASE_Pos))
{
ARM_MPU_SetRegion(i, rbar, rlar);
}
}
/*
* SHCSR.MEMFAULTENA is set inside ARM_MPU_Enable().
* Leave SHPR1.PRI_4 at reset value of zero.
* Leave MPU_CTRL.HFNMIENA at reset value of zero.
* Provide MPU_CTRL_PRIVDEFENA_Msk to ARM_MPU_Enable() to set MPU_CTRL.PRIVDEFENA.
*/
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
}
#endif
/** @} (end addtogroup BSP_MCU) */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOARD_SDRAM_H
#define BOARD_SDRAM_H
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* DEPRECATED: This is a temporary alias to the new SDRAM support in bsp_sdram.c. It will be removed in FSP v6.0.0.
* It is only present if the new support has not been enabled. */
#if 1 != BSP_CFG_SDRAM_ENABLED
#define bsp_sdram_init() R_BSP_SdramInit(true)
#endif
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
*
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ICCARM__)
#define WEAK_ERROR_ATTRIBUTE
#define WEAK_INIT_ATTRIBUTE
#pragma weak fsp_error_log = fsp_error_log_internal
#pragma weak bsp_init = bsp_init_internal
#elif defined(__GNUC__)
#define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal")))
#define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal")))
#endif
#define FSP_SECTION_VERSION ".version"
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/** Prototype of initialization function called before main. This prototype sets the weak association of this
* function to an internal example implementation. If this function is defined in the application code, the
* application code version is used. */
void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE;
void bsp_init_internal(void * p_args); /* / Default initialization function */
#if (1 == BSP_CFG_ASSERT)
/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ASSERT is set to 1. This
* prototype sets the weak association of this function to an internal example implementation. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE;
void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /* / Default error logger function */
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
static bool bsp_valid_register_check(uint32_t register_address,
uint32_t const * const p_register_table,
uint32_t register_table_length);
#endif
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/* FSP pack version structure. */
static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) =
{
.version_id_b =
{
.minor = FSP_VERSION_MINOR,
.major = FSP_VERSION_MAJOR,
.build = FSP_VERSION_BUILD,
.patch = FSP_VERSION_PATCH
}
};
/* Public FSP version name. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_STRING;
/* Unique FSP version ID. */
static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) =
FSP_VERSION_BUILD_STRING;
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Get the FSP version based on compile time macros.
*
* @param[out] p_version Memory address to return version information to.
*
* @retval FSP_SUCCESS Version information stored.
* @retval FSP_ERR_ASSERTION The parameter p_version is NULL.
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version)
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/** Verify parameters are valid */
FSP_ASSERT(NULL != p_version);
#endif
*p_version = g_fsp_version;
return FSP_SUCCESS;
}
#if (1 == BSP_CFG_ASSERT)
/*******************************************************************************************************************//**
* Default error logger function, used only if fsp_error_log is not defined in the user application.
*
* @param[in] err The error code encountered.
* @param[in] file The file name in which the error code was encountered.
* @param[in] line The line number at which the error code was encountered.
**********************************************************************************************************************/
void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line)
{
/** Do nothing. Do not generate any 'unused' warnings. */
FSP_PARAMETER_NOT_USED(err);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
}
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
/*******************************************************************************************************************//**
* Read a secure 8-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
{
uint8_t volatile * p_reg_s = (uint8_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_SYSTEM->SCKDIVCR2,
(uint32_t) &R_SYSTEM->SCKSCR,
(uint32_t) &R_SYSTEM->SPICKDIVCR,
(uint32_t) &R_SYSTEM->SPICKCR,
(uint32_t) &R_SYSTEM->SCICKDIVCR,
(uint32_t) &R_SYSTEM->SCICKCR,
(uint32_t) &R_SYSTEM->CANFDCKCR,
(uint32_t) &R_SYSTEM->PLLCR,
(uint32_t) &R_SYSTEM->PLL2CR,
(uint32_t) &R_SYSTEM->MOCOCR,
(uint32_t) &R_SYSTEM->OPCCR,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint8_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
/*******************************************************************************************************************//**
* Read a secure 16-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
{
uint16_t volatile * p_reg_s = (uint16_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_DTC->DTCSTS,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint16_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
/*******************************************************************************************************************//**
* Read a secure 32-bit STYPE3 register in the non-secure state.
*
* @param[in] p_reg The address of the secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
{
uint32_t volatile * p_reg_s = (uint32_t volatile *) ((uint32_t) p_reg & ~BSP_FEATURE_TZ_NS_OFFSET);
/* Table of secure registers that may be read from the non-secure application. */
static const uint32_t valid_addresses[] =
{
(uint32_t) &R_SYSTEM->SCKDIVCR,
};
if (bsp_valid_register_check((uint32_t) p_reg_s, valid_addresses,
sizeof(valid_addresses) / sizeof(valid_addresses[0])))
{
return *p_reg_s;
}
/* Generate a trustzone access violation by accessing the non-secure aliased address. */
return *((uint32_t volatile *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET));
}
#endif
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* Default initialization function, used only if bsp_init is not defined in the user application.
**********************************************************************************************************************/
void bsp_init_internal (void * p_args)
{
/* Do nothing. */
FSP_PARAMETER_NOT_USED(p_args);
}
#if defined(__ARMCC_VERSION)
/*******************************************************************************************************************//**
* Default implementation of assert for AC6.
**********************************************************************************************************************/
__attribute__((weak, noreturn))
void __aeabi_assert (const char * expr, const char * file, int line)
{
FSP_PARAMETER_NOT_USED(expr);
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#elif defined(__GNUC__)
/* The default assert implementation for GCC brings in printing/formatting code. FSP overrides the default assert
* behavior to reduce code size. */
#if !BSP_CFG_USE_STANDARD_ASSERT
/*******************************************************************************************************************//**
* Default implementation of assert for GCC.
**********************************************************************************************************************/
BSP_WEAK_REFERENCE void __assert_func (const char * file, int line, const char * func, const char * expr)
{
FSP_PARAMETER_NOT_USED(file);
FSP_PARAMETER_NOT_USED(line);
FSP_PARAMETER_NOT_USED(func);
FSP_PARAMETER_NOT_USED(expr);
__BKPT(0);
while (1)
{
/* Do nothing. */
}
}
#endif
#endif
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_SECURE_BUILD == 1
/*******************************************************************************************************************//**
* Check if a register address should be accessible by the non-secure application.
**********************************************************************************************************************/
static bool bsp_valid_register_check (uint32_t register_address,
uint32_t const * const p_register_table,
uint32_t register_table_length)
{
bool valid = false;
/* Check if the given address is valid. */
for (uint32_t i = 0; i < register_table_length; i++)
{
if (p_register_table[i] == register_address)
{
valid = true;
break;
}
}
return valid;
}
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSP_COMMON_H
#define BSP_COMMON_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* C99 includes. */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <assert.h>
#include <string.h>
/* Different compiler support. */
#include "../../inc/api/fsp_common_api.h"
#include "bsp_compiler_support.h"
/* BSP TFU Includes. */
#include "../../src/bsp/mcu/all/bsp_tfu.h"
#include "../../src/bsp/mcu/all/bsp_sdram.h"
/* BSP MMF Includes. */
#include "../../src/bsp/mcu/all/bsp_mmf.h"
#include "bsp_cfg.h"
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** Used to signify that an ELC event is not able to be used as an interrupt. */
#define BSP_IRQ_DISABLED (0xFFU)
/* Version of this module's code and API. */
#if 1 == BSP_CFG_RTOS /* ThreadX */
#include "tx_user.h"
#if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY)
#include "tx_port.h"
#define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet());
#define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet());
#else
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
#endif
#else
#define FSP_CONTEXT_SAVE
#define FSP_CONTEXT_RESTORE
#endif
/** Macro that can be defined in order to enable logging in FSP modules. */
#ifndef FSP_LOG_PRINT
#define FSP_LOG_PRINT(X)
#endif
/** Macro to log and return error without an assertion. */
#ifndef FSP_RETURN
#define FSP_RETURN(err) FSP_ERROR_LOG((err)); \
return err;
#endif
/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in
* user code and do required debugging (breakpoints, stack dump, etc) in this function.*/
#if (1 == BSP_CFG_ASSERT)
#ifndef FSP_ERROR_LOG
#define FSP_ERROR_LOG(err) \
fsp_error_log((err), __FILE__, __LINE__);
#endif
#else
#define FSP_ERROR_LOG(err)
#endif
/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP
* functions. */
#if (3 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a)
#elif (2 == BSP_CFG_ASSERT)
#define FSP_ASSERT(a) {assert(a);}
#else
#define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION)
#endif /* ifndef FSP_ASSERT */
/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used
* to identify runtime errors in FSP functions. */
#define FSP_ERROR_RETURN(a, err) \
{ \
if ((a)) \
{ \
(void) 0; /* Do nothing */ \
} \
else \
{ \
FSP_ERROR_LOG(err); \
return err; \
} \
}
/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates.
* This macro can be redefined to add a timeout if necessary. */
#ifndef FSP_HARDWARE_REGISTER_WAIT
#define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */}
#endif
#ifndef FSP_REGISTER_READ
/* Read a register and discard the result. */
#define FSP_REGISTER_READ(A) __ASM volatile ("" : : "r" (A));
#endif
/****************************************************************
*
* This check is performed to select suitable ASM API with respect to core
*
* The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so
* the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */
#if (defined(__IICARM__) && defined(RENESAS_CORTEX_M23)) || defined(RENESAS_CORTEX_M4)
#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
#else
#ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION
#endif
#define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U)
#endif
/* This macro defines a variable for saving previous mask value */
#ifndef FSP_CRITICAL_SECTION_DEFINE
#define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U
#endif
/* These macros abstract methods to save and restore the interrupt state for different architectures. */
#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION)
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK
#define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U)
#else
#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI
#define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI
#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \
(8U - __NVIC_PRIO_BITS)))
#endif
/** This macro temporarily saves the current interrupt state and disables interrupts. */
#ifndef FSP_CRITICAL_SECTION_ENTER
#define FSP_CRITICAL_SECTION_ENTER \
old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \
FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET)
#endif
/** This macro restores the previously saved interrupt state, reenabling interrupts. */
#ifndef FSP_CRITICAL_SECTION_EXIT
#define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level)
#endif
/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */
#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U)
/** Used to signify that the requested IRQ vector is not defined in this system. */
#define FSP_INVALID_VECTOR ((IRQn_Type) - 33)
/* Private definition used in bsp_clocks and R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is up to 4 bits wide. */
#if (BSP_CFG_MCU_PART_SERIES == 8)
#define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU)
#else
#define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
#endif
/* Use the secure registers for secure projects and flat projects. */
#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE
#define FSP_PRIV_TZ_USE_SECURE_REGS (1)
#else
#define FSP_PRIV_TZ_USE_SECURE_REGS (0)
#endif
/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */
#if BSP_CFG_EARLY_INIT
#define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT)
#else
#define BSP_SECTION_EARLY_INIT
#endif
#if (BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD) && BSP_FEATURE_TZ_VERSION == 2
BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
#endif
#if BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
/*
* If the STYPE3 register's security attribution is set to secure, the non-secure application must read the register
* from the secure application using the provided non-secure callable functions.
*/
#define FSP_STYPE3_REG8_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU8Read((uint8_t const volatile *) &X)))
#define FSP_STYPE3_REG16_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU16Read((uint16_t const volatile *) &X)))
#define FSP_STYPE3_REG32_READ(X, S) (!(S) ? X : (R_BSP_NSC_STYPE3_RegU32Read((uint32_t const volatile *) &X)))
#elif BSP_FEATURE_TZ_HAS_TRUSTZONE && BSP_TZ_SECURE_BUILD && BSP_FEATURE_TZ_VERSION == 2
/*******************************************************************************************************************//**
* Read a non-secure 8-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg)
{
p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*******************************************************************************************************************//**
* Read a non-secure 16-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg)
{
p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*******************************************************************************************************************//**
* Read a non-secure 32-bit STYPE3 register in the secure state.
*
* @param[in] p_reg The address of the non-secure register.
*
* @return Value read from the register.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg)
{
p_reg = (uint32_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET);
return *p_reg;
}
/*
* If the STYPE3 register's security attribution is set to non-secure, the secure application must read the register
* using the non-secure aliased address.
*/
#define FSP_STYPE3_REG8_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU8Read((uint8_t const volatile *) &X))
#define FSP_STYPE3_REG16_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU16Read((uint16_t const volatile *) &X))
#define FSP_STYPE3_REG32_READ(X, S) ((S) ? (X) : R_BSP_S_STYPE3_RegU32Read((uint32_t const volatile *) &X))
#else
#define FSP_STYPE3_REG8_READ(X, S) (X)
#define FSP_STYPE3_REG16_READ(X, S) (X)
#define FSP_STYPE3_REG32_READ(X, S) (X)
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Different warm start entry locations in the BSP. */
typedef enum e_bsp_warm_start_event
{
BSP_WARM_START_RESET = 0, /* /< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. */
BSP_WARM_START_POST_CLOCK, /* /< Called after clock initialization. No C runtime environment or IRQs. */
BSP_WARM_START_POST_C /* /< Called after clocks and C runtime environment have been set up */
} bsp_warm_start_event_t;
/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */
typedef enum e_fsp_priv_clock
{
FSP_PRIV_CLOCK_PCLKD = 0,
FSP_PRIV_CLOCK_PCLKC = 4,
FSP_PRIV_CLOCK_PCLKB = 8,
FSP_PRIV_CLOCK_PCLKA = 12,
FSP_PRIV_CLOCK_BCLK = 16,
FSP_PRIV_CLOCK_PCLKE = 20,
FSP_PRIV_CLOCK_ICLK = 24,
FSP_PRIV_CLOCK_FCLK = 28,
FSP_PRIV_CLOCK_CPUCLK = 32,
} fsp_priv_clock_t;
/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */
typedef enum e_fsp_priv_source_clock
{
FSP_PRIV_CLOCK_HOCO = 0, /* /< The high speed on chip oscillator */
FSP_PRIV_CLOCK_MOCO = 1, /* /< The middle speed on chip oscillator */
FSP_PRIV_CLOCK_LOCO = 2, /* /< The low speed on chip oscillator */
FSP_PRIV_CLOCK_MAIN_OSC = 3, /* /< The main oscillator */
FSP_PRIV_CLOCK_SUBCLOCK = 4, /* /< The subclock oscillator */
FSP_PRIV_CLOCK_PLL = 5, /* /< The PLL output */
FSP_PRIV_CLOCK_PLL1P = 5, /* /< The PLL1P output */
FSP_PRIV_CLOCK_PLL2 = 6, /* /< The PLL2 output */
FSP_PRIV_CLOCK_PLL2P = 6, /* /< The PLL2P output */
FSP_PRIV_CLOCK_PLL1Q = 7, /* /< The PLL1Q output */
FSP_PRIV_CLOCK_PLL1R = 8, /* /< The PLL1R output */
FSP_PRIV_CLOCK_PLL2Q = 9, /* /< The PLL2Q output */
FSP_PRIV_CLOCK_PLL2R = 10, /* /< The PLL2R output */
} fsp_priv_source_clock_t;
typedef struct st_bsp_unique_id
{
union
{
uint32_t unique_id_words[4];
uint8_t unique_id_bytes[16];
};
} bsp_unique_id_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock);
/***********************************************************************************************************************
* Global variables (defined in other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Inline Functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Return active interrupt vector number value
*
* @return Active interrupt vector number value
**********************************************************************************************************************/
__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
{
xPSR_Type xpsr_value;
xpsr_value.w = __get_xPSR();
return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS);
}
/*******************************************************************************************************************//**
* Gets the frequency of a system clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
{
#if !BSP_FEATURE_CGC_REGISTER_SET_B
uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK;
#if BSP_FEATURE_CGC_HAS_CPUCLK
if (FSP_PRIV_CLOCK_CPUCLK == clock)
{
return SystemCoreClock;
}
/* Get CPUCLK divisor */
uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK;
/* Determine if either divisor is a multiple of 3 */
if ((cpuclk_div | clock_div) & 8U)
{
/* Convert divisor settings to their actual values */
cpuclk_div = (cpuclk_div & 8U) ? (3U << (cpuclk_div & 7U)) : (1U << cpuclk_div);
clock_div = (clock_div & 8U) ? (3U << (clock_div & 7U)) : (1U << clock_div);
/* Calculate clock with multiplication and division instead of shifting */
return (SystemCoreClock * cpuclk_div) / clock_div;
}
else
{
return (SystemCoreClock << cpuclk_div) >> clock_div;
}
#else
uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK;
return (SystemCoreClock << iclk_div) >> clock_div;
#endif
#else
FSP_PARAMETER_NOT_USED(clock);
return SystemCoreClock;
#endif
}
/*******************************************************************************************************************//**
* Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
*
* @return Clock Divider
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
{
if (2U >= ckdivcr)
{
/* clock_div:
* - Clock Divided by 1: 0
* - Clock Divided by 2: 1
* - Clock Divided by 4: 2
*/
return 1U << ckdivcr;
}
else if (3U == ckdivcr)
{
/* Clock Divided by 6 */
return 6U;
}
else if (4U == ckdivcr)
{
/* Clock Divided by 8 */
return 8U;
}
else if (5U == ckdivcr)
{
/* Clock Divided by 3 */
return 3U;
}
else if (6U == ckdivcr)
{
/* Clock Divided by 5 */
return 5;
}
else if (7U == ckdivcr)
{
/* Clock Divided by 10 */
return 10;
}
else
{
/* The remaining case is ckdivcr = 8 which divides the clock by 16. */
}
/* Clock Divided by 16 */
return 16U;
}
#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SCI/SPI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void)
{
uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR;
uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL;
return R_BSP_SourceClockHzGet(scispicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SPI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SPI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SpiClockHzGet (void)
{
uint32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t spicksel =
(fsp_priv_source_clock_t) ((FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKCR,
BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >>
R_SYSTEM_SPICKCR_CKSEL_Pos);
return R_BSP_SourceClockHzGet(spicksel) / clock_div;
}
#endif
#if BSP_FEATURE_BSP_HAS_SCI_CLOCK
/*******************************************************************************************************************//**
* Gets the frequency of a SCI clock.
*
* @return Frequency of requested clock in Hertz.
**********************************************************************************************************************/
__STATIC_INLINE uint32_t R_FSP_SciClockHzGet (void)
{
uint32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE);
uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK);
fsp_priv_source_clock_t scicksel =
(fsp_priv_source_clock_t) (FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKCR,
BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >>
R_SYSTEM_SCICKCR_SCICKSEL_Pos);
return R_BSP_SourceClockHzGet(scicksel) / clock_div;
}
#endif
/*******************************************************************************************************************//**
* Get unique ID for this device.
*
* @return A pointer to the unique identifier structure
**********************************************************************************************************************/
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
{
#if BSP_FEATURE_TZ_VERSION == 2 && BSP_TZ_NONSECURE_BUILD == 1
return (bsp_unique_id_t *) (BSP_FEATURE_BSP_UNIQUE_ID_POINTER | BSP_FEATURE_TZ_NS_OFFSET);
#else
return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER;
#endif
}
/*******************************************************************************************************************//**
* Disables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheDisable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
R_FCACHE->FCACHEE = 0U;
#endif
#ifdef R_CACHE
#if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 2
/* Writeback and flush cache when disabling
* MREF_INTERNAL_12 */
if (R_CACHE->CCAWTA_b.WT)
{
R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk;
}
else
{
R_CACHE->CCACTL = R_CACHE_CCACTL_FC_Msk | R_CACHE_CCACTL_WB_Msk;
}
FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U);
#else
/* Disable the C-Cache. */
R_CACHE->CCACTL = 0U;
#endif
#endif
}
/*******************************************************************************************************************//**
* Enables the flash cache.
**********************************************************************************************************************/
__STATIC_INLINE void R_BSP_FlashCacheEnable (void)
{
#if BSP_FEATURE_BSP_FLASH_CACHE
/* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache
* in the RA6M3 manual R01UH0878EJ0100). */
R_FCACHE->FCACHEIV = 1U;
FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U);
/* Enable flash cache. */
R_FCACHE->FCACHEE = 1U;
#endif
#ifdef R_CACHE
#if BSP_FEATURE_BSP_CODE_CACHE_VERSION == 1
/* Configure the C-Cache line size. */
R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE;
#else
/* Check that no flush or writeback are ongoing before enabling
* MREF_INTERNAL_13 */
FSP_HARDWARE_REGISTER_WAIT(R_CACHE->CCAFCT, 0U);
#endif
/* Enable the C-Cache. */
R_CACHE->CCACTL = 1U;
#endif
}
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
#if (1 == BSP_CFG_ASSERT)
/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */
void fsp_error_log(fsp_err_t err, const char * file, int32_t line);
#endif
/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will
* alert the user of the error. The user can override this default behavior by defining their own
* BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
*/
#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR)
#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x))
#endif
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
#ifndef BSP_COMPILER_SUPPORT_H
#define BSP_COMPILER_SUPPORT_H
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
#include "arm_cmse.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if defined(__ARMCC_VERSION) /* AC6 compiler */
/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load
* memory (ROM) is reserved unnecessarily. */
#define BSP_UNINIT_SECTION_PREFIX ".bss"
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap"
#endif
#define BSP_DONT_REMOVE __attribute__((used))
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__GNUC__) /* GCC compiler */
#define BSP_UNINIT_SECTION_PREFIX
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP ".heap"
#endif
#define BSP_DONT_REMOVE __attribute__((used))
#define BSP_ATTRIBUTE_STACKLESS __attribute__((naked))
#define BSP_FORCE_INLINE __attribute__((always_inline))
#elif defined(__ICCARM__) /* IAR compiler */
#define BSP_UNINIT_SECTION_PREFIX
#ifndef BSP_SECTION_HEAP
#define BSP_SECTION_HEAP "HEAP"
#endif
#define BSP_DONT_REMOVE __root
#define BSP_ATTRIBUTE_STACKLESS __stackless
#define BSP_FORCE_INLINE _Pragma("inline=forced")
#endif
#ifndef BSP_SECTION_STACK
#define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack"
#endif
#ifndef BSP_SECTION_FLASH_GAP
#define BSP_SECTION_FLASH_GAP
#endif
#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit"
#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors"
#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors"
#define BSP_SECTION_ROM_REGISTERS ".rom_registers"
#define BSP_SECTION_ID_CODE ".id_code"
/* Compiler neutral macros. */
#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__))
#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x)))
#define BSP_PACKED __attribute__((aligned(1))) /* DEPRECATED */
#define BSP_WEAK_REFERENCE __attribute__((weak))
/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */
#define BSP_STACK_ALIGNMENT (8)
/***********************************************************************************************************************
* TrustZone definitions
**********************************************************************************************************************/
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__)
#if defined(__ICCARM__) /* IAR compiler */
#define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call
#define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry
#else
#define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call))
#define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
#endif
#else
#define BSP_CMSE_NONSECURE_CALL
#define BSP_CMSE_NONSECURE_ENTRY
#endif
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end of addtogroup BSP_MCU) */
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#include "bsp_delay.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BSP_DELAY_NS_PER_SECOND (1000000000)
#define BSP_DELAY_US_PER_SECOND (1000000)
#define BSP_DELAY_NS_PER_US (1000)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private function prototypes
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Delay for at least the specified duration in units and return.
* @param[in] delay The number of 'units' to delay.
* @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are:
* BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n
* For example:@n
* At 1 MHz one cycle takes 1 microsecond (.000001 seconds).@n
* At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.@n
* Therefore one run through bsp_prv_software_delay_loop() takes:
* ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns.
* A delay of 2 us therefore requires 2000ns/332ns or 6 loops.
*
* The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate.
* @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds.
* @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds
*
* Note that requests for very large delays will be affected by rounding in the calculations and the actual delay
* achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.
*
* Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called
* at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the
* overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
*
* @note This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires
* that the BSP has already initialized the CGC (which it does as part of the Sysinit).
* Care should be taken to ensure this remains the case if in the future this function were to be called as part
* of the BSP initialization.
*
* @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number
* of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified.
* Approximate overhead for this function is as follows:
* - CM4: 20-50 cycles
* - CM33: 10-60 cycles
* - CM23: 75-200 cycles
*
* @note If more accurate microsecond timing must be performed in software it is recommended to use
* bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE()
* to convert a calculated delay cycle count to a number of software delay loops.
*
* @note Delays may be longer than expected when compiler optimization is turned off.
*
* @warning The delay will be longer than specified on CM23 devices when the core clock is greater than 32 MHz. Setting
* BSP_DELAY_LOOP_CYCLES to 6 will improve accuracy at 48 MHz but will result in shorter than expected delays
* at lower speeds.
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
{
uint32_t iclk_hz;
uint32_t loops_required = 0;
uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */
iclk_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */
#if (BSP_CFG_MCU_PART_SERIES == 8)
if (iclk_hz >= BSP_MOCO_HZ)
{
/* For larger system clock values the below calculation in the else causes inaccurate delays due to rounding errors:
*
* ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz
*
* For system clock values greater than the MOCO speed the following delay calculation is used instead.
*/
uint32_t cycles_per_us = iclk_hz / (BSP_DELAY_US_PER_SECOND * BSP_DELAY_LOOP_CYCLES);
uint64_t loops_required_u64 = ((uint64_t) total_us) * cycles_per_us;
if (loops_required_u64 > UINT32_MAX)
{
loops_required = UINT32_MAX;
}
else
{
loops_required = (uint32_t) loops_required_u64;
}
}
else
#endif
{
uint32_t cycles_requested;
uint32_t ns_per_cycle;
uint64_t ns_64bits;
/* Running on the Sub-clock (32768 Hz) there are 30517 ns/cycle. This means one cycle takes 31 us. One execution
* loop of the delay_loop takes 6 cycles which at 32768 Hz is 180 us. That does not include the overhead below prior to even getting
* to the delay loop. Given this, at this frequency anything less then a delay request of 122 us will not even generate a single
* pass through the delay loop. For this reason small delays (<=~200 us) at this slow clock rate will not be possible and such a request
* will generate a minimum delay of ~200 us.*/
ns_per_cycle = BSP_DELAY_NS_PER_SECOND / iclk_hz; /** Get the # of nanoseconds/cycle. */
/* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */
/* division as that pulls in a division library. */
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; /* Convert to ns. */
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
/* No, we will not overflow. */
cycles_requested = ((uint32_t) ns_64bits / ns_per_cycle);
loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES;
}
else
{
/* We did overflow. Try dividing down first. */
total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES));
ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; /* Convert to ns. */
/* Have we overflowed 32 bits? */
if (ns_64bits <= UINT32_MAX)
{
/* No, we will not overflow. */
loops_required = (uint32_t) ns_64bits;
}
else
{
/* We still overflowed, use the max count for cycles */
loops_required = UINT32_MAX;
}
}
}
/** Only delay if the supplied parameters constitute a delay. */
if (loops_required > (uint32_t) 0)
{
bsp_prv_software_delay_loop(loops_required);
}
}
/** @} (end addtogroup BSP_MCU) */
/*******************************************************************************************************************//**
* This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles
* occur when the loop exits. The 'naked' attribute indicates that the specified function does not need
* prologue/epilogue sequences generated by the compiler.
* @param[in] loop_cnt The number of loops to iterate.
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop (__attribute__(
(unused)) uint32_t loop_cnt)
{
__asm volatile (
#if defined(RENESAS_CORTEX_M85) && (defined(__ARMCC_VERSION) || defined(__GNUC__))
/* Align the branch target to a 64-bit boundary, a CM85 specific optimization. */
/* IAR does not support alignment control within inline assembly. */
".balign 8\n"
#endif
"sw_delay_loop: \n"
#if defined(__ICCARM__) || defined(__ARMCC_VERSION) || (defined(__llvm__) && !defined(__CLANG_TIDY__))
" subs r0, #1 \n" /* /< 1 cycle */
#elif defined(__GNUC__)
" sub r0, r0, #1 \n" /* /< 1 cycle */
#endif
" cmp r0, #0 \n" /* /< 1 cycle */
/* CM0 and CM23 have a different instruction set */
#if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC)
" bne sw_delay_loop \n" /* /< 2 cycles */
#else
" bne.n sw_delay_loop \n" /* /< 2 cycles */
#endif
" bx lr \n"); /* /< 2 cycles */
}

74
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSP_DELAY_H
#define BSP_DELAY_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "bsp_compiler_support.h"
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/* The number of cycles required per software delay loop. */
#ifndef BSP_DELAY_LOOP_CYCLES
#if defined(RENESAS_CORTEX_M85)
/* On M85 cores, code alignment can affect execution speed. bsp_prv_software_delay_loop is aligned to 8 bytes for
* GCC and AC6, but IAR does not support aligning code. The below ensures the correct loop cycle count is used in
* this case. */
#if defined(__ICCARM__)
#define BSP_DELAY_LOOP_CYCLES (((uint32_t) bsp_prv_software_delay_loop & 0x6) ? 2 : 1)
#else
#define BSP_DELAY_LOOP_CYCLES (1)
#endif
#else
#define BSP_DELAY_LOOP_CYCLES (4)
#endif
#endif
/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle
* count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures
* the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count
* of 0. */
#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U)
/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */
typedef enum
{
BSP_DELAY_UNITS_SECONDS = 1000000, /* /< Requested delay amount is in seconds */
BSP_DELAY_UNITS_MILLISECONDS = 1000, /* /< Requested delay amount is in milliseconds */
BSP_DELAY_UNITS_MICROSECONDS = 1 /* /< Requested delay amount is in microseconds */
} bsp_delay_units_t;
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/** @} (end addtogroup BSP_MCU) */
#ifndef BSP_EXCEPTIONS_H
#define BSP_EXCEPTIONS_H
#ifdef __cplusplus
extern "C" {
#endif
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */
typedef enum IRQn
{
Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */
HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */
MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */
UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */
SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor */
PendSV_IRQn = -2, /* 14 Pendable request for system service */
SysTick_IRQn = -1, /* 15 System Tick Timer */
} IRQn_Type;
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#if (BSP_FEATURE_ICU_NMIER_MAX_INDEX > 15U)
#define BSP_PRV_NMIER_T uint32_t
#else
#define BSP_PRV_NMIER_T uint16_t
#endif
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** This array holds callback functions. */
bsp_grp_irq_cb_t g_bsp_group_irq_sources[BSP_FEATURE_ICU_NMIER_MAX_INDEX + 1] BSP_SECTION_EARLY_INIT;
void NMI_Handler(void);
static void bsp_group_irq_call(bsp_grp_irq_t irq);
/*******************************************************************************************************************//**
* Calls the callback function for an interrupt if a callback has been registered.
*
* @param[in] irq Which interrupt to check and possibly call.
*
* @retval FSP_SUCCESS Callback was called.
* @retval FSP_ERR_INVALID_ARGUMENT No valid callback has been registered for this interrupt source.
*
* @warning This function is called from within an interrupt
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP static void bsp_group_irq_call (bsp_grp_irq_t irq)
{
/** Check for valid callback */
if (NULL != g_bsp_group_irq_sources[irq])
{
/** Callback has been found. Call it. */
g_bsp_group_irq_sources[irq](irq);
}
}
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* Register a callback function for supported interrupts. If NULL is passed for the callback argument then any
* previously registered callbacks are unregistered.
*
* @param[in] irq Interrupt for which to register a callback.
* @param[in] p_callback Pointer to function to call when interrupt occurs.
*
* @retval FSP_SUCCESS Callback registered
* @retval FSP_ERR_ASSERTION Callback pointer is NULL
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq))
{
#if BSP_CFG_PARAM_CHECKING_ENABLE
/* Check pointer for NULL value. */
FSP_ASSERT(p_callback);
#endif
/* Register callback. */
g_bsp_group_irq_sources[irq] = p_callback;
return FSP_SUCCESS;
}
/*******************************************************************************************************************//**
* Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because
* there are many sources that map to the NMI exception.
**********************************************************************************************************************/
BSP_SECTION_FLASH_GAP void NMI_Handler (void)
{
/* NMISR is masked by NMIER to prevent iterating over NMI status flags that are not enabled. */
BSP_PRV_NMIER_T nmier = R_ICU->NMIER;
BSP_PRV_NMIER_T nmisr = R_ICU->NMISR & nmier;
/* Loop over all NMI status flags */
for (bsp_grp_irq_t irq = BSP_GRP_IRQ_IWDT_ERROR; irq <= (bsp_grp_irq_t) (BSP_FEATURE_ICU_NMIER_MAX_INDEX); irq++)
{
/* If the current irq status register is set call the irq callback. */
if (0U != (nmisr & (1U << irq)))
{
(void) bsp_group_irq_call(irq);
}
}
/* Clear status flags that have been handled. */
R_ICU->NMICLR = nmisr;
#if BSP_CFG_MCU_PART_SERIES == 8
/* Wait for NMISR to be cleared before exiting the ISR to prevent the IRQ from being regenerated.
* See section "13.2.12 NMICLR : Non-Maskable Interrupt Status Clear Register" in the RA8M1 manual
* R01UH0994EJ0100 */
FSP_HARDWARE_REGISTER_WAIT((R_ICU->NMISR & nmisr), 0);
#endif
}
/** @} (end addtogroup BSP_MCU) */

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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BSP_GROUP_IRQ_H
#define BSP_GROUP_IRQ_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_GROUP_IRQ_T
/** Which interrupts can have callbacks registered. */
typedef enum e_bsp_grp_irq
{
BSP_GRP_IRQ_IWDT_ERROR = 0, /* /< IWDT underflow/refresh error has occurred */
BSP_GRP_IRQ_WDT_ERROR = 1, /* /< WDT underflow/refresh error has occurred */
BSP_GRP_IRQ_LVD1 = 2, /* /< Voltage monitoring 1 interrupt */
BSP_GRP_IRQ_LVD2 = 3, /* /< Voltage monitoring 2 interrupt */
BSP_GRP_IRQ_VBATT = 4, /* /< VBATT monitor interrupt */
BSP_GRP_IRQ_OSC_STOP_DETECT = 6, /* /< Oscillation stop is detected */
BSP_GRP_IRQ_NMI_PIN = 7, /* /< NMI Pin interrupt */
BSP_GRP_IRQ_RAM_PARITY = 8, /* /< RAM Parity Error */
BSP_GRP_IRQ_RAM_ECC = 9, /* /< RAM ECC Error */
BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, /* /< MPU Bus Slave Error */
BSP_GRP_IRQ_MPU_BUS_MASTER = 11, /* /< MPU Bus Master Error */
BSP_GRP_IRQ_MPU_STACK = 12, /* /< MPU Stack Error */
BSP_GRP_IRQ_TRUSTZONE = 13, /* /< MPU Stack Error */
BSP_GRP_IRQ_CACHE_PARITY = 15, /* /< MPU Stack Error */
} bsp_grp_irq_t;
#endif
/* Callback type. */
typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq);
/** @} (end addtogroup BSP_MCU) */
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/* Public functions defined in bsp.h */
void bsp_group_interrupt_open(void); /* Used internally by BSP */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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bsp/renesas/ra4e2-eco/ra/fsp/src/bsp/mcu/all/bsp_guard.c Normal file
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/*
* Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "bsp_guard.h"
/* Only the secure project has nonsecure callable functions. */
#if BSP_TZ_SECURE_BUILD
/* If the CGG Security Attribution is configured to secure access only. */
#if BSP_CFG_CLOCKS_SECURE == 1
/*******************************************************************************************************************//**
* Set the callback used by the secure project to notify the nonsecure project when the clock settings have changed.
*
* @retval FSP_SUCCESS Callback set.
* @retval FSP_ERR_ASSERTION An input parameter is invalid.
**********************************************************************************************************************/
BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet (bsp_clock_update_callback_t p_callback,
bsp_clock_update_callback_args_t * p_callback_memory)
{
bsp_clock_update_callback_t p_callback_checked =
(bsp_clock_update_callback_t) cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE);
bsp_clock_update_callback_args_t * p_callback_memory_checked =
(bsp_clock_update_callback_args_t *) cmse_check_address_range(p_callback_memory,
sizeof(bsp_clock_update_callback_args_t),
CMSE_AU_NONSECURE);
FSP_ASSERT(p_callback == p_callback_checked);
FSP_ASSERT(p_callback_memory == p_callback_memory_checked);
r_bsp_clock_update_callback_set(p_callback_checked, p_callback_memory_checked);
return FSP_SUCCESS;
}
#endif
#endif

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