mirror of https://github.com/RT-Thread/rt-thread
*** EFM32 branch ***
1. Move file, "start_gcc.S", from "libcpu/arm/cortex-m3/" to "bsp/efm32/"
2. Upgrade EFM32 driver libraries (CMSIS and efm32lib) to version 2.2.2
3. Upgrade EFM32 G2xx development kit drivers (EFM32_Gxxx_DK) to version 1.7.2 (from version 1.6.0)
4. Modify the files ("drv_usart.c" and "drv_iic.c") according to the driver libraries upgrading
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1818 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
onelife.real
parent
1b3411abde
commit
ed9828226a
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@ -2,7 +2,7 @@
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* @file
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* @brief DVK board support package, initialization
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -32,16 +32,23 @@
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/**************************************************************************//**
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* @brief Initializes DVK, configures board control access
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*****************************************************************************/
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void DVK_init(void)
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bool DVK_init(void)
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{
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bool ret;
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#ifdef DVK_EBI_CONTROL
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DVK_EBI_init();
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ret = DVK_EBI_init();
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#endif
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#ifdef DVK_SPI_CONTROL
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DVK_SPI_init();
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ret = DVK_SPI_init();
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#endif
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if ( ret == false )
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{
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/* Board is configured in wrong mode, please restart KIT! */
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while(1);
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}
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/* Inform AEM application that we are in Energy Mode 0 by default */
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DVK_setEnergyMode(0);
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return ret;
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}
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/**************************************************************************//**
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@ -2,7 +2,7 @@
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* @file
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* @brief DVK Board Support, master header file
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -30,6 +30,7 @@
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#define __DVK_H
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#include <stdint.h>
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#include <stdbool.h>
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#include "dvk_boardcontrol.h"
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#include "dvk_bcregisters.h"
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@ -92,15 +93,19 @@
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#endif
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#endif
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/* EBI access */
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void DVK_EBI_init(void);
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void DVK_EBI_disable(void);
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* EBI access */
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bool DVK_EBI_init(void);
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void DVK_EBI_disable(void);
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void DVK_EBI_configure(void);
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void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data);
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uint16_t DVK_EBI_readRegister(volatile uint16_t *addr);
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/* SPI access */
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void DVK_SPI_init(void);
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bool DVK_SPI_init(void);
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void DVK_SPI_disable(void);
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void DVK_SPI_writeRegister(volatile uint16_t *addr, uint16_t data);
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@ -119,7 +124,12 @@ uint16_t DVK_SPI_readRegister(volatile uint16_t *addr);
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#endif
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/* General initialization routines */
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void DVK_init(void);
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bool DVK_init(void);
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void DVK_disable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -2,7 +2,7 @@
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* @file
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* @brief Board Control register definitions
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -2,7 +2,7 @@
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* @file
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* @brief DVK Peripheral Board Control API implementation
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -2,7 +2,7 @@
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* @file
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* @brief DVK Peripheral Board Control, prototypes and definitions
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -4,7 +4,7 @@
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* This implementation works for devices w/o LCD display on the
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* MCU module, specifically the EFM32_G2xx_DK development board
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -34,7 +34,7 @@
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#include "dvk.h"
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#include "dvk_bcregisters.h"
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#if defined(EBI_PRESENT)
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/**************************************************************************//**
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* @brief Configure EBI (external bus interface) for Board Control register
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* access
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@ -64,7 +64,8 @@ void DVK_EBI_configure(void)
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CMU_ClockEnable(cmuClock_EBI, true);
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CMU_ClockEnable(cmuClock_GPIO, true);
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/* Configure bus connect PC bit 12 active low */
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/* Configure mode - disable SPI, enable EBI */
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GPIO_PinModeSet(gpioPortC, 13, gpioModePushPull, 1);
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GPIO_PinModeSet(gpioPortC, 12, gpioModePushPull, 0);
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/* Configure GPIO pins as push pull */
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@ -135,11 +136,12 @@ void DVK_EBI_configure(void)
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/**************************************************************************//**
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* @brief Initialize EBI
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* access
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* @return true on success, false on failure
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*****************************************************************************/
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void DVK_EBI_init(void)
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bool DVK_EBI_init(void)
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{
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uint16_t ebiMagic;
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int ctr;
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int retry = 10;
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/* Disable all GPIO pins and register */
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DVK_EBI_disable();
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/* Verify that EBI access is working, if not kit is in SPI mode and needs to
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* be configured for EBI access */
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ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
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if (ebiMagic != BC_MAGIC_VALUE)
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while ((ebiMagic != BC_MAGIC_VALUE) && retry)
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{
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/* Disable EBI */
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DVK_EBI_disable();
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/* Enable SPI interface */
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DVK_SPI_init();
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/* Set EBI mode - after this SPI access will no longer be available */
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ebiMagic = DVK_SPI_readRegister(BC_MAGIC);
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DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
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/* Disable SPI */
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DVK_SPI_disable();
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/* Now setup EBI again */
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DVK_EBI_configure();
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/* Wait until ready */
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ctr = 0;
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do
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{
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/* Check if FPGA responds */
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ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
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ctr++;
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DVK_EBI_writeRegister(BC_LED, ctr);
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} while (ebiMagic != BC_MAGIC_VALUE);
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if (ebiMagic == BC_MAGIC_VALUE) break;
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retry--;
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}
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if ( ! retry ) return false;
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DVK_EBI_writeRegister(BC_LED, retry);
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return true;
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}
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/**************************************************************************//**
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*****************************************************************************/
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void DVK_EBI_disable(void)
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{
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/* Disable EBI controller */
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EBI_Disable();
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/* Disable EBI clock in CMU */
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CMU_ClockEnable(cmuClock_EBI, false);
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/* Disable EBI _BC_BUS_CONNECT */
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/* Disable EBI and SPI _BC_BUS_CONNECT */
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GPIO_PinModeSet(gpioPortC, 12, gpioModeDisabled, 0);
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GPIO_PinModeSet(gpioPortC, 13, gpioModeDisabled, 0);
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/* Configure GPIO pins as disabled */
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GPIO_PinModeSet(gpioPortA, 0, gpioModeDisabled, 0);
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GPIO_PinModeSet(gpioPortF, 3, gpioModeDisabled, 0);
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GPIO_PinModeSet(gpioPortF, 4, gpioModeDisabled, 0);
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GPIO_PinModeSet(gpioPortF, 5, gpioModeDisabled, 0);
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/* Disable EBI controller */
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#if 0
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EBI_Disable();
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#endif
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/* Disable EBI clock in CMU */
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CMU_ClockEnable(cmuClock_EBI, false);
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}
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/**************************************************************************//**
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{
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return *addr;
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}
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#endif
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@ -4,7 +4,7 @@
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* This implementation use the USART2 SPI interface to control board
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* control registers. It works
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* @author Energy Micro AS
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* @version 1.6.0
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* @version 1.7.2
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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@ -27,7 +27,6 @@
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* arising from your use of this Software.
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*
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*****************************************************************************/
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#include <stdio.h>
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#include "efm32.h"
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#include "efm32_usart.h"
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@ -36,6 +35,26 @@
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#include "dvk.h"
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#include "dvk_bcregisters.h"
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#ifdef _EFM32_TINY_FAMILY
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/* USART used for SPI access */
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#define USART_USED USART0
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#define USART_CLK cmuClock_USART0
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/* GPIO pins used, please refer to DVK user guide. */
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#define PIN_SPIBUS_CONNECT 13
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#define PORT_SPIBUS_CONNECT gpioPortC
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#define PIN_SPI_TX 10
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#define PORT_SPI_TX gpioPortE
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#define PIN_SPI_RX 11
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#define PORT_SPI_RX gpioPortE
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#define PIN_SPI_CLK 12
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#define PORT_SPI_CLK gpioPortE
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#define PIN_SPI_CS 13
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#define PORT_SPI_CS gpioPortE
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#else
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/* USART used for SPI access */
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#define USART_USED USART2
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#define USART_CLK cmuClock_USART2
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/* GPIO pins used, please refer to DVK user guide. */
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#define PIN_SPIBUS_CONNECT 13
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#define PORT_SPIBUS_CONNECT gpioPortC
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#define PIN_EBIBUS_CONNECT 12
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#define PORT_EBIBUS_CONNECT gpioPortC
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#define PIN_SPI_TX 2
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#define PORT_SPI_TX gpioPortC
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#define PIN_SPI_RX 3
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@ -52,6 +73,8 @@
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#define PIN_SPI_CS 5
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#define PORT_SPI_CS gpioPortC
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#endif
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static volatile uint16_t *lastAddr = NULL;
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/**************************************************************************//**
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@ -67,8 +90,9 @@ static void spiInit(void)
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CMU_ClockEnable(cmuClock_HFPER, true);
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CMU_ClockEnable(USART_CLK, true);
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/* Configure SPI bus connect pins, DOUT set to 0 */
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/* Configure SPI bus connect pins, DOUT set to 0, disable EBI */
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GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModePushPull, 0);
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GPIO_PinModeSet(PORT_EBIBUS_CONNECT, PIN_EBIBUS_CONNECT, gpioModePushPull, 1);
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/* Configure SPI pins */
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GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0);
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@ -77,18 +101,15 @@ static void spiInit(void)
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/* Keep CS high to not activate slave */
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GPIO_PinModeSet(PORT_SPI_CS, PIN_SPI_CS, gpioModePushPull, 1);
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/* Enable pins at default location */
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USART_USED->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN;
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/* Reset USART just in case */
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USART_Reset(USART_USED);
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/* Configure to use SPI master with manual CS */
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/* For now, configure SPI for worst case 32MHz clock in order to work for all */
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/* configurations. */
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init.refFreq = 32000000;
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init.baudrate = 7000000;
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USART_InitSync(USART_USED, &init);
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/* Enable pins at default location */
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USART_USED->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN;
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}
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/**************************************************************************//**
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@ -98,11 +119,12 @@ static void spiDisable(void)
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{
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USART_Reset(USART_USED);
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/* Route setup must be reset separately */
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USART_USED->ROUTE = _USART_ROUTE_RESETVALUE;
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/* Disable LCD_SELECT */
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GPIO_PinModeSet(gpioPortD, 13, gpioModeDisabled, 0);
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/* Disable SPI pins */
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GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPIBUS_CONNECT, 13, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPIBUS_CONNECT, 12, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModeDisabled, 0);
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GPIO_PinModeSet(PORT_SPI_CLK, PIN_SPI_CLK, gpioModeDisabled, 0);
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@ -164,8 +186,9 @@ static uint16_t spiRead(uint8_t spiadr, uint16_t spidata)
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/**************************************************************************//**
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* @brief Initializes DVK register access
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* @return true on success, false on failure
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*****************************************************************************/
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void DVK_SPI_init(void)
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bool DVK_SPI_init(void)
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{
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uint16_t spiMagic;
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@ -174,12 +197,13 @@ void DVK_SPI_init(void)
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/* if not FPGA is configured to be in EBI mode */
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spiMagic = DVK_SPI_readRegister(BC_MAGIC);
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if (spiMagic != BC_MAGIC_VALUE)
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if(spiMagic != BC_MAGIC_VALUE)
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{
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/* Development Kit is configured to use EBI mode, restart of kit required */
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/* to use SPI for configuration */
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spiDisable();
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while (1) ;
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return false;
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}
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else
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{
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return true;
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}
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}
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|
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@ -9,7 +9,7 @@
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* Add "#include "efm32.h" to your source files
|
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* @endverbatim
|
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* @author Energy Micro AS
|
||||
* @version 2.0.0
|
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* @version 2.2.2
|
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******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
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|
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@ -130,6 +130,306 @@
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#elif defined(EFM32G890F64)
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#include "efm32g890f64.h"
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#elif defined(EFM32GG230F1024)
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#include "efm32gg230f1024.h"
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#elif defined(EFM32GG230F512)
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#include "efm32gg230f512.h"
|
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#elif defined(EFM32GG232F1024)
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#include "efm32gg232f1024.h"
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#elif defined(EFM32GG232F512)
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#include "efm32gg232f512.h"
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#elif defined(EFM32GG280F1024)
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#include "efm32gg280f1024.h"
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#elif defined(EFM32GG280F512)
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#include "efm32gg280f512.h"
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#elif defined(EFM32GG290F1024)
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#include "efm32gg290f1024.h"
|
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#elif defined(EFM32GG290F512)
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#include "efm32gg290f512.h"
|
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|
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#elif defined(EFM32GG295F1024)
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#include "efm32gg295f1024.h"
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#elif defined(EFM32GG295F512)
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#include "efm32gg295f512.h"
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#elif defined(EFM32GG330F1024)
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#include "efm32gg330f1024.h"
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#elif defined(EFM32GG330F512)
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#include "efm32gg330f512.h"
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#elif defined(EFM32GG332F1024)
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#include "efm32gg332f1024.h"
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#elif defined(EFM32GG332F512)
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#include "efm32gg332f512.h"
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#elif defined(EFM32GG380F1024)
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#include "efm32gg380f1024.h"
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#elif defined(EFM32GG380F512)
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#include "efm32gg380f512.h"
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#elif defined(EFM32GG390F1024)
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#include "efm32gg390f1024.h"
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|
||||
#elif defined(EFM32GG390F512)
|
||||
#include "efm32gg390f512.h"
|
||||
|
||||
#elif defined(EFM32GG395F1024)
|
||||
#include "efm32gg395f1024.h"
|
||||
|
||||
#elif defined(EFM32GG395F512)
|
||||
#include "efm32gg395f512.h"
|
||||
|
||||
#elif defined(EFM32GG840F1024)
|
||||
#include "efm32gg840f1024.h"
|
||||
|
||||
#elif defined(EFM32GG840F512)
|
||||
#include "efm32gg840f512.h"
|
||||
|
||||
#elif defined(EFM32GG842F1024)
|
||||
#include "efm32gg842f1024.h"
|
||||
|
||||
#elif defined(EFM32GG842F512)
|
||||
#include "efm32gg842f512.h"
|
||||
|
||||
#elif defined(EFM32GG880F1024)
|
||||
#include "efm32gg880f1024.h"
|
||||
|
||||
#elif defined(EFM32GG880F512)
|
||||
#include "efm32gg880f512.h"
|
||||
|
||||
#elif defined(EFM32GG890F1024)
|
||||
#include "efm32gg890f1024.h"
|
||||
|
||||
#elif defined(EFM32GG890F512)
|
||||
#include "efm32gg890f512.h"
|
||||
|
||||
#elif defined(EFM32GG895F1024)
|
||||
#include "efm32gg895f1024.h"
|
||||
|
||||
#elif defined(EFM32GG895F512)
|
||||
#include "efm32gg895f512.h"
|
||||
|
||||
#elif defined(EFM32GG940F1024)
|
||||
#include "efm32gg940f1024.h"
|
||||
|
||||
#elif defined(EFM32GG940F512)
|
||||
#include "efm32gg940f512.h"
|
||||
|
||||
#elif defined(EFM32GG942F1024)
|
||||
#include "efm32gg942f1024.h"
|
||||
|
||||
#elif defined(EFM32GG942F512)
|
||||
#include "efm32gg942f512.h"
|
||||
|
||||
#elif defined(EFM32GG980F1024)
|
||||
#include "efm32gg980f1024.h"
|
||||
|
||||
#elif defined(EFM32GG980F512)
|
||||
#include "efm32gg980f512.h"
|
||||
|
||||
#elif defined(EFM32GG990F1024)
|
||||
#include "efm32gg990f1024.h"
|
||||
|
||||
#elif defined(EFM32GG990F512)
|
||||
#include "efm32gg990f512.h"
|
||||
|
||||
#elif defined(EFM32GG995F1024)
|
||||
#include "efm32gg995f1024.h"
|
||||
|
||||
#elif defined(EFM32GG995F512)
|
||||
#include "efm32gg995f512.h"
|
||||
|
||||
#elif defined(EFM32LG230F128)
|
||||
#include "efm32lg230f128.h"
|
||||
|
||||
#elif defined(EFM32LG230F256)
|
||||
#include "efm32lg230f256.h"
|
||||
|
||||
#elif defined(EFM32LG230F64)
|
||||
#include "efm32lg230f64.h"
|
||||
|
||||
#elif defined(EFM32LG232F128)
|
||||
#include "efm32lg232f128.h"
|
||||
|
||||
#elif defined(EFM32LG232F256)
|
||||
#include "efm32lg232f256.h"
|
||||
|
||||
#elif defined(EFM32LG232F64)
|
||||
#include "efm32lg232f64.h"
|
||||
|
||||
#elif defined(EFM32LG280F128)
|
||||
#include "efm32lg280f128.h"
|
||||
|
||||
#elif defined(EFM32LG280F256)
|
||||
#include "efm32lg280f256.h"
|
||||
|
||||
#elif defined(EFM32LG280F64)
|
||||
#include "efm32lg280f64.h"
|
||||
|
||||
#elif defined(EFM32LG290F128)
|
||||
#include "efm32lg290f128.h"
|
||||
|
||||
#elif defined(EFM32LG290F256)
|
||||
#include "efm32lg290f256.h"
|
||||
|
||||
#elif defined(EFM32LG290F64)
|
||||
#include "efm32lg290f64.h"
|
||||
|
||||
#elif defined(EFM32LG295F128)
|
||||
#include "efm32lg295f128.h"
|
||||
|
||||
#elif defined(EFM32LG295F256)
|
||||
#include "efm32lg295f256.h"
|
||||
|
||||
#elif defined(EFM32LG295F64)
|
||||
#include "efm32lg295f64.h"
|
||||
|
||||
#elif defined(EFM32LG330F128)
|
||||
#include "efm32lg330f128.h"
|
||||
|
||||
#elif defined(EFM32LG330F256)
|
||||
#include "efm32lg330f256.h"
|
||||
|
||||
#elif defined(EFM32LG330F64)
|
||||
#include "efm32lg330f64.h"
|
||||
|
||||
#elif defined(EFM32LG332F128)
|
||||
#include "efm32lg332f128.h"
|
||||
|
||||
#elif defined(EFM32LG332F256)
|
||||
#include "efm32lg332f256.h"
|
||||
|
||||
#elif defined(EFM32LG332F64)
|
||||
#include "efm32lg332f64.h"
|
||||
|
||||
#elif defined(EFM32LG380F128)
|
||||
#include "efm32lg380f128.h"
|
||||
|
||||
#elif defined(EFM32LG380F256)
|
||||
#include "efm32lg380f256.h"
|
||||
|
||||
#elif defined(EFM32LG380F64)
|
||||
#include "efm32lg380f64.h"
|
||||
|
||||
#elif defined(EFM32LG390F128)
|
||||
#include "efm32lg390f128.h"
|
||||
|
||||
#elif defined(EFM32LG390F256)
|
||||
#include "efm32lg390f256.h"
|
||||
|
||||
#elif defined(EFM32LG390F64)
|
||||
#include "efm32lg390f64.h"
|
||||
|
||||
#elif defined(EFM32LG395F128)
|
||||
#include "efm32lg395f128.h"
|
||||
|
||||
#elif defined(EFM32LG395F256)
|
||||
#include "efm32lg395f256.h"
|
||||
|
||||
#elif defined(EFM32LG395F64)
|
||||
#include "efm32lg395f64.h"
|
||||
|
||||
#elif defined(EFM32LG840F128)
|
||||
#include "efm32lg840f128.h"
|
||||
|
||||
#elif defined(EFM32LG840F256)
|
||||
#include "efm32lg840f256.h"
|
||||
|
||||
#elif defined(EFM32LG840F64)
|
||||
#include "efm32lg840f64.h"
|
||||
|
||||
#elif defined(EFM32LG842F128)
|
||||
#include "efm32lg842f128.h"
|
||||
|
||||
#elif defined(EFM32LG842F256)
|
||||
#include "efm32lg842f256.h"
|
||||
|
||||
#elif defined(EFM32LG842F64)
|
||||
#include "efm32lg842f64.h"
|
||||
|
||||
#elif defined(EFM32LG880F128)
|
||||
#include "efm32lg880f128.h"
|
||||
|
||||
#elif defined(EFM32LG880F256)
|
||||
#include "efm32lg880f256.h"
|
||||
|
||||
#elif defined(EFM32LG880F64)
|
||||
#include "efm32lg880f64.h"
|
||||
|
||||
#elif defined(EFM32LG890F128)
|
||||
#include "efm32lg890f128.h"
|
||||
|
||||
#elif defined(EFM32LG890F256)
|
||||
#include "efm32lg890f256.h"
|
||||
|
||||
#elif defined(EFM32LG890F64)
|
||||
#include "efm32lg890f64.h"
|
||||
|
||||
#elif defined(EFM32LG895F128)
|
||||
#include "efm32lg895f128.h"
|
||||
|
||||
#elif defined(EFM32LG895F256)
|
||||
#include "efm32lg895f256.h"
|
||||
|
||||
#elif defined(EFM32LG895F64)
|
||||
#include "efm32lg895f64.h"
|
||||
|
||||
#elif defined(EFM32LG940F128)
|
||||
#include "efm32lg940f128.h"
|
||||
|
||||
#elif defined(EFM32LG940F256)
|
||||
#include "efm32lg940f256.h"
|
||||
|
||||
#elif defined(EFM32LG940F64)
|
||||
#include "efm32lg940f64.h"
|
||||
|
||||
#elif defined(EFM32LG942F128)
|
||||
#include "efm32lg942f128.h"
|
||||
|
||||
#elif defined(EFM32LG942F256)
|
||||
#include "efm32lg942f256.h"
|
||||
|
||||
#elif defined(EFM32LG942F64)
|
||||
#include "efm32lg942f64.h"
|
||||
|
||||
#elif defined(EFM32LG980F128)
|
||||
#include "efm32lg980f128.h"
|
||||
|
||||
#elif defined(EFM32LG980F256)
|
||||
#include "efm32lg980f256.h"
|
||||
|
||||
#elif defined(EFM32LG980F64)
|
||||
#include "efm32lg980f64.h"
|
||||
|
||||
#elif defined(EFM32LG990F128)
|
||||
#include "efm32lg990f128.h"
|
||||
|
||||
#elif defined(EFM32LG990F256)
|
||||
#include "efm32lg990f256.h"
|
||||
|
||||
#elif defined(EFM32LG990F64)
|
||||
#include "efm32lg990f64.h"
|
||||
|
||||
#elif defined(EFM32LG995F128)
|
||||
#include "efm32lg995f128.h"
|
||||
|
||||
#elif defined(EFM32LG995F256)
|
||||
#include "efm32lg995f256.h"
|
||||
|
||||
#elif defined(EFM32LG995F64)
|
||||
#include "efm32lg995f64.h"
|
||||
|
||||
#elif defined(EFM32TG108F16)
|
||||
#include "efm32tg108f16.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G200F16
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -83,8 +83,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_Core EFM32G200F16 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -109,34 +109,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G200F16" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G200F16 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -203,14 +203,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_Peripheral_TypeDefs EFM32G200F16 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_MSC EFM32G200F16 MSC
|
||||
* @brief EFM32G200F16_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -234,8 +234,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_EMU EFM32G200F16 EMU
|
||||
* @brief EFM32G200F16_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_RMU EFM32G200F16 RMU
|
||||
* @brief EFM32G200F16_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_CMU EFM32G200F16 CMU
|
||||
* @brief EFM32G200F16_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -320,8 +320,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_GPIO EFM32G200F16 GPIO
|
||||
* @brief EFM32G200F16_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -352,8 +352,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_PRS EFM32G200F16 PRS
|
||||
* @brief EFM32G200F16_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -375,8 +375,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_DMA EFM32G200F16 DMA
|
||||
* @brief EFM32G200F16_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -427,8 +427,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_TIMER EFM32G200F16 TIMER
|
||||
* @brief EFM32G200F16_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_USART EFM32G200F16 USART
|
||||
* @brief EFM32G200F16_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -491,8 +491,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_LEUART EFM32G200F16 LEUART
|
||||
* @brief EFM32G200F16_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -522,8 +522,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_LETIMER EFM32G200F16 LETIMER
|
||||
* @brief EFM32G200F16_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -549,8 +549,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_PCNT EFM32G200F16 PCNT
|
||||
* @brief EFM32G200F16_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -572,8 +572,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_I2C EFM32G200F16 I2C
|
||||
* @brief EFM32G200F16_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -596,8 +596,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_ADC EFM32G200F16 ADC
|
||||
* @brief EFM32G200F16_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -622,8 +622,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_DAC EFM32G200F16 DAC
|
||||
* @brief EFM32G200F16_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -644,8 +644,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_ACMP EFM32G200F16 ACMP
|
||||
* @brief EFM32G200F16_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -661,8 +661,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_VCMP EFM32G200F16 VCMP
|
||||
* @brief EFM32G200F16_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_RTC EFM32G200F16 RTC
|
||||
* @brief EFM32G200F16_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_WDOG EFM32G200F16 WDOG
|
||||
* @brief EFM32G200F16_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F16_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -802,31 +802,31 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G200F16_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -836,7 +836,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_PRS EFM32G200F16 PRS
|
||||
* @addtogroup EFM32G200F16_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6086,7 +6086,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -9789,31 +9789,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_MSC_BitFields EFM32G200F16_MSC Bit Fields
|
||||
* @addtogroup EFM32G200F16_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G200F16_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_EMU_BitFields EFM32G200F16_EMU Bit Fields
|
||||
* @addtogroup EFM32G200F16_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G200F16_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_CMU_BitFields EFM32G200F16_CMU Bit Fields
|
||||
* @addtogroup EFM32G200F16_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G200F16_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_GPIO_BitFields EFM32G200F16_GPIO Bit Fields
|
||||
* @addtogroup EFM32G200F16_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G200F16_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F16_TIMER_BitFields EFM32G200F16_TIMER Bit Fields
|
||||
* @addtogroup EFM32G200F16_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10180,254 +10180,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G200F16_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G200F16_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10444,7 +10196,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G200F16 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G200F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -83,8 +83,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_Core EFM32G200F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -109,34 +109,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G200F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G200F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -203,14 +203,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_Peripheral_TypeDefs EFM32G200F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_MSC EFM32G200F32 MSC
|
||||
* @brief EFM32G200F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -234,8 +234,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_EMU EFM32G200F32 EMU
|
||||
* @brief EFM32G200F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_RMU EFM32G200F32 RMU
|
||||
* @brief EFM32G200F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_CMU EFM32G200F32 CMU
|
||||
* @brief EFM32G200F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -320,8 +320,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_GPIO EFM32G200F32 GPIO
|
||||
* @brief EFM32G200F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -352,8 +352,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_PRS EFM32G200F32 PRS
|
||||
* @brief EFM32G200F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -375,8 +375,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_DMA EFM32G200F32 DMA
|
||||
* @brief EFM32G200F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -427,8 +427,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_TIMER EFM32G200F32 TIMER
|
||||
* @brief EFM32G200F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_USART EFM32G200F32 USART
|
||||
* @brief EFM32G200F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -491,8 +491,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_LEUART EFM32G200F32 LEUART
|
||||
* @brief EFM32G200F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -522,8 +522,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_LETIMER EFM32G200F32 LETIMER
|
||||
* @brief EFM32G200F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -549,8 +549,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_PCNT EFM32G200F32 PCNT
|
||||
* @brief EFM32G200F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -572,8 +572,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_I2C EFM32G200F32 I2C
|
||||
* @brief EFM32G200F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -596,8 +596,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_ADC EFM32G200F32 ADC
|
||||
* @brief EFM32G200F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -622,8 +622,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_DAC EFM32G200F32 DAC
|
||||
* @brief EFM32G200F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -644,8 +644,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_ACMP EFM32G200F32 ACMP
|
||||
* @brief EFM32G200F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -661,8 +661,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_VCMP EFM32G200F32 VCMP
|
||||
* @brief EFM32G200F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_RTC EFM32G200F32 RTC
|
||||
* @brief EFM32G200F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_WDOG EFM32G200F32 WDOG
|
||||
* @brief EFM32G200F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -802,31 +802,31 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G200F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -836,7 +836,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_PRS EFM32G200F32 PRS
|
||||
* @addtogroup EFM32G200F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6086,7 +6086,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -9789,31 +9789,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_MSC_BitFields EFM32G200F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G200F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G200F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_EMU_BitFields EFM32G200F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G200F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G200F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_CMU_BitFields EFM32G200F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G200F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G200F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_GPIO_BitFields EFM32G200F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G200F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G200F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F32_TIMER_BitFields EFM32G200F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G200F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10180,254 +10180,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G200F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G200F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10444,7 +10196,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G200F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G200F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -83,8 +83,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_Core EFM32G200F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -109,34 +109,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G200F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G200F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -203,14 +203,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_Peripheral_TypeDefs EFM32G200F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_MSC EFM32G200F64 MSC
|
||||
* @brief EFM32G200F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -234,8 +234,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_EMU EFM32G200F64 EMU
|
||||
* @brief EFM32G200F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_RMU EFM32G200F64 RMU
|
||||
* @brief EFM32G200F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_CMU EFM32G200F64 CMU
|
||||
* @brief EFM32G200F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -320,8 +320,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_GPIO EFM32G200F64 GPIO
|
||||
* @brief EFM32G200F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -352,8 +352,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_PRS EFM32G200F64 PRS
|
||||
* @brief EFM32G200F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -375,8 +375,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_DMA EFM32G200F64 DMA
|
||||
* @brief EFM32G200F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -427,8 +427,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_TIMER EFM32G200F64 TIMER
|
||||
* @brief EFM32G200F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_USART EFM32G200F64 USART
|
||||
* @brief EFM32G200F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -491,8 +491,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_LEUART EFM32G200F64 LEUART
|
||||
* @brief EFM32G200F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -522,8 +522,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_LETIMER EFM32G200F64 LETIMER
|
||||
* @brief EFM32G200F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -549,8 +549,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_PCNT EFM32G200F64 PCNT
|
||||
* @brief EFM32G200F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -572,8 +572,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_I2C EFM32G200F64 I2C
|
||||
* @brief EFM32G200F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -596,8 +596,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_ADC EFM32G200F64 ADC
|
||||
* @brief EFM32G200F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -622,8 +622,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_DAC EFM32G200F64 DAC
|
||||
* @brief EFM32G200F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -644,8 +644,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_ACMP EFM32G200F64 ACMP
|
||||
* @brief EFM32G200F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -661,8 +661,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_VCMP EFM32G200F64 VCMP
|
||||
* @brief EFM32G200F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_RTC EFM32G200F64 RTC
|
||||
* @brief EFM32G200F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_WDOG EFM32G200F64 WDOG
|
||||
* @brief EFM32G200F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G200F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -802,31 +802,31 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G200F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -836,7 +836,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_PRS EFM32G200F64 PRS
|
||||
* @addtogroup EFM32G200F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6086,7 +6086,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -9789,31 +9789,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_MSC_BitFields EFM32G200F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G200F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G200F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_EMU_BitFields EFM32G200F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G200F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G200F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_CMU_BitFields EFM32G200F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G200F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G200F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_GPIO_BitFields EFM32G200F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G200F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G200F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G200F64_TIMER_BitFields EFM32G200F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G200F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10180,254 +10180,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G200F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G200F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10444,7 +10196,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G200F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G210F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -84,8 +84,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_Core EFM32G210F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -110,34 +110,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G210F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G210F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -206,14 +206,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_Peripheral_TypeDefs EFM32G210F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_MSC EFM32G210F128 MSC
|
||||
* @brief EFM32G210F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -237,8 +237,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_EMU EFM32G210F128 EMU
|
||||
* @brief EFM32G210F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_RMU EFM32G210F128 RMU
|
||||
* @brief EFM32G210F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_CMU EFM32G210F128 CMU
|
||||
* @brief EFM32G210F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -307,8 +307,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_AES EFM32G210F128 AES
|
||||
* @brief EFM32G210F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -350,8 +350,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_GPIO EFM32G210F128 GPIO
|
||||
* @brief EFM32G210F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -382,8 +382,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_PRS EFM32G210F128 PRS
|
||||
* @brief EFM32G210F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -405,8 +405,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_DMA EFM32G210F128 DMA
|
||||
* @brief EFM32G210F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -457,8 +457,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_TIMER EFM32G210F128 TIMER
|
||||
* @brief EFM32G210F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -490,8 +490,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_USART EFM32G210F128 USART
|
||||
* @brief EFM32G210F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -521,8 +521,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_LEUART EFM32G210F128 LEUART
|
||||
* @brief EFM32G210F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -552,8 +552,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_LETIMER EFM32G210F128 LETIMER
|
||||
* @brief EFM32G210F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_PCNT EFM32G210F128 PCNT
|
||||
* @brief EFM32G210F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -602,8 +602,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_I2C EFM32G210F128 I2C
|
||||
* @brief EFM32G210F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -626,8 +626,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_ADC EFM32G210F128 ADC
|
||||
* @brief EFM32G210F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -652,8 +652,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_DAC EFM32G210F128 DAC
|
||||
* @brief EFM32G210F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -674,8 +674,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_ACMP EFM32G210F128 ACMP
|
||||
* @brief EFM32G210F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -691,8 +691,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_VCMP EFM32G210F128 VCMP
|
||||
* @brief EFM32G210F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -707,8 +707,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_RTC EFM32G210F128 RTC
|
||||
* @brief EFM32G210F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -727,8 +727,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_WDOG EFM32G210F128 WDOG
|
||||
* @brief EFM32G210F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G210F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -833,32 +833,32 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G210F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -868,7 +868,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_PRS EFM32G210F128 PRS
|
||||
* @addtogroup EFM32G210F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6118,7 +6118,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10010,31 +10010,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_MSC_BitFields EFM32G210F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G210F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G210F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_EMU_BitFields EFM32G210F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G210F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G210F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_CMU_BitFields EFM32G210F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G210F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G210F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_GPIO_BitFields EFM32G210F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G210F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G210F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G210F128_TIMER_BitFields EFM32G210F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G210F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10401,254 +10401,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G210F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G210F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10665,7 +10417,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G210F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G222F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -87,8 +87,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_Core EFM32G222F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -113,34 +113,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G222F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G222F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -209,14 +209,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_Peripheral_TypeDefs EFM32G222F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_MSC EFM32G222F128 MSC
|
||||
* @brief EFM32G222F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -240,8 +240,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_EMU EFM32G222F128 EMU
|
||||
* @brief EFM32G222F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -255,8 +255,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_RMU EFM32G222F128 RMU
|
||||
* @brief EFM32G222F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_CMU EFM32G222F128 CMU
|
||||
* @brief EFM32G222F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -310,8 +310,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_AES EFM32G222F128 AES
|
||||
* @brief EFM32G222F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -353,8 +353,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_GPIO EFM32G222F128 GPIO
|
||||
* @brief EFM32G222F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -385,8 +385,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_PRS EFM32G222F128 PRS
|
||||
* @brief EFM32G222F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -408,8 +408,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_DMA EFM32G222F128 DMA
|
||||
* @brief EFM32G222F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_TIMER EFM32G222F128 TIMER
|
||||
* @brief EFM32G222F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -493,8 +493,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_USART EFM32G222F128 USART
|
||||
* @brief EFM32G222F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -524,8 +524,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_LEUART EFM32G222F128 LEUART
|
||||
* @brief EFM32G222F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -555,8 +555,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_LETIMER EFM32G222F128 LETIMER
|
||||
* @brief EFM32G222F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -582,8 +582,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_PCNT EFM32G222F128 PCNT
|
||||
* @brief EFM32G222F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -605,8 +605,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_I2C EFM32G222F128 I2C
|
||||
* @brief EFM32G222F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_ADC EFM32G222F128 ADC
|
||||
* @brief EFM32G222F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_DAC EFM32G222F128 DAC
|
||||
* @brief EFM32G222F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_ACMP EFM32G222F128 ACMP
|
||||
* @brief EFM32G222F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -694,8 +694,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_VCMP EFM32G222F128 VCMP
|
||||
* @brief EFM32G222F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -710,8 +710,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_RTC EFM32G222F128 RTC
|
||||
* @brief EFM32G222F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -730,8 +730,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_WDOG EFM32G222F128 WDOG
|
||||
* @brief EFM32G222F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -839,35 +839,35 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G222F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -877,7 +877,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_PRS EFM32G222F128 PRS
|
||||
* @addtogroup EFM32G222F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6132,7 +6132,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10088,31 +10088,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_MSC_BitFields EFM32G222F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G222F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G222F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_EMU_BitFields EFM32G222F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G222F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G222F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_CMU_BitFields EFM32G222F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G222F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G222F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_GPIO_BitFields EFM32G222F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G222F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G222F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F128_TIMER_BitFields EFM32G222F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G222F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10479,254 +10479,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G222F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G222F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10743,7 +10495,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G222F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G222F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -87,8 +87,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_Core EFM32G222F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -113,34 +113,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G222F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G222F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -209,14 +209,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_Peripheral_TypeDefs EFM32G222F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_MSC EFM32G222F32 MSC
|
||||
* @brief EFM32G222F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -240,8 +240,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_EMU EFM32G222F32 EMU
|
||||
* @brief EFM32G222F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -255,8 +255,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_RMU EFM32G222F32 RMU
|
||||
* @brief EFM32G222F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_CMU EFM32G222F32 CMU
|
||||
* @brief EFM32G222F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -310,8 +310,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_AES EFM32G222F32 AES
|
||||
* @brief EFM32G222F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -353,8 +353,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_GPIO EFM32G222F32 GPIO
|
||||
* @brief EFM32G222F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -385,8 +385,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_PRS EFM32G222F32 PRS
|
||||
* @brief EFM32G222F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -408,8 +408,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_DMA EFM32G222F32 DMA
|
||||
* @brief EFM32G222F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_TIMER EFM32G222F32 TIMER
|
||||
* @brief EFM32G222F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -493,8 +493,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_USART EFM32G222F32 USART
|
||||
* @brief EFM32G222F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -524,8 +524,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_LEUART EFM32G222F32 LEUART
|
||||
* @brief EFM32G222F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -555,8 +555,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_LETIMER EFM32G222F32 LETIMER
|
||||
* @brief EFM32G222F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -582,8 +582,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_PCNT EFM32G222F32 PCNT
|
||||
* @brief EFM32G222F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -605,8 +605,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_I2C EFM32G222F32 I2C
|
||||
* @brief EFM32G222F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_ADC EFM32G222F32 ADC
|
||||
* @brief EFM32G222F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_DAC EFM32G222F32 DAC
|
||||
* @brief EFM32G222F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_ACMP EFM32G222F32 ACMP
|
||||
* @brief EFM32G222F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -694,8 +694,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_VCMP EFM32G222F32 VCMP
|
||||
* @brief EFM32G222F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -710,8 +710,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_RTC EFM32G222F32 RTC
|
||||
* @brief EFM32G222F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -730,8 +730,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_WDOG EFM32G222F32 WDOG
|
||||
* @brief EFM32G222F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -839,35 +839,35 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G222F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -877,7 +877,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_PRS EFM32G222F32 PRS
|
||||
* @addtogroup EFM32G222F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6132,7 +6132,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10088,31 +10088,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_MSC_BitFields EFM32G222F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G222F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G222F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_EMU_BitFields EFM32G222F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G222F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G222F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_CMU_BitFields EFM32G222F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G222F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G222F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_GPIO_BitFields EFM32G222F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G222F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G222F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F32_TIMER_BitFields EFM32G222F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G222F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10479,254 +10479,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G222F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G222F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10743,7 +10495,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G222F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G222F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -87,8 +87,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_Core EFM32G222F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -113,34 +113,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G222F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G222F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -209,14 +209,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_Peripheral_TypeDefs EFM32G222F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_MSC EFM32G222F64 MSC
|
||||
* @brief EFM32G222F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -240,8 +240,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_EMU EFM32G222F64 EMU
|
||||
* @brief EFM32G222F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -255,8 +255,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_RMU EFM32G222F64 RMU
|
||||
* @brief EFM32G222F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_CMU EFM32G222F64 CMU
|
||||
* @brief EFM32G222F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -310,8 +310,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_AES EFM32G222F64 AES
|
||||
* @brief EFM32G222F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -353,8 +353,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_GPIO EFM32G222F64 GPIO
|
||||
* @brief EFM32G222F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -385,8 +385,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_PRS EFM32G222F64 PRS
|
||||
* @brief EFM32G222F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -408,8 +408,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_DMA EFM32G222F64 DMA
|
||||
* @brief EFM32G222F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -460,8 +460,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_TIMER EFM32G222F64 TIMER
|
||||
* @brief EFM32G222F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -493,8 +493,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_USART EFM32G222F64 USART
|
||||
* @brief EFM32G222F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -524,8 +524,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_LEUART EFM32G222F64 LEUART
|
||||
* @brief EFM32G222F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -555,8 +555,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_LETIMER EFM32G222F64 LETIMER
|
||||
* @brief EFM32G222F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -582,8 +582,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_PCNT EFM32G222F64 PCNT
|
||||
* @brief EFM32G222F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -605,8 +605,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_I2C EFM32G222F64 I2C
|
||||
* @brief EFM32G222F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_ADC EFM32G222F64 ADC
|
||||
* @brief EFM32G222F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_DAC EFM32G222F64 DAC
|
||||
* @brief EFM32G222F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -677,8 +677,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_ACMP EFM32G222F64 ACMP
|
||||
* @brief EFM32G222F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -694,8 +694,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_VCMP EFM32G222F64 VCMP
|
||||
* @brief EFM32G222F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -710,8 +710,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_RTC EFM32G222F64 RTC
|
||||
* @brief EFM32G222F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -730,8 +730,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_WDOG EFM32G222F64 WDOG
|
||||
* @brief EFM32G222F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G222F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -839,35 +839,35 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G222F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -877,7 +877,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_PRS EFM32G222F64 PRS
|
||||
* @addtogroup EFM32G222F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6132,7 +6132,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10088,31 +10088,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_MSC_BitFields EFM32G222F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G222F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G222F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_EMU_BitFields EFM32G222F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G222F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G222F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_CMU_BitFields EFM32G222F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G222F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G222F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_GPIO_BitFields EFM32G222F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G222F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G222F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G222F64_TIMER_BitFields EFM32G222F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G222F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10479,254 +10479,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G222F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G222F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10743,7 +10495,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G222F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G230F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_Core EFM32G230F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G230F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G230F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_Peripheral_TypeDefs EFM32G230F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_MSC EFM32G230F128 MSC
|
||||
* @brief EFM32G230F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_EMU EFM32G230F128 EMU
|
||||
* @brief EFM32G230F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_RMU EFM32G230F128 RMU
|
||||
* @brief EFM32G230F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_CMU EFM32G230F128 CMU
|
||||
* @brief EFM32G230F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_AES EFM32G230F128 AES
|
||||
* @brief EFM32G230F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_GPIO EFM32G230F128 GPIO
|
||||
* @brief EFM32G230F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_PRS EFM32G230F128 PRS
|
||||
* @brief EFM32G230F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_DMA EFM32G230F128 DMA
|
||||
* @brief EFM32G230F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_TIMER EFM32G230F128 TIMER
|
||||
* @brief EFM32G230F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_USART EFM32G230F128 USART
|
||||
* @brief EFM32G230F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_LEUART EFM32G230F128 LEUART
|
||||
* @brief EFM32G230F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_LETIMER EFM32G230F128 LETIMER
|
||||
* @brief EFM32G230F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_PCNT EFM32G230F128 PCNT
|
||||
* @brief EFM32G230F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_I2C EFM32G230F128 I2C
|
||||
* @brief EFM32G230F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_ADC EFM32G230F128 ADC
|
||||
* @brief EFM32G230F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_DAC EFM32G230F128 DAC
|
||||
* @brief EFM32G230F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_ACMP EFM32G230F128 ACMP
|
||||
* @brief EFM32G230F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_VCMP EFM32G230F128 VCMP
|
||||
* @brief EFM32G230F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_RTC EFM32G230F128 RTC
|
||||
* @brief EFM32G230F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_WDOG EFM32G230F128 WDOG
|
||||
* @brief EFM32G230F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G230F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_PRS EFM32G230F128 PRS
|
||||
* @addtogroup EFM32G230F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_MSC_BitFields EFM32G230F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G230F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G230F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_EMU_BitFields EFM32G230F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G230F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G230F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_CMU_BitFields EFM32G230F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G230F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G230F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_GPIO_BitFields EFM32G230F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G230F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G230F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F128_TIMER_BitFields EFM32G230F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G230F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G230F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G230F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G230F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G230F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_Core EFM32G230F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G230F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G230F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_Peripheral_TypeDefs EFM32G230F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_MSC EFM32G230F32 MSC
|
||||
* @brief EFM32G230F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_EMU EFM32G230F32 EMU
|
||||
* @brief EFM32G230F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_RMU EFM32G230F32 RMU
|
||||
* @brief EFM32G230F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_CMU EFM32G230F32 CMU
|
||||
* @brief EFM32G230F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_AES EFM32G230F32 AES
|
||||
* @brief EFM32G230F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_GPIO EFM32G230F32 GPIO
|
||||
* @brief EFM32G230F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_PRS EFM32G230F32 PRS
|
||||
* @brief EFM32G230F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_DMA EFM32G230F32 DMA
|
||||
* @brief EFM32G230F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_TIMER EFM32G230F32 TIMER
|
||||
* @brief EFM32G230F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_USART EFM32G230F32 USART
|
||||
* @brief EFM32G230F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_LEUART EFM32G230F32 LEUART
|
||||
* @brief EFM32G230F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_LETIMER EFM32G230F32 LETIMER
|
||||
* @brief EFM32G230F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_PCNT EFM32G230F32 PCNT
|
||||
* @brief EFM32G230F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_I2C EFM32G230F32 I2C
|
||||
* @brief EFM32G230F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_ADC EFM32G230F32 ADC
|
||||
* @brief EFM32G230F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_DAC EFM32G230F32 DAC
|
||||
* @brief EFM32G230F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_ACMP EFM32G230F32 ACMP
|
||||
* @brief EFM32G230F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_VCMP EFM32G230F32 VCMP
|
||||
* @brief EFM32G230F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_RTC EFM32G230F32 RTC
|
||||
* @brief EFM32G230F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_WDOG EFM32G230F32 WDOG
|
||||
* @brief EFM32G230F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G230F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_PRS EFM32G230F32 PRS
|
||||
* @addtogroup EFM32G230F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_MSC_BitFields EFM32G230F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G230F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G230F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_EMU_BitFields EFM32G230F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G230F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G230F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_CMU_BitFields EFM32G230F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G230F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G230F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_GPIO_BitFields EFM32G230F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G230F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G230F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F32_TIMER_BitFields EFM32G230F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G230F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G230F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G230F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G230F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G230F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_Core EFM32G230F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G230F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G230F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_Peripheral_TypeDefs EFM32G230F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_MSC EFM32G230F64 MSC
|
||||
* @brief EFM32G230F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_EMU EFM32G230F64 EMU
|
||||
* @brief EFM32G230F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_RMU EFM32G230F64 RMU
|
||||
* @brief EFM32G230F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_CMU EFM32G230F64 CMU
|
||||
* @brief EFM32G230F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_AES EFM32G230F64 AES
|
||||
* @brief EFM32G230F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_GPIO EFM32G230F64 GPIO
|
||||
* @brief EFM32G230F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_PRS EFM32G230F64 PRS
|
||||
* @brief EFM32G230F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_DMA EFM32G230F64 DMA
|
||||
* @brief EFM32G230F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_TIMER EFM32G230F64 TIMER
|
||||
* @brief EFM32G230F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_USART EFM32G230F64 USART
|
||||
* @brief EFM32G230F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_LEUART EFM32G230F64 LEUART
|
||||
* @brief EFM32G230F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_LETIMER EFM32G230F64 LETIMER
|
||||
* @brief EFM32G230F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_PCNT EFM32G230F64 PCNT
|
||||
* @brief EFM32G230F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_I2C EFM32G230F64 I2C
|
||||
* @brief EFM32G230F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_ADC EFM32G230F64 ADC
|
||||
* @brief EFM32G230F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_DAC EFM32G230F64 DAC
|
||||
* @brief EFM32G230F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_ACMP EFM32G230F64 ACMP
|
||||
* @brief EFM32G230F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_VCMP EFM32G230F64 VCMP
|
||||
* @brief EFM32G230F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_RTC EFM32G230F64 RTC
|
||||
* @brief EFM32G230F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_WDOG EFM32G230F64 WDOG
|
||||
* @brief EFM32G230F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G230F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G230F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_PRS EFM32G230F64 PRS
|
||||
* @addtogroup EFM32G230F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_MSC_BitFields EFM32G230F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G230F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G230F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_EMU_BitFields EFM32G230F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G230F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G230F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_CMU_BitFields EFM32G230F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G230F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G230F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_GPIO_BitFields EFM32G230F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G230F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G230F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G230F64_TIMER_BitFields EFM32G230F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G230F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G230F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G230F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G230F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G232F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_Core EFM32G232F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G232F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G232F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_Peripheral_TypeDefs EFM32G232F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_MSC EFM32G232F128 MSC
|
||||
* @brief EFM32G232F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_EMU EFM32G232F128 EMU
|
||||
* @brief EFM32G232F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_RMU EFM32G232F128 RMU
|
||||
* @brief EFM32G232F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_CMU EFM32G232F128 CMU
|
||||
* @brief EFM32G232F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_AES EFM32G232F128 AES
|
||||
* @brief EFM32G232F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_GPIO EFM32G232F128 GPIO
|
||||
* @brief EFM32G232F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_PRS EFM32G232F128 PRS
|
||||
* @brief EFM32G232F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_DMA EFM32G232F128 DMA
|
||||
* @brief EFM32G232F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_TIMER EFM32G232F128 TIMER
|
||||
* @brief EFM32G232F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_USART EFM32G232F128 USART
|
||||
* @brief EFM32G232F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_LEUART EFM32G232F128 LEUART
|
||||
* @brief EFM32G232F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_LETIMER EFM32G232F128 LETIMER
|
||||
* @brief EFM32G232F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_PCNT EFM32G232F128 PCNT
|
||||
* @brief EFM32G232F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_I2C EFM32G232F128 I2C
|
||||
* @brief EFM32G232F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_ADC EFM32G232F128 ADC
|
||||
* @brief EFM32G232F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_DAC EFM32G232F128 DAC
|
||||
* @brief EFM32G232F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_ACMP EFM32G232F128 ACMP
|
||||
* @brief EFM32G232F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_VCMP EFM32G232F128 VCMP
|
||||
* @brief EFM32G232F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_RTC EFM32G232F128 RTC
|
||||
* @brief EFM32G232F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_WDOG EFM32G232F128 WDOG
|
||||
* @brief EFM32G232F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G232F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_PRS EFM32G232F128 PRS
|
||||
* @addtogroup EFM32G232F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_MSC_BitFields EFM32G232F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G232F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G232F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_EMU_BitFields EFM32G232F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G232F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G232F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_CMU_BitFields EFM32G232F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G232F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G232F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_GPIO_BitFields EFM32G232F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G232F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G232F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F128_TIMER_BitFields EFM32G232F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G232F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G232F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G232F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G232F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G232F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_Core EFM32G232F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G232F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G232F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_Peripheral_TypeDefs EFM32G232F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_MSC EFM32G232F32 MSC
|
||||
* @brief EFM32G232F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_EMU EFM32G232F32 EMU
|
||||
* @brief EFM32G232F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_RMU EFM32G232F32 RMU
|
||||
* @brief EFM32G232F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_CMU EFM32G232F32 CMU
|
||||
* @brief EFM32G232F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_AES EFM32G232F32 AES
|
||||
* @brief EFM32G232F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_GPIO EFM32G232F32 GPIO
|
||||
* @brief EFM32G232F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_PRS EFM32G232F32 PRS
|
||||
* @brief EFM32G232F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_DMA EFM32G232F32 DMA
|
||||
* @brief EFM32G232F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_TIMER EFM32G232F32 TIMER
|
||||
* @brief EFM32G232F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_USART EFM32G232F32 USART
|
||||
* @brief EFM32G232F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_LEUART EFM32G232F32 LEUART
|
||||
* @brief EFM32G232F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_LETIMER EFM32G232F32 LETIMER
|
||||
* @brief EFM32G232F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_PCNT EFM32G232F32 PCNT
|
||||
* @brief EFM32G232F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_I2C EFM32G232F32 I2C
|
||||
* @brief EFM32G232F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_ADC EFM32G232F32 ADC
|
||||
* @brief EFM32G232F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_DAC EFM32G232F32 DAC
|
||||
* @brief EFM32G232F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_ACMP EFM32G232F32 ACMP
|
||||
* @brief EFM32G232F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_VCMP EFM32G232F32 VCMP
|
||||
* @brief EFM32G232F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_RTC EFM32G232F32 RTC
|
||||
* @brief EFM32G232F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_WDOG EFM32G232F32 WDOG
|
||||
* @brief EFM32G232F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G232F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_PRS EFM32G232F32 PRS
|
||||
* @addtogroup EFM32G232F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_MSC_BitFields EFM32G232F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G232F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G232F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_EMU_BitFields EFM32G232F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G232F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G232F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_CMU_BitFields EFM32G232F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G232F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G232F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_GPIO_BitFields EFM32G232F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G232F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G232F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F32_TIMER_BitFields EFM32G232F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G232F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G232F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G232F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G232F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G232F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -90,8 +90,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_Core EFM32G232F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -116,34 +116,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G232F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G232F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -212,14 +212,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_Peripheral_TypeDefs EFM32G232F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_MSC EFM32G232F64 MSC
|
||||
* @brief EFM32G232F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -243,8 +243,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_EMU EFM32G232F64 EMU
|
||||
* @brief EFM32G232F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -258,8 +258,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_RMU EFM32G232F64 RMU
|
||||
* @brief EFM32G232F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -270,8 +270,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_CMU EFM32G232F64 CMU
|
||||
* @brief EFM32G232F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -313,8 +313,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_AES EFM32G232F64 AES
|
||||
* @brief EFM32G232F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -356,8 +356,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_GPIO EFM32G232F64 GPIO
|
||||
* @brief EFM32G232F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -388,8 +388,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_PRS EFM32G232F64 PRS
|
||||
* @brief EFM32G232F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_DMA EFM32G232F64 DMA
|
||||
* @brief EFM32G232F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -463,8 +463,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_TIMER EFM32G232F64 TIMER
|
||||
* @brief EFM32G232F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -496,8 +496,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_USART EFM32G232F64 USART
|
||||
* @brief EFM32G232F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -527,8 +527,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_LEUART EFM32G232F64 LEUART
|
||||
* @brief EFM32G232F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -558,8 +558,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_LETIMER EFM32G232F64 LETIMER
|
||||
* @brief EFM32G232F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -585,8 +585,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_PCNT EFM32G232F64 PCNT
|
||||
* @brief EFM32G232F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_I2C EFM32G232F64 I2C
|
||||
* @brief EFM32G232F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -632,8 +632,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_ADC EFM32G232F64 ADC
|
||||
* @brief EFM32G232F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -658,8 +658,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_DAC EFM32G232F64 DAC
|
||||
* @brief EFM32G232F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -680,8 +680,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_ACMP EFM32G232F64 ACMP
|
||||
* @brief EFM32G232F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -697,8 +697,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_VCMP EFM32G232F64 VCMP
|
||||
* @brief EFM32G232F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -713,8 +713,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_RTC EFM32G232F64 RTC
|
||||
* @brief EFM32G232F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -733,8 +733,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_WDOG EFM32G232F64 WDOG
|
||||
* @brief EFM32G232F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G232F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -844,37 +844,37 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G232F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -884,7 +884,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_PRS EFM32G232F64 PRS
|
||||
* @addtogroup EFM32G232F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6142,7 +6142,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10131,31 +10131,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_MSC_BitFields EFM32G232F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G232F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G232F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_EMU_BitFields EFM32G232F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G232F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G232F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_CMU_BitFields EFM32G232F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G232F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G232F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_GPIO_BitFields EFM32G232F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G232F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G232F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G232F64_TIMER_BitFields EFM32G232F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G232F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10522,254 +10522,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G232F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G232F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -10786,7 +10538,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G232F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G280F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_Core EFM32G280F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G280F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G280F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_Peripheral_TypeDefs EFM32G280F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_MSC EFM32G280F128 MSC
|
||||
* @brief EFM32G280F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_EMU EFM32G280F128 EMU
|
||||
* @brief EFM32G280F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_RMU EFM32G280F128 RMU
|
||||
* @brief EFM32G280F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_CMU EFM32G280F128 CMU
|
||||
* @brief EFM32G280F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_AES EFM32G280F128 AES
|
||||
* @brief EFM32G280F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_EBI EFM32G280F128 EBI
|
||||
* @brief EFM32G280F128_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_GPIO EFM32G280F128 GPIO
|
||||
* @brief EFM32G280F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_PRS EFM32G280F128 PRS
|
||||
* @brief EFM32G280F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_DMA EFM32G280F128 DMA
|
||||
* @brief EFM32G280F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_TIMER EFM32G280F128 TIMER
|
||||
* @brief EFM32G280F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_USART EFM32G280F128 USART
|
||||
* @brief EFM32G280F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_LEUART EFM32G280F128 LEUART
|
||||
* @brief EFM32G280F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_LETIMER EFM32G280F128 LETIMER
|
||||
* @brief EFM32G280F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_PCNT EFM32G280F128 PCNT
|
||||
* @brief EFM32G280F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_I2C EFM32G280F128 I2C
|
||||
* @brief EFM32G280F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_ADC EFM32G280F128 ADC
|
||||
* @brief EFM32G280F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_DAC EFM32G280F128 DAC
|
||||
* @brief EFM32G280F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_ACMP EFM32G280F128 ACMP
|
||||
* @brief EFM32G280F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_VCMP EFM32G280F128 VCMP
|
||||
* @brief EFM32G280F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_RTC EFM32G280F128 RTC
|
||||
* @brief EFM32G280F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_WDOG EFM32G280F128 WDOG
|
||||
* @brief EFM32G280F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G280F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_PRS EFM32G280F128 PRS
|
||||
* @addtogroup EFM32G280F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_MSC_BitFields EFM32G280F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G280F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G280F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_EMU_BitFields EFM32G280F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G280F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G280F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_CMU_BitFields EFM32G280F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G280F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G280F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_GPIO_BitFields EFM32G280F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G280F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G280F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F128_TIMER_BitFields EFM32G280F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G280F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G280F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G280F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G280F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G280F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_Core EFM32G280F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G280F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G280F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_Peripheral_TypeDefs EFM32G280F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_MSC EFM32G280F32 MSC
|
||||
* @brief EFM32G280F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_EMU EFM32G280F32 EMU
|
||||
* @brief EFM32G280F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_RMU EFM32G280F32 RMU
|
||||
* @brief EFM32G280F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_CMU EFM32G280F32 CMU
|
||||
* @brief EFM32G280F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_AES EFM32G280F32 AES
|
||||
* @brief EFM32G280F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_EBI EFM32G280F32 EBI
|
||||
* @brief EFM32G280F32_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_GPIO EFM32G280F32 GPIO
|
||||
* @brief EFM32G280F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_PRS EFM32G280F32 PRS
|
||||
* @brief EFM32G280F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_DMA EFM32G280F32 DMA
|
||||
* @brief EFM32G280F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_TIMER EFM32G280F32 TIMER
|
||||
* @brief EFM32G280F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_USART EFM32G280F32 USART
|
||||
* @brief EFM32G280F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_LEUART EFM32G280F32 LEUART
|
||||
* @brief EFM32G280F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_LETIMER EFM32G280F32 LETIMER
|
||||
* @brief EFM32G280F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_PCNT EFM32G280F32 PCNT
|
||||
* @brief EFM32G280F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_I2C EFM32G280F32 I2C
|
||||
* @brief EFM32G280F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_ADC EFM32G280F32 ADC
|
||||
* @brief EFM32G280F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_DAC EFM32G280F32 DAC
|
||||
* @brief EFM32G280F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_ACMP EFM32G280F32 ACMP
|
||||
* @brief EFM32G280F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_VCMP EFM32G280F32 VCMP
|
||||
* @brief EFM32G280F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_RTC EFM32G280F32 RTC
|
||||
* @brief EFM32G280F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_WDOG EFM32G280F32 WDOG
|
||||
* @brief EFM32G280F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G280F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_PRS EFM32G280F32 PRS
|
||||
* @addtogroup EFM32G280F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_MSC_BitFields EFM32G280F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G280F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G280F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_EMU_BitFields EFM32G280F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G280F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G280F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_CMU_BitFields EFM32G280F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G280F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G280F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_GPIO_BitFields EFM32G280F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G280F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G280F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F32_TIMER_BitFields EFM32G280F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G280F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G280F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G280F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G280F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G280F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_Core EFM32G280F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G280F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G280F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_Peripheral_TypeDefs EFM32G280F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_MSC EFM32G280F64 MSC
|
||||
* @brief EFM32G280F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_EMU EFM32G280F64 EMU
|
||||
* @brief EFM32G280F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_RMU EFM32G280F64 RMU
|
||||
* @brief EFM32G280F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_CMU EFM32G280F64 CMU
|
||||
* @brief EFM32G280F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_AES EFM32G280F64 AES
|
||||
* @brief EFM32G280F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_EBI EFM32G280F64 EBI
|
||||
* @brief EFM32G280F64_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_GPIO EFM32G280F64 GPIO
|
||||
* @brief EFM32G280F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_PRS EFM32G280F64 PRS
|
||||
* @brief EFM32G280F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_DMA EFM32G280F64 DMA
|
||||
* @brief EFM32G280F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_TIMER EFM32G280F64 TIMER
|
||||
* @brief EFM32G280F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_USART EFM32G280F64 USART
|
||||
* @brief EFM32G280F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_LEUART EFM32G280F64 LEUART
|
||||
* @brief EFM32G280F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_LETIMER EFM32G280F64 LETIMER
|
||||
* @brief EFM32G280F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_PCNT EFM32G280F64 PCNT
|
||||
* @brief EFM32G280F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_I2C EFM32G280F64 I2C
|
||||
* @brief EFM32G280F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_ADC EFM32G280F64 ADC
|
||||
* @brief EFM32G280F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_DAC EFM32G280F64 DAC
|
||||
* @brief EFM32G280F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_ACMP EFM32G280F64 ACMP
|
||||
* @brief EFM32G280F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_VCMP EFM32G280F64 VCMP
|
||||
* @brief EFM32G280F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_RTC EFM32G280F64 RTC
|
||||
* @brief EFM32G280F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_WDOG EFM32G280F64 WDOG
|
||||
* @brief EFM32G280F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G280F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G280F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_PRS EFM32G280F64 PRS
|
||||
* @addtogroup EFM32G280F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_MSC_BitFields EFM32G280F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G280F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G280F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_EMU_BitFields EFM32G280F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G280F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G280F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_CMU_BitFields EFM32G280F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G280F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G280F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_GPIO_BitFields EFM32G280F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G280F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G280F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G280F64_TIMER_BitFields EFM32G280F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G280F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G280F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G280F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G280F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G290F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_Core EFM32G290F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G290F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G290F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_Peripheral_TypeDefs EFM32G290F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_MSC EFM32G290F128 MSC
|
||||
* @brief EFM32G290F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_EMU EFM32G290F128 EMU
|
||||
* @brief EFM32G290F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_RMU EFM32G290F128 RMU
|
||||
* @brief EFM32G290F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_CMU EFM32G290F128 CMU
|
||||
* @brief EFM32G290F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_AES EFM32G290F128 AES
|
||||
* @brief EFM32G290F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_EBI EFM32G290F128 EBI
|
||||
* @brief EFM32G290F128_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_GPIO EFM32G290F128 GPIO
|
||||
* @brief EFM32G290F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_PRS EFM32G290F128 PRS
|
||||
* @brief EFM32G290F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_DMA EFM32G290F128 DMA
|
||||
* @brief EFM32G290F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_TIMER EFM32G290F128 TIMER
|
||||
* @brief EFM32G290F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_USART EFM32G290F128 USART
|
||||
* @brief EFM32G290F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_LEUART EFM32G290F128 LEUART
|
||||
* @brief EFM32G290F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_LETIMER EFM32G290F128 LETIMER
|
||||
* @brief EFM32G290F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_PCNT EFM32G290F128 PCNT
|
||||
* @brief EFM32G290F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_I2C EFM32G290F128 I2C
|
||||
* @brief EFM32G290F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_ADC EFM32G290F128 ADC
|
||||
* @brief EFM32G290F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_DAC EFM32G290F128 DAC
|
||||
* @brief EFM32G290F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_ACMP EFM32G290F128 ACMP
|
||||
* @brief EFM32G290F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_VCMP EFM32G290F128 VCMP
|
||||
* @brief EFM32G290F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_RTC EFM32G290F128 RTC
|
||||
* @brief EFM32G290F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_WDOG EFM32G290F128 WDOG
|
||||
* @brief EFM32G290F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G290F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_PRS EFM32G290F128 PRS
|
||||
* @addtogroup EFM32G290F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_MSC_BitFields EFM32G290F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G290F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G290F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_EMU_BitFields EFM32G290F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G290F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G290F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_CMU_BitFields EFM32G290F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G290F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G290F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_GPIO_BitFields EFM32G290F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G290F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G290F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F128_TIMER_BitFields EFM32G290F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G290F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G290F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G290F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G290F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G290F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_Core EFM32G290F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G290F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G290F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_Peripheral_TypeDefs EFM32G290F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_MSC EFM32G290F32 MSC
|
||||
* @brief EFM32G290F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_EMU EFM32G290F32 EMU
|
||||
* @brief EFM32G290F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_RMU EFM32G290F32 RMU
|
||||
* @brief EFM32G290F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_CMU EFM32G290F32 CMU
|
||||
* @brief EFM32G290F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_AES EFM32G290F32 AES
|
||||
* @brief EFM32G290F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_EBI EFM32G290F32 EBI
|
||||
* @brief EFM32G290F32_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_GPIO EFM32G290F32 GPIO
|
||||
* @brief EFM32G290F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_PRS EFM32G290F32 PRS
|
||||
* @brief EFM32G290F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_DMA EFM32G290F32 DMA
|
||||
* @brief EFM32G290F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_TIMER EFM32G290F32 TIMER
|
||||
* @brief EFM32G290F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_USART EFM32G290F32 USART
|
||||
* @brief EFM32G290F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_LEUART EFM32G290F32 LEUART
|
||||
* @brief EFM32G290F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_LETIMER EFM32G290F32 LETIMER
|
||||
* @brief EFM32G290F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_PCNT EFM32G290F32 PCNT
|
||||
* @brief EFM32G290F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_I2C EFM32G290F32 I2C
|
||||
* @brief EFM32G290F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_ADC EFM32G290F32 ADC
|
||||
* @brief EFM32G290F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_DAC EFM32G290F32 DAC
|
||||
* @brief EFM32G290F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_ACMP EFM32G290F32 ACMP
|
||||
* @brief EFM32G290F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_VCMP EFM32G290F32 VCMP
|
||||
* @brief EFM32G290F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_RTC EFM32G290F32 RTC
|
||||
* @brief EFM32G290F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_WDOG EFM32G290F32 WDOG
|
||||
* @brief EFM32G290F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G290F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_PRS EFM32G290F32 PRS
|
||||
* @addtogroup EFM32G290F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_MSC_BitFields EFM32G290F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G290F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G290F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_EMU_BitFields EFM32G290F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G290F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G290F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_CMU_BitFields EFM32G290F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G290F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G290F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_GPIO_BitFields EFM32G290F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G290F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G290F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F32_TIMER_BitFields EFM32G290F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G290F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G290F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G290F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G290F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G290F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -92,8 +92,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_Core EFM32G290F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -118,34 +118,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G290F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G290F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -218,14 +218,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_Peripheral_TypeDefs EFM32G290F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_MSC EFM32G290F64 MSC
|
||||
* @brief EFM32G290F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_EMU EFM32G290F64 EMU
|
||||
* @brief EFM32G290F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -264,8 +264,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_RMU EFM32G290F64 RMU
|
||||
* @brief EFM32G290F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -276,8 +276,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_CMU EFM32G290F64 CMU
|
||||
* @brief EFM32G290F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -319,8 +319,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_AES EFM32G290F64 AES
|
||||
* @brief EFM32G290F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -346,8 +346,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_EBI EFM32G290F64 EBI
|
||||
* @brief EFM32G290F64_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -377,8 +377,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_GPIO EFM32G290F64 GPIO
|
||||
* @brief EFM32G290F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -409,8 +409,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_PRS EFM32G290F64 PRS
|
||||
* @brief EFM32G290F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -432,8 +432,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_DMA EFM32G290F64 DMA
|
||||
* @brief EFM32G290F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -484,8 +484,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_TIMER EFM32G290F64 TIMER
|
||||
* @brief EFM32G290F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -517,8 +517,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_USART EFM32G290F64 USART
|
||||
* @brief EFM32G290F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -548,8 +548,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_LEUART EFM32G290F64 LEUART
|
||||
* @brief EFM32G290F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -579,8 +579,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_LETIMER EFM32G290F64 LETIMER
|
||||
* @brief EFM32G290F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -606,8 +606,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_PCNT EFM32G290F64 PCNT
|
||||
* @brief EFM32G290F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -629,8 +629,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_I2C EFM32G290F64 I2C
|
||||
* @brief EFM32G290F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -653,8 +653,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_ADC EFM32G290F64 ADC
|
||||
* @brief EFM32G290F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -679,8 +679,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_DAC EFM32G290F64 DAC
|
||||
* @brief EFM32G290F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -701,8 +701,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_ACMP EFM32G290F64 ACMP
|
||||
* @brief EFM32G290F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -718,8 +718,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_VCMP EFM32G290F64 VCMP
|
||||
* @brief EFM32G290F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -734,8 +734,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_RTC EFM32G290F64 RTC
|
||||
* @brief EFM32G290F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -754,8 +754,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_WDOG EFM32G290F64 WDOG
|
||||
* @brief EFM32G290F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G290F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -867,39 +867,39 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G290F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -909,7 +909,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_PRS EFM32G290F64 PRS
|
||||
* @addtogroup EFM32G290F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7125,7 +7125,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11320,31 +11320,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_MSC_BitFields EFM32G290F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G290F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G290F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_EMU_BitFields EFM32G290F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G290F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G290F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_CMU_BitFields EFM32G290F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G290F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G290F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_GPIO_BitFields EFM32G290F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G290F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G290F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G290F64_TIMER_BitFields EFM32G290F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G290F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -11711,254 +11711,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G290F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G290F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11975,7 +11727,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G290F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G840F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_Core EFM32G840F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G840F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G840F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_Peripheral_TypeDefs EFM32G840F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_MSC EFM32G840F128 MSC
|
||||
* @brief EFM32G840F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_EMU EFM32G840F128 EMU
|
||||
* @brief EFM32G840F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_RMU EFM32G840F128 RMU
|
||||
* @brief EFM32G840F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_CMU EFM32G840F128 CMU
|
||||
* @brief EFM32G840F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_AES EFM32G840F128 AES
|
||||
* @brief EFM32G840F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_GPIO EFM32G840F128 GPIO
|
||||
* @brief EFM32G840F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_PRS EFM32G840F128 PRS
|
||||
* @brief EFM32G840F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_DMA EFM32G840F128 DMA
|
||||
* @brief EFM32G840F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_TIMER EFM32G840F128 TIMER
|
||||
* @brief EFM32G840F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_USART EFM32G840F128 USART
|
||||
* @brief EFM32G840F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_LEUART EFM32G840F128 LEUART
|
||||
* @brief EFM32G840F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_LETIMER EFM32G840F128 LETIMER
|
||||
* @brief EFM32G840F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_PCNT EFM32G840F128 PCNT
|
||||
* @brief EFM32G840F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_I2C EFM32G840F128 I2C
|
||||
* @brief EFM32G840F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_ADC EFM32G840F128 ADC
|
||||
* @brief EFM32G840F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_DAC EFM32G840F128 DAC
|
||||
* @brief EFM32G840F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_ACMP EFM32G840F128 ACMP
|
||||
* @brief EFM32G840F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_VCMP EFM32G840F128 VCMP
|
||||
* @brief EFM32G840F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_LCD EFM32G840F128 LCD
|
||||
* @brief EFM32G840F128_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_RTC EFM32G840F128 RTC
|
||||
* @brief EFM32G840F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_WDOG EFM32G840F128 WDOG
|
||||
* @brief EFM32G840F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G840F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_PRS EFM32G840F128 PRS
|
||||
* @addtogroup EFM32G840F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_MSC_BitFields EFM32G840F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G840F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G840F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_EMU_BitFields EFM32G840F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G840F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G840F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_CMU_BitFields EFM32G840F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G840F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G840F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_GPIO_BitFields EFM32G840F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G840F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G840F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F128_TIMER_BitFields EFM32G840F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G840F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G840F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G840F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G840F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G840F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_Core EFM32G840F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G840F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G840F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_Peripheral_TypeDefs EFM32G840F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_MSC EFM32G840F32 MSC
|
||||
* @brief EFM32G840F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_EMU EFM32G840F32 EMU
|
||||
* @brief EFM32G840F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_RMU EFM32G840F32 RMU
|
||||
* @brief EFM32G840F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_CMU EFM32G840F32 CMU
|
||||
* @brief EFM32G840F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_AES EFM32G840F32 AES
|
||||
* @brief EFM32G840F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_GPIO EFM32G840F32 GPIO
|
||||
* @brief EFM32G840F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_PRS EFM32G840F32 PRS
|
||||
* @brief EFM32G840F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_DMA EFM32G840F32 DMA
|
||||
* @brief EFM32G840F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_TIMER EFM32G840F32 TIMER
|
||||
* @brief EFM32G840F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_USART EFM32G840F32 USART
|
||||
* @brief EFM32G840F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_LEUART EFM32G840F32 LEUART
|
||||
* @brief EFM32G840F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_LETIMER EFM32G840F32 LETIMER
|
||||
* @brief EFM32G840F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_PCNT EFM32G840F32 PCNT
|
||||
* @brief EFM32G840F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_I2C EFM32G840F32 I2C
|
||||
* @brief EFM32G840F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_ADC EFM32G840F32 ADC
|
||||
* @brief EFM32G840F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_DAC EFM32G840F32 DAC
|
||||
* @brief EFM32G840F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_ACMP EFM32G840F32 ACMP
|
||||
* @brief EFM32G840F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_VCMP EFM32G840F32 VCMP
|
||||
* @brief EFM32G840F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_LCD EFM32G840F32 LCD
|
||||
* @brief EFM32G840F32_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_RTC EFM32G840F32 RTC
|
||||
* @brief EFM32G840F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_WDOG EFM32G840F32 WDOG
|
||||
* @brief EFM32G840F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G840F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_PRS EFM32G840F32 PRS
|
||||
* @addtogroup EFM32G840F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_MSC_BitFields EFM32G840F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G840F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G840F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_EMU_BitFields EFM32G840F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G840F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G840F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_CMU_BitFields EFM32G840F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G840F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G840F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_GPIO_BitFields EFM32G840F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G840F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G840F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F32_TIMER_BitFields EFM32G840F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G840F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G840F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G840F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G840F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G840F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_Core EFM32G840F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G840F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G840F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_Peripheral_TypeDefs EFM32G840F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_MSC EFM32G840F64 MSC
|
||||
* @brief EFM32G840F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_EMU EFM32G840F64 EMU
|
||||
* @brief EFM32G840F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_RMU EFM32G840F64 RMU
|
||||
* @brief EFM32G840F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_CMU EFM32G840F64 CMU
|
||||
* @brief EFM32G840F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_AES EFM32G840F64 AES
|
||||
* @brief EFM32G840F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_GPIO EFM32G840F64 GPIO
|
||||
* @brief EFM32G840F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_PRS EFM32G840F64 PRS
|
||||
* @brief EFM32G840F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_DMA EFM32G840F64 DMA
|
||||
* @brief EFM32G840F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_TIMER EFM32G840F64 TIMER
|
||||
* @brief EFM32G840F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_USART EFM32G840F64 USART
|
||||
* @brief EFM32G840F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_LEUART EFM32G840F64 LEUART
|
||||
* @brief EFM32G840F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_LETIMER EFM32G840F64 LETIMER
|
||||
* @brief EFM32G840F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_PCNT EFM32G840F64 PCNT
|
||||
* @brief EFM32G840F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_I2C EFM32G840F64 I2C
|
||||
* @brief EFM32G840F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_ADC EFM32G840F64 ADC
|
||||
* @brief EFM32G840F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_DAC EFM32G840F64 DAC
|
||||
* @brief EFM32G840F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_ACMP EFM32G840F64 ACMP
|
||||
* @brief EFM32G840F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_VCMP EFM32G840F64 VCMP
|
||||
* @brief EFM32G840F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_LCD EFM32G840F64 LCD
|
||||
* @brief EFM32G840F64_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_RTC EFM32G840F64 RTC
|
||||
* @brief EFM32G840F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_WDOG EFM32G840F64 WDOG
|
||||
* @brief EFM32G840F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G840F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G840F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_PRS EFM32G840F64 PRS
|
||||
* @addtogroup EFM32G840F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_MSC_BitFields EFM32G840F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G840F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G840F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_EMU_BitFields EFM32G840F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G840F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G840F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_CMU_BitFields EFM32G840F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G840F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G840F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_GPIO_BitFields EFM32G840F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G840F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G840F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G840F64_TIMER_BitFields EFM32G840F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G840F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G840F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G840F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G840F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G842F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_Core EFM32G842F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G842F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G842F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_Peripheral_TypeDefs EFM32G842F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_MSC EFM32G842F128 MSC
|
||||
* @brief EFM32G842F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_EMU EFM32G842F128 EMU
|
||||
* @brief EFM32G842F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_RMU EFM32G842F128 RMU
|
||||
* @brief EFM32G842F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_CMU EFM32G842F128 CMU
|
||||
* @brief EFM32G842F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_AES EFM32G842F128 AES
|
||||
* @brief EFM32G842F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_GPIO EFM32G842F128 GPIO
|
||||
* @brief EFM32G842F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_PRS EFM32G842F128 PRS
|
||||
* @brief EFM32G842F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_DMA EFM32G842F128 DMA
|
||||
* @brief EFM32G842F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_TIMER EFM32G842F128 TIMER
|
||||
* @brief EFM32G842F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_USART EFM32G842F128 USART
|
||||
* @brief EFM32G842F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_LEUART EFM32G842F128 LEUART
|
||||
* @brief EFM32G842F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_LETIMER EFM32G842F128 LETIMER
|
||||
* @brief EFM32G842F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_PCNT EFM32G842F128 PCNT
|
||||
* @brief EFM32G842F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_I2C EFM32G842F128 I2C
|
||||
* @brief EFM32G842F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_ADC EFM32G842F128 ADC
|
||||
* @brief EFM32G842F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_DAC EFM32G842F128 DAC
|
||||
* @brief EFM32G842F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_ACMP EFM32G842F128 ACMP
|
||||
* @brief EFM32G842F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_VCMP EFM32G842F128 VCMP
|
||||
* @brief EFM32G842F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_LCD EFM32G842F128 LCD
|
||||
* @brief EFM32G842F128_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_RTC EFM32G842F128 RTC
|
||||
* @brief EFM32G842F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_WDOG EFM32G842F128 WDOG
|
||||
* @brief EFM32G842F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G842F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_PRS EFM32G842F128 PRS
|
||||
* @addtogroup EFM32G842F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_MSC_BitFields EFM32G842F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G842F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G842F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_EMU_BitFields EFM32G842F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G842F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G842F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_CMU_BitFields EFM32G842F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G842F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G842F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_GPIO_BitFields EFM32G842F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G842F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G842F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F128_TIMER_BitFields EFM32G842F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G842F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G842F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G842F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G842F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G842F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_Core EFM32G842F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G842F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G842F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_Peripheral_TypeDefs EFM32G842F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_MSC EFM32G842F32 MSC
|
||||
* @brief EFM32G842F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_EMU EFM32G842F32 EMU
|
||||
* @brief EFM32G842F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_RMU EFM32G842F32 RMU
|
||||
* @brief EFM32G842F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_CMU EFM32G842F32 CMU
|
||||
* @brief EFM32G842F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_AES EFM32G842F32 AES
|
||||
* @brief EFM32G842F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_GPIO EFM32G842F32 GPIO
|
||||
* @brief EFM32G842F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_PRS EFM32G842F32 PRS
|
||||
* @brief EFM32G842F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_DMA EFM32G842F32 DMA
|
||||
* @brief EFM32G842F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_TIMER EFM32G842F32 TIMER
|
||||
* @brief EFM32G842F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_USART EFM32G842F32 USART
|
||||
* @brief EFM32G842F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_LEUART EFM32G842F32 LEUART
|
||||
* @brief EFM32G842F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_LETIMER EFM32G842F32 LETIMER
|
||||
* @brief EFM32G842F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_PCNT EFM32G842F32 PCNT
|
||||
* @brief EFM32G842F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_I2C EFM32G842F32 I2C
|
||||
* @brief EFM32G842F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_ADC EFM32G842F32 ADC
|
||||
* @brief EFM32G842F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_DAC EFM32G842F32 DAC
|
||||
* @brief EFM32G842F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_ACMP EFM32G842F32 ACMP
|
||||
* @brief EFM32G842F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_VCMP EFM32G842F32 VCMP
|
||||
* @brief EFM32G842F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_LCD EFM32G842F32 LCD
|
||||
* @brief EFM32G842F32_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_RTC EFM32G842F32 RTC
|
||||
* @brief EFM32G842F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_WDOG EFM32G842F32 WDOG
|
||||
* @brief EFM32G842F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G842F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_PRS EFM32G842F32 PRS
|
||||
* @addtogroup EFM32G842F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_MSC_BitFields EFM32G842F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G842F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G842F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_EMU_BitFields EFM32G842F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G842F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G842F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_CMU_BitFields EFM32G842F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G842F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G842F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_GPIO_BitFields EFM32G842F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G842F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G842F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F32_TIMER_BitFields EFM32G842F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G842F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G842F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G842F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G842F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G842F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -91,8 +91,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_Core EFM32G842F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -117,34 +117,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G842F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G842F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -215,14 +215,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_Peripheral_TypeDefs EFM32G842F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_MSC EFM32G842F64 MSC
|
||||
* @brief EFM32G842F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -246,8 +246,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_EMU EFM32G842F64 EMU
|
||||
* @brief EFM32G842F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -261,8 +261,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_RMU EFM32G842F64 RMU
|
||||
* @brief EFM32G842F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -273,8 +273,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_CMU EFM32G842F64 CMU
|
||||
* @brief EFM32G842F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -315,8 +315,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_AES EFM32G842F64 AES
|
||||
* @brief EFM32G842F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -358,8 +358,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_GPIO EFM32G842F64 GPIO
|
||||
* @brief EFM32G842F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -390,8 +390,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_PRS EFM32G842F64 PRS
|
||||
* @brief EFM32G842F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -413,8 +413,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_DMA EFM32G842F64 DMA
|
||||
* @brief EFM32G842F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -465,8 +465,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_TIMER EFM32G842F64 TIMER
|
||||
* @brief EFM32G842F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -498,8 +498,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_USART EFM32G842F64 USART
|
||||
* @brief EFM32G842F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -529,8 +529,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_LEUART EFM32G842F64 LEUART
|
||||
* @brief EFM32G842F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -560,8 +560,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_LETIMER EFM32G842F64 LETIMER
|
||||
* @brief EFM32G842F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -587,8 +587,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_PCNT EFM32G842F64 PCNT
|
||||
* @brief EFM32G842F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -610,8 +610,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_I2C EFM32G842F64 I2C
|
||||
* @brief EFM32G842F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -634,8 +634,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_ADC EFM32G842F64 ADC
|
||||
* @brief EFM32G842F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -660,8 +660,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_DAC EFM32G842F64 DAC
|
||||
* @brief EFM32G842F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -682,8 +682,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_ACMP EFM32G842F64 ACMP
|
||||
* @brief EFM32G842F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -699,8 +699,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_VCMP EFM32G842F64 VCMP
|
||||
* @brief EFM32G842F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -715,8 +715,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_LCD EFM32G842F64 LCD
|
||||
* @brief EFM32G842F64_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -748,8 +748,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_RTC EFM32G842F64 RTC
|
||||
* @brief EFM32G842F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -768,8 +768,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_WDOG EFM32G842F64 WDOG
|
||||
* @brief EFM32G842F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G842F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -880,38 +880,38 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G842F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -921,7 +921,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_PRS EFM32G842F64 PRS
|
||||
* @addtogroup EFM32G842F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -6179,7 +6179,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -10605,31 +10605,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_MSC_BitFields EFM32G842F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G842F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G842F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_EMU_BitFields EFM32G842F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G842F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G842F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_CMU_BitFields EFM32G842F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G842F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G842F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_GPIO_BitFields EFM32G842F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G842F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G842F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G842F64_TIMER_BitFields EFM32G842F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G842F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -10996,254 +10996,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G842F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G842F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -11260,7 +11012,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G842F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Core EFM32G880F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G880F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Peripheral_TypeDefs EFM32G880F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_MSC EFM32G880F128 MSC
|
||||
* @brief EFM32G880F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_EMU EFM32G880F128 EMU
|
||||
* @brief EFM32G880F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_RMU EFM32G880F128 RMU
|
||||
* @brief EFM32G880F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_CMU EFM32G880F128 CMU
|
||||
* @brief EFM32G880F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_AES EFM32G880F128 AES
|
||||
* @brief EFM32G880F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_EBI EFM32G880F128 EBI
|
||||
* @brief EFM32G880F128_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_GPIO EFM32G880F128 GPIO
|
||||
* @brief EFM32G880F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_PRS EFM32G880F128 PRS
|
||||
* @brief EFM32G880F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_DMA EFM32G880F128 DMA
|
||||
* @brief EFM32G880F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_TIMER EFM32G880F128 TIMER
|
||||
* @brief EFM32G880F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_USART EFM32G880F128 USART
|
||||
* @brief EFM32G880F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_LEUART EFM32G880F128 LEUART
|
||||
* @brief EFM32G880F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_LETIMER EFM32G880F128 LETIMER
|
||||
* @brief EFM32G880F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_PCNT EFM32G880F128 PCNT
|
||||
* @brief EFM32G880F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_I2C EFM32G880F128 I2C
|
||||
* @brief EFM32G880F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_ADC EFM32G880F128 ADC
|
||||
* @brief EFM32G880F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_DAC EFM32G880F128 DAC
|
||||
* @brief EFM32G880F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_ACMP EFM32G880F128 ACMP
|
||||
* @brief EFM32G880F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_VCMP EFM32G880F128 VCMP
|
||||
* @brief EFM32G880F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_LCD EFM32G880F128 LCD
|
||||
* @brief EFM32G880F128_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_RTC EFM32G880F128 RTC
|
||||
* @brief EFM32G880F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_WDOG EFM32G880F128 WDOG
|
||||
* @brief EFM32G880F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_PRS EFM32G880F128 PRS
|
||||
* @addtogroup EFM32G880F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_MSC_BitFields EFM32G880F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G880F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G880F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_EMU_BitFields EFM32G880F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G880F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G880F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_CMU_BitFields EFM32G880F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G880F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G880F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_GPIO_BitFields EFM32G880F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G880F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G880F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_TIMER_BitFields EFM32G880F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G880F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G880F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G880F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Core EFM32G880F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G880F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Peripheral_TypeDefs EFM32G880F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_MSC EFM32G880F32 MSC
|
||||
* @brief EFM32G880F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_EMU EFM32G880F32 EMU
|
||||
* @brief EFM32G880F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_RMU EFM32G880F32 RMU
|
||||
* @brief EFM32G880F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_CMU EFM32G880F32 CMU
|
||||
* @brief EFM32G880F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_AES EFM32G880F32 AES
|
||||
* @brief EFM32G880F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_EBI EFM32G880F32 EBI
|
||||
* @brief EFM32G880F32_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_GPIO EFM32G880F32 GPIO
|
||||
* @brief EFM32G880F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_PRS EFM32G880F32 PRS
|
||||
* @brief EFM32G880F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_DMA EFM32G880F32 DMA
|
||||
* @brief EFM32G880F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_TIMER EFM32G880F32 TIMER
|
||||
* @brief EFM32G880F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_USART EFM32G880F32 USART
|
||||
* @brief EFM32G880F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_LEUART EFM32G880F32 LEUART
|
||||
* @brief EFM32G880F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_LETIMER EFM32G880F32 LETIMER
|
||||
* @brief EFM32G880F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_PCNT EFM32G880F32 PCNT
|
||||
* @brief EFM32G880F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_I2C EFM32G880F32 I2C
|
||||
* @brief EFM32G880F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_ADC EFM32G880F32 ADC
|
||||
* @brief EFM32G880F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_DAC EFM32G880F32 DAC
|
||||
* @brief EFM32G880F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_ACMP EFM32G880F32 ACMP
|
||||
* @brief EFM32G880F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_VCMP EFM32G880F32 VCMP
|
||||
* @brief EFM32G880F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_LCD EFM32G880F32 LCD
|
||||
* @brief EFM32G880F32_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_RTC EFM32G880F32 RTC
|
||||
* @brief EFM32G880F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_WDOG EFM32G880F32 WDOG
|
||||
* @brief EFM32G880F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_PRS EFM32G880F32 PRS
|
||||
* @addtogroup EFM32G880F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_MSC_BitFields EFM32G880F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G880F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G880F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_EMU_BitFields EFM32G880F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G880F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G880F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_CMU_BitFields EFM32G880F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G880F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G880F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_GPIO_BitFields EFM32G880F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G880F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G880F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_TIMER_BitFields EFM32G880F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G880F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G880F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G880F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Core EFM32G880F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G880F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Peripheral_TypeDefs EFM32G880F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_MSC EFM32G880F64 MSC
|
||||
* @brief EFM32G880F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_EMU EFM32G880F64 EMU
|
||||
* @brief EFM32G880F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_RMU EFM32G880F64 RMU
|
||||
* @brief EFM32G880F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_CMU EFM32G880F64 CMU
|
||||
* @brief EFM32G880F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_AES EFM32G880F64 AES
|
||||
* @brief EFM32G880F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_EBI EFM32G880F64 EBI
|
||||
* @brief EFM32G880F64_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_GPIO EFM32G880F64 GPIO
|
||||
* @brief EFM32G880F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_PRS EFM32G880F64 PRS
|
||||
* @brief EFM32G880F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_DMA EFM32G880F64 DMA
|
||||
* @brief EFM32G880F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_TIMER EFM32G880F64 TIMER
|
||||
* @brief EFM32G880F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_USART EFM32G880F64 USART
|
||||
* @brief EFM32G880F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_LEUART EFM32G880F64 LEUART
|
||||
* @brief EFM32G880F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_LETIMER EFM32G880F64 LETIMER
|
||||
* @brief EFM32G880F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_PCNT EFM32G880F64 PCNT
|
||||
* @brief EFM32G880F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_I2C EFM32G880F64 I2C
|
||||
* @brief EFM32G880F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_ADC EFM32G880F64 ADC
|
||||
* @brief EFM32G880F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_DAC EFM32G880F64 DAC
|
||||
* @brief EFM32G880F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_ACMP EFM32G880F64 ACMP
|
||||
* @brief EFM32G880F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_VCMP EFM32G880F64 VCMP
|
||||
* @brief EFM32G880F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_LCD EFM32G880F64 LCD
|
||||
* @brief EFM32G880F64_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_RTC EFM32G880F64 RTC
|
||||
* @brief EFM32G880F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_WDOG EFM32G880F64 WDOG
|
||||
* @brief EFM32G880F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G880F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_PRS EFM32G880F64 PRS
|
||||
* @addtogroup EFM32G880F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_MSC_BitFields EFM32G880F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G880F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G880F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_EMU_BitFields EFM32G880F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G880F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G880F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_CMU_BitFields EFM32G880F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G880F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G880F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_GPIO_BitFields EFM32G880F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G880F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G880F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_TIMER_BitFields EFM32G880F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G880F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G880F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G880F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F64 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F128
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Core EFM32G890F128 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G890F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Peripheral_TypeDefs EFM32G890F128 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_MSC EFM32G890F128 MSC
|
||||
* @brief EFM32G890F128_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_EMU EFM32G890F128 EMU
|
||||
* @brief EFM32G890F128_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_RMU EFM32G890F128 RMU
|
||||
* @brief EFM32G890F128_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_CMU EFM32G890F128 CMU
|
||||
* @brief EFM32G890F128_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_AES EFM32G890F128 AES
|
||||
* @brief EFM32G890F128_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_EBI EFM32G890F128 EBI
|
||||
* @brief EFM32G890F128_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_GPIO EFM32G890F128 GPIO
|
||||
* @brief EFM32G890F128_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_PRS EFM32G890F128 PRS
|
||||
* @brief EFM32G890F128_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_DMA EFM32G890F128 DMA
|
||||
* @brief EFM32G890F128_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_TIMER EFM32G890F128 TIMER
|
||||
* @brief EFM32G890F128_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_USART EFM32G890F128 USART
|
||||
* @brief EFM32G890F128_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_LEUART EFM32G890F128 LEUART
|
||||
* @brief EFM32G890F128_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_LETIMER EFM32G890F128 LETIMER
|
||||
* @brief EFM32G890F128_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_PCNT EFM32G890F128 PCNT
|
||||
* @brief EFM32G890F128_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_I2C EFM32G890F128 I2C
|
||||
* @brief EFM32G890F128_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_ADC EFM32G890F128 ADC
|
||||
* @brief EFM32G890F128_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_DAC EFM32G890F128 DAC
|
||||
* @brief EFM32G890F128_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_ACMP EFM32G890F128 ACMP
|
||||
* @brief EFM32G890F128_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_VCMP EFM32G890F128 VCMP
|
||||
* @brief EFM32G890F128_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_LCD EFM32G890F128 LCD
|
||||
* @brief EFM32G890F128_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_RTC EFM32G890F128 RTC
|
||||
* @brief EFM32G890F128_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_WDOG EFM32G890F128 WDOG
|
||||
* @brief EFM32G890F128_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F128_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F128_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_PRS EFM32G890F128 PRS
|
||||
* @addtogroup EFM32G890F128_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_MSC_BitFields EFM32G890F128_MSC Bit Fields
|
||||
* @addtogroup EFM32G890F128_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G890F128_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_EMU_BitFields EFM32G890F128_EMU Bit Fields
|
||||
* @addtogroup EFM32G890F128_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G890F128_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_CMU_BitFields EFM32G890F128_CMU Bit Fields
|
||||
* @addtogroup EFM32G890F128_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G890F128_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_GPIO_BitFields EFM32G890F128_GPIO Bit Fields
|
||||
* @addtogroup EFM32G890F128_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G890F128_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_TIMER_BitFields EFM32G890F128_TIMER Bit Fields
|
||||
* @addtogroup EFM32G890F128_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G890F128_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G890F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F128 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F32
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Core EFM32G890F32 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G890F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Peripheral_TypeDefs EFM32G890F32 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_MSC EFM32G890F32 MSC
|
||||
* @brief EFM32G890F32_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_EMU EFM32G890F32 EMU
|
||||
* @brief EFM32G890F32_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_RMU EFM32G890F32 RMU
|
||||
* @brief EFM32G890F32_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_CMU EFM32G890F32 CMU
|
||||
* @brief EFM32G890F32_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_AES EFM32G890F32 AES
|
||||
* @brief EFM32G890F32_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_EBI EFM32G890F32 EBI
|
||||
* @brief EFM32G890F32_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_GPIO EFM32G890F32 GPIO
|
||||
* @brief EFM32G890F32_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_PRS EFM32G890F32 PRS
|
||||
* @brief EFM32G890F32_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_DMA EFM32G890F32 DMA
|
||||
* @brief EFM32G890F32_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_TIMER EFM32G890F32 TIMER
|
||||
* @brief EFM32G890F32_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_USART EFM32G890F32 USART
|
||||
* @brief EFM32G890F32_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_LEUART EFM32G890F32 LEUART
|
||||
* @brief EFM32G890F32_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_LETIMER EFM32G890F32 LETIMER
|
||||
* @brief EFM32G890F32_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_PCNT EFM32G890F32 PCNT
|
||||
* @brief EFM32G890F32_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_I2C EFM32G890F32 I2C
|
||||
* @brief EFM32G890F32_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_ADC EFM32G890F32 ADC
|
||||
* @brief EFM32G890F32_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_DAC EFM32G890F32 DAC
|
||||
* @brief EFM32G890F32_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_ACMP EFM32G890F32 ACMP
|
||||
* @brief EFM32G890F32_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_VCMP EFM32G890F32 VCMP
|
||||
* @brief EFM32G890F32_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_LCD EFM32G890F32 LCD
|
||||
* @brief EFM32G890F32_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_RTC EFM32G890F32 RTC
|
||||
* @brief EFM32G890F32_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_WDOG EFM32G890F32 WDOG
|
||||
* @brief EFM32G890F32_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F32_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F32_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_PRS EFM32G890F32 PRS
|
||||
* @addtogroup EFM32G890F32_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_MSC_BitFields EFM32G890F32_MSC Bit Fields
|
||||
* @addtogroup EFM32G890F32_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G890F32_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_EMU_BitFields EFM32G890F32_EMU Bit Fields
|
||||
* @addtogroup EFM32G890F32_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G890F32_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_CMU_BitFields EFM32G890F32_CMU Bit Fields
|
||||
* @addtogroup EFM32G890F32_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G890F32_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_GPIO_BitFields EFM32G890F32_GPIO Bit Fields
|
||||
* @addtogroup EFM32G890F32_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G890F32_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_TIMER_BitFields EFM32G890F32_TIMER Bit Fields
|
||||
* @addtogroup EFM32G890F32_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G890F32_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G890F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F32 */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F64
|
||||
* @author Energy Micro AS
|
||||
* @version 2.0.0
|
||||
* @version 2.2.2
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2011 Energy Micro AS, http://www.energymicro.com</b>
|
||||
|
|
@ -93,8 +93,8 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Core EFM32G890F64 Core
|
||||
* @brief Processor and Core Peripheral Section
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
|
|
@ -119,34 +119,34 @@ typedef enum IRQn
|
|||
#define PART_NUMBER "EFM32G890F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t)0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t)0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t)0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t)0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t)0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t)0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t)0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t)0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t)0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t)0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t)0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t)0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t)0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t)0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t)0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t)0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t)0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t)0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t)0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t)0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t)0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t)0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t)0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t)0x28UL) /**< FLASH used bits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t)0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t)0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
|
|
@ -221,14 +221,14 @@ typedef enum IRQn
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Peripheral_TypeDefs EFM32G890F64 Peripheral TypeDefs
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_MSC EFM32G890F64 MSC
|
||||
* @brief EFM32G890F64_MSC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -252,8 +252,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_EMU EFM32G890F64 EMU
|
||||
* @brief EFM32G890F64_EMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -267,8 +267,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_RMU EFM32G890F64 RMU
|
||||
* @brief EFM32G890F64_RMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -279,8 +279,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_CMU EFM32G890F64 CMU
|
||||
* @brief EFM32G890F64_CMU Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_CMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -321,8 +321,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_AES EFM32G890F64 AES
|
||||
* @brief EFM32G890F64_AES Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -348,8 +348,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_EBI EFM32G890F64 EBI
|
||||
* @brief EFM32G890F64_EBI Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -379,8 +379,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_GPIO EFM32G890F64 GPIO
|
||||
* @brief EFM32G890F64_GPIO Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_GPIO Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -411,8 +411,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_PRS EFM32G890F64 PRS
|
||||
* @brief EFM32G890F64_PRS Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -434,8 +434,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_DMA EFM32G890F64 DMA
|
||||
* @brief EFM32G890F64_DMA Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_DMA Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -486,8 +486,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_TIMER EFM32G890F64 TIMER
|
||||
* @brief EFM32G890F64_TIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -519,8 +519,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_USART EFM32G890F64 USART
|
||||
* @brief EFM32G890F64_USART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_USART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -550,8 +550,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_LEUART EFM32G890F64 LEUART
|
||||
* @brief EFM32G890F64_LEUART Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -581,8 +581,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_LETIMER EFM32G890F64 LETIMER
|
||||
* @brief EFM32G890F64_LETIMER Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -608,8 +608,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_PCNT EFM32G890F64 PCNT
|
||||
* @brief EFM32G890F64_PCNT Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -631,8 +631,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_I2C EFM32G890F64 I2C
|
||||
* @brief EFM32G890F64_I2C Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -655,8 +655,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_ADC EFM32G890F64 ADC
|
||||
* @brief EFM32G890F64_ADC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -681,8 +681,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_DAC EFM32G890F64 DAC
|
||||
* @brief EFM32G890F64_DAC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -703,8 +703,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_ACMP EFM32G890F64 ACMP
|
||||
* @brief EFM32G890F64_ACMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -720,8 +720,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_VCMP EFM32G890F64 VCMP
|
||||
* @brief EFM32G890F64_VCMP Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -736,8 +736,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_LCD EFM32G890F64 LCD
|
||||
* @brief EFM32G890F64_LCD Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -769,8 +769,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_RTC EFM32G890F64 RTC
|
||||
* @brief EFM32G890F64_RTC Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -789,8 +789,8 @@ typedef struct
|
|||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_WDOG EFM32G890F64 WDOG
|
||||
* @brief EFM32G890F64_WDOG Register Declaration
|
||||
* @{
|
||||
* @brief EFM32G890F64_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -903,40 +903,40 @@ typedef struct
|
|||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *)MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *)EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *)RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *)CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *)AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *)EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *)GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *)PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *)DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *)TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *)USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *)USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *)USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *)UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *)LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *)LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *)LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *)PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *)PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *)PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *)I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *)ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *)DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *)VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *)LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *)RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *)WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *)CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *)DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *)ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F64_Peripheral_Declaration */
|
||||
|
||||
|
|
@ -946,7 +946,7 @@ typedef struct
|
|||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_PRS EFM32G890F64 PRS
|
||||
* @addtogroup EFM32G890F64_PRS
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
|
@ -7162,7 +7162,7 @@ typedef struct
|
|||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x000001BFUL /**< Mask for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
|
|
@ -11794,31 +11794,31 @@ typedef struct
|
|||
* Unlock codes
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_MSC_BitFields EFM32G890F64_MSC Bit Fields
|
||||
* @addtogroup EFM32G890F64_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
/** @} End of group EFM32G890F64_MSC */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_EMU_BitFields EFM32G890F64_EMU Bit Fields
|
||||
* @addtogroup EFM32G890F64_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
/** @} End of group EFM32G890F64_EMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_CMU_BitFields EFM32G890F64_CMU Bit Fields
|
||||
* @addtogroup EFM32G890F64_CMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
/** @} End of group EFM32G890F64_CMU */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_GPIO_BitFields EFM32G890F64_GPIO Bit Fields
|
||||
* @addtogroup EFM32G890F64_GPIO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
/** @} End of group EFM32G890F64_GPIO */
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_TIMER_BitFields EFM32G890F64_TIMER Bit Fields
|
||||
* @addtogroup EFM32G890F64_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
|
@ -12185,254 +12185,6 @@ typedef struct
|
|||
|
||||
/** @} End of group EFM32G890F64_AF_Pins */
|
||||
|
||||
/** Grouped by channel c, function f */
|
||||
#define AF_PORT(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PORT((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PORT((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PORT((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PORT((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PORT((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PORT((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PORT((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PORT((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PORT((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PORT((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PORT((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PORT((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PORT((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PORT((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PORT((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PORT((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PORT((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PORT((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PORT((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PORT((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PORT((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PORT((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PORT((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PORT((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PORT((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PORT((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PORT((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PORT((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PORT((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PORT((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PORT((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PORT((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PORT((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PORT((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PORT((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PORT((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PORT((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PORT((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PORT((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PORT((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PORT((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PORT((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PORT((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PORT((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PORT((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PORT((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PORT((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PORT((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PORT((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PORT((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PORT((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PORT((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PORT((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PORT((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PORT((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PORT((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PORT((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PORT((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PORT((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PORT((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PORT((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PORT((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PORT((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PORT((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PORT((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PORT((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PORT((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PORT((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PORT((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PORT((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PORT((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PORT((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PORT((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PORT((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PORT((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PORT((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PORT((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PORT((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PORT((f)) : \
|
||||
-1)
|
||||
|
||||
#define AF_PIN(c, f) ( \
|
||||
(c) == 0 ? AF_CMU_CLK0_PIN((f)) : \
|
||||
(c) == 1 ? AF_CMU_CLK1_PIN((f)) : \
|
||||
(c) == 2 ? AF_EBI_AD00_PIN((f)) : \
|
||||
(c) == 3 ? AF_EBI_AD01_PIN((f)) : \
|
||||
(c) == 4 ? AF_EBI_AD02_PIN((f)) : \
|
||||
(c) == 5 ? AF_EBI_AD03_PIN((f)) : \
|
||||
(c) == 6 ? AF_EBI_AD04_PIN((f)) : \
|
||||
(c) == 7 ? AF_EBI_AD05_PIN((f)) : \
|
||||
(c) == 8 ? AF_EBI_AD06_PIN((f)) : \
|
||||
(c) == 9 ? AF_EBI_AD07_PIN((f)) : \
|
||||
(c) == 10 ? AF_EBI_AD08_PIN((f)) : \
|
||||
(c) == 11 ? AF_EBI_AD09_PIN((f)) : \
|
||||
(c) == 12 ? AF_EBI_AD10_PIN((f)) : \
|
||||
(c) == 13 ? AF_EBI_AD11_PIN((f)) : \
|
||||
(c) == 14 ? AF_EBI_AD12_PIN((f)) : \
|
||||
(c) == 15 ? AF_EBI_AD13_PIN((f)) : \
|
||||
(c) == 16 ? AF_EBI_AD14_PIN((f)) : \
|
||||
(c) == 17 ? AF_EBI_AD15_PIN((f)) : \
|
||||
(c) == 18 ? AF_EBI_CS0_PIN((f)) : \
|
||||
(c) == 19 ? AF_EBI_CS1_PIN((f)) : \
|
||||
(c) == 20 ? AF_EBI_CS2_PIN((f)) : \
|
||||
(c) == 21 ? AF_EBI_CS3_PIN((f)) : \
|
||||
(c) == 22 ? AF_EBI_WEn_PIN((f)) : \
|
||||
(c) == 23 ? AF_EBI_REn_PIN((f)) : \
|
||||
(c) == 24 ? AF_EBI_ARDY_PIN((f)) : \
|
||||
(c) == 25 ? AF_EBI_ALE_PIN((f)) : \
|
||||
(c) == 26 ? AF_TIMER0_CC0_PIN((f)) : \
|
||||
(c) == 27 ? AF_TIMER0_CC1_PIN((f)) : \
|
||||
(c) == 28 ? AF_TIMER0_CC2_PIN((f)) : \
|
||||
(c) == 29 ? AF_TIMER0_CDTI0_PIN((f)) : \
|
||||
(c) == 30 ? AF_TIMER0_CDTI1_PIN((f)) : \
|
||||
(c) == 31 ? AF_TIMER0_CDTI2_PIN((f)) : \
|
||||
(c) == 32 ? AF_TIMER1_CC0_PIN((f)) : \
|
||||
(c) == 33 ? AF_TIMER1_CC1_PIN((f)) : \
|
||||
(c) == 34 ? AF_TIMER1_CC2_PIN((f)) : \
|
||||
(c) == 35 ? AF_TIMER1_CDTI0_PIN((f)) : \
|
||||
(c) == 36 ? AF_TIMER1_CDTI1_PIN((f)) : \
|
||||
(c) == 37 ? AF_TIMER1_CDTI2_PIN((f)) : \
|
||||
(c) == 38 ? AF_TIMER2_CC0_PIN((f)) : \
|
||||
(c) == 39 ? AF_TIMER2_CC1_PIN((f)) : \
|
||||
(c) == 40 ? AF_TIMER2_CC2_PIN((f)) : \
|
||||
(c) == 41 ? AF_TIMER2_CDTI0_PIN((f)) : \
|
||||
(c) == 42 ? AF_TIMER2_CDTI1_PIN((f)) : \
|
||||
(c) == 43 ? AF_TIMER2_CDTI2_PIN((f)) : \
|
||||
(c) == 44 ? AF_USART0_TX_PIN((f)) : \
|
||||
(c) == 45 ? AF_USART0_RX_PIN((f)) : \
|
||||
(c) == 46 ? AF_USART0_CLK_PIN((f)) : \
|
||||
(c) == 47 ? AF_USART0_CS_PIN((f)) : \
|
||||
(c) == 48 ? AF_USART1_TX_PIN((f)) : \
|
||||
(c) == 49 ? AF_USART1_RX_PIN((f)) : \
|
||||
(c) == 50 ? AF_USART1_CLK_PIN((f)) : \
|
||||
(c) == 51 ? AF_USART1_CS_PIN((f)) : \
|
||||
(c) == 52 ? AF_USART2_TX_PIN((f)) : \
|
||||
(c) == 53 ? AF_USART2_RX_PIN((f)) : \
|
||||
(c) == 54 ? AF_USART2_CLK_PIN((f)) : \
|
||||
(c) == 55 ? AF_USART2_CS_PIN((f)) : \
|
||||
(c) == 56 ? AF_UART0_TX_PIN((f)) : \
|
||||
(c) == 57 ? AF_UART0_RX_PIN((f)) : \
|
||||
(c) == 58 ? AF_UART0_CLK_PIN((f)) : \
|
||||
(c) == 59 ? AF_UART0_CS_PIN((f)) : \
|
||||
(c) == 60 ? AF_LEUART0_TX_PIN((f)) : \
|
||||
(c) == 61 ? AF_LEUART0_RX_PIN((f)) : \
|
||||
(c) == 62 ? AF_LEUART1_TX_PIN((f)) : \
|
||||
(c) == 63 ? AF_LEUART1_RX_PIN((f)) : \
|
||||
(c) == 64 ? AF_LETIMER0_OUT0_PIN((f)) : \
|
||||
(c) == 65 ? AF_LETIMER0_OUT1_PIN((f)) : \
|
||||
(c) == 66 ? AF_PCNT0_S0IN_PIN((f)) : \
|
||||
(c) == 67 ? AF_PCNT0_S1IN_PIN((f)) : \
|
||||
(c) == 68 ? AF_PCNT1_S0IN_PIN((f)) : \
|
||||
(c) == 69 ? AF_PCNT1_S1IN_PIN((f)) : \
|
||||
(c) == 70 ? AF_PCNT2_S0IN_PIN((f)) : \
|
||||
(c) == 71 ? AF_PCNT2_S1IN_PIN((f)) : \
|
||||
(c) == 72 ? AF_I2C0_SDA_PIN((f)) : \
|
||||
(c) == 73 ? AF_I2C0_SCL_PIN((f)) : \
|
||||
(c) == 74 ? AF_ACMP0_OUT_PIN((f)) : \
|
||||
(c) == 75 ? AF_ACMP1_OUT_PIN((f)) : \
|
||||
(c) == 76 ? AF_DBG_SWO_PIN((f)) : \
|
||||
(c) == 77 ? AF_DBG_SWDIO_PIN((f)) : \
|
||||
(c) == 78 ? AF_DBG_SWCLK_PIN((f)) : \
|
||||
-1)
|
||||
|
||||
/** AF channel output count for channel c */
|
||||
#define AF_COUNT(c) ( \
|
||||
(c) == 0 ? 2 : \
|
||||
(c) == 1 ? 2 : \
|
||||
(c) == 2 ? 1 : \
|
||||
(c) == 3 ? 1 : \
|
||||
(c) == 4 ? 1 : \
|
||||
(c) == 5 ? 1 : \
|
||||
(c) == 6 ? 1 : \
|
||||
(c) == 7 ? 1 : \
|
||||
(c) == 8 ? 1 : \
|
||||
(c) == 9 ? 1 : \
|
||||
(c) == 10 ? 1 : \
|
||||
(c) == 11 ? 1 : \
|
||||
(c) == 12 ? 1 : \
|
||||
(c) == 13 ? 1 : \
|
||||
(c) == 14 ? 1 : \
|
||||
(c) == 15 ? 1 : \
|
||||
(c) == 16 ? 1 : \
|
||||
(c) == 17 ? 1 : \
|
||||
(c) == 18 ? 1 : \
|
||||
(c) == 19 ? 1 : \
|
||||
(c) == 20 ? 1 : \
|
||||
(c) == 21 ? 1 : \
|
||||
(c) == 22 ? 1 : \
|
||||
(c) == 23 ? 1 : \
|
||||
(c) == 24 ? 1 : \
|
||||
(c) == 25 ? 1 : \
|
||||
(c) == 26 ? 4 : \
|
||||
(c) == 27 ? 4 : \
|
||||
(c) == 28 ? 4 : \
|
||||
(c) == 29 ? 4 : \
|
||||
(c) == 30 ? 4 : \
|
||||
(c) == 31 ? 4 : \
|
||||
(c) == 32 ? 3 : \
|
||||
(c) == 33 ? 3 : \
|
||||
(c) == 34 ? 3 : \
|
||||
(c) == 35 ? 0 : \
|
||||
(c) == 36 ? 0 : \
|
||||
(c) == 37 ? 0 : \
|
||||
(c) == 38 ? 3 : \
|
||||
(c) == 39 ? 3 : \
|
||||
(c) == 40 ? 3 : \
|
||||
(c) == 41 ? 0 : \
|
||||
(c) == 42 ? 0 : \
|
||||
(c) == 43 ? 0 : \
|
||||
(c) == 44 ? 3 : \
|
||||
(c) == 45 ? 3 : \
|
||||
(c) == 46 ? 3 : \
|
||||
(c) == 47 ? 3 : \
|
||||
(c) == 48 ? 2 : \
|
||||
(c) == 49 ? 2 : \
|
||||
(c) == 50 ? 2 : \
|
||||
(c) == 51 ? 2 : \
|
||||
(c) == 52 ? 2 : \
|
||||
(c) == 53 ? 2 : \
|
||||
(c) == 54 ? 2 : \
|
||||
(c) == 55 ? 2 : \
|
||||
(c) == 56 ? 4 : \
|
||||
(c) == 57 ? 4 : \
|
||||
(c) == 58 ? 0 : \
|
||||
(c) == 59 ? 0 : \
|
||||
(c) == 60 ? 3 : \
|
||||
(c) == 61 ? 3 : \
|
||||
(c) == 62 ? 2 : \
|
||||
(c) == 63 ? 2 : \
|
||||
(c) == 64 ? 4 : \
|
||||
(c) == 65 ? 4 : \
|
||||
(c) == 66 ? 3 : \
|
||||
(c) == 67 ? 3 : \
|
||||
(c) == 68 ? 2 : \
|
||||
(c) == 69 ? 2 : \
|
||||
(c) == 70 ? 2 : \
|
||||
(c) == 71 ? 2 : \
|
||||
(c) == 72 ? 4 : \
|
||||
(c) == 73 ? 4 : \
|
||||
(c) == 74 ? 2 : \
|
||||
(c) == 75 ? 2 : \
|
||||
(c) == 76 ? 2 : \
|
||||
(c) == 77 ? 2 : \
|
||||
(c) == 78 ? 2 : \
|
||||
-1)
|
||||
|
||||
/** @} End of group EFM32G890F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
|
|
@ -12449,7 +12201,7 @@ typedef struct
|
|||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG)&~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F64 */
|
||||
|
||||
|
|
|
|||
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Load Diff
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Load Diff
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Load Diff
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Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue