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fix pendsv priority set reverse bug 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1218 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2010-12-20 13:41:56 +00:00
parent d8b4897cac
commit f18a82d59b
5 changed files with 41 additions and 9 deletions
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4
libcpu/arm/lm3s/context_gcc.S
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@ -146,7 +146,9 @@ rt_hw_context_switch_to:
/* set the PendSV exception priority */ /* set the PendSV exception priority */
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
STR r1, [r0] LDR.W R2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-bak
LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET

4
libcpu/arm/lm3s/context_rvds.S
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@ -155,7 +155,9 @@ rt_hw_context_switch_to PROC
; trigger the PendSV exception (causes context switch) ; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL LDR r0, =NVIC_INT_CTRL
LDR r1, =NVIC_PENDSVSET LDR r1, =NVIC_PENDSVSET
STR r1, [r0] LDR.W R2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-bak
; enable interrupts at processor level ; enable interrupts at processor level
CPSIE I CPSIE I

4
libcpu/arm/lpc17xx/context_iar.S
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@ -148,7 +148,9 @@ rt_hw_context_switch_to:
; set the PendSV exception priority ; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
STR r1, [r0] LDR.W R2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-bak
; trigger the PendSV exception (causes context switch) ; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL LDR r0, =NVIC_INT_CTRL

4
libcpu/arm/lpc17xx/context_rvds.S
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@ -150,7 +150,9 @@ rt_hw_context_switch_to PROC
; set the PendSV exception priority ; set the PendSV exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
STR r1, [r0] LDR.W R2, [r0,#0x00] ; read
ORR r1,r1,r2 ; modify
STR r1, [r0] ; write-bak
; trigger the PendSV exception (causes context switch) ; trigger the PendSV exception (causes context switch)
LDR r0, =NVIC_INT_CTRL LDR r0, =NVIC_INT_CTRL

34
libcpu/arm/s3c24x0/start_rvds.S
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@ -498,7 +498,7 @@ GPDAT_OFS EQU 0x04 ; Data Register Offset
GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset
;// <e> I/O Setup ;// <e> I/O Setup
GP_SETUP EQU 0 GP_SETUP EQU 1
;// <e> Port A Settings ;// <e> Port A Settings
;// <h> Port A Control Register (GPACON) ;// <h> Port A Control Register (GPACON)
@ -710,9 +710,9 @@ GPEUP_Val EQU 0x00000000
;// <o2.0> GPF0 Pull-up Disable ;// <o2.0> GPF0 Pull-up Disable
;// </h> ;// </h>
;// </e> ;// </e>
GPF_SETUP EQU 0 GPF_SETUP EQU 1
GPFCON_Val EQU 0x00000000 GPFCON_Val EQU 0x000000AA
GPFUP_Val EQU 0x00000000 GPFUP_Val EQU 0x0000000F
;// <e> Port G Settings ;// <e> Port G Settings
;// <h> Port G Control Register (GPGCON) ;// <h> Port G Control Register (GPGCON)
@ -866,10 +866,34 @@ FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler ;DAbt_Handler B DAbt_Handler
FIQ_Handler B FIQ_Handler FIQ_Handler B FIQ_Handler
;*
;*************************************************************************
;*
;* Interrupt handling
;*
;*************************************************************************
;*
; DAbt Handler
DAbt_Handler
IMPORT rt_hw_trap_dabt
sub sp, sp, #72
stmia sp, {r0 - r12} ;/* Calling r0-r12 */
add r8, sp, #60
stmdb r8, {sp, lr} ;/* Calling SP, LR */
str lr, [r8, #0] ;/* Save calling PC */
mrs r6, spsr
str r6, [r8, #4] ;/* Save CPSR */
str r0, [r8, #8] ;/* Save OLD_R0 */
mov r0, sp
bl rt_hw_trap_dabt
;##########################################
; Reset Handler ; Reset Handler
EXPORT Reset_Handler EXPORT Reset_Handler