[BSP] add i.MX 6UL BSP

bsp/imx6ul/KConfig

@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config BOARD_IMX6UL
+    bool 
+    select ARCH_ARM_CORTEX_A7
+    default y
+
+source "$RTT_DIR/KConfig"
+source "$PKGS_DIR/KConfig"
+
+source "$BSP_DIR/drivers/Kconfig"

bsp/imx6ul/Makefile

@@ -0,0 +1,10 @@
+scons:=python ${SCONS}\scons.py
+
+all:
+	@$(scons)
+
+clean:
+	@$(scons) -c
+
+copy:
+	@$(scons) --copy -s

bsp/imx6ul/README.md

@@ -0,0 +1,17 @@
+# i.MX6 SoloX
+
+Freescale's Smart Application Blueprint for Rapid Engineering (SABRE) board for smart devices
+
+Rev.B
+
+CPU: MCIMX6X4EVM10AB
+
+* ARM Cortex-A9 @ 1GHz
+* ARM Cortex-M4 @ 200MHz
+
+* Freescale PF0200 PMIC
+* 1GB DDR3
+* 32 MB x2 QuadSPI Flash
+
+* Freescale MMA8451 3-Axis Accelerometer
+* Freescale MAG3110 3D Magnetometer

bsp/imx6ul/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imx6ul/SConstruct

@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/imx6ul/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6ul/applications/application.c

@@ -0,0 +1,45 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rtthread.h>
+
+#include <sdk_version.h>
+#include <ccm_pll.h>
+
+void show_freq(void)
+{
+    rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000);
+    rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000);
+    rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000);
+}
+
+void init_thread(void* parameter)
+{
+    rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING);
+    show_freq();
+
+    rt_components_init();
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", init_thread, RT_NULL,
+        1024, RT_THREAD_PRIORITY_MAX/3, 10);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+

bsp/imx6ul/applications/startup.c

@@ -0,0 +1,74 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-05     Bernard      the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int  rt_application_init(void);
+extern void rt_hw_board_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    // platform_init();
+    // print_version();
+
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize timer and soft timer thread */
+    rt_system_timer_init();
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}

bsp/imx6ul/drivers/SConscript

@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src	= Glob('*.c') + Glob('iomux/*.c')
+
+CPPPATH = [cwd, cwd + '/iomux']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6ul/drivers/board.c

@@ -0,0 +1,79 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2016, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include <registers/regsarmglobaltimer.h>
+#include <registers/regsepit.h>
+
+#include <imx_uart.h>
+#include <epit.h>
+#include <cortex_a.h>
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    epit_get_compare_event(HW_EPIT1);
+}
+
+int rt_hw_timer_init(void)
+{
+    uint32_t freq;
+
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTER_HI_WR(0);
+    HW_ARMGLOBALTIMER_COUNTER_LO_WR(0);
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+
+    freq = get_main_clock(IPG_CLK);
+
+    epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000,
+              SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN);
+
+    epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE);
+
+    rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(IMX_INT_EPIT1);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+/**
+ * This function will initialize hardware board
+ */
+void rt_hw_board_init(void)
+{
+    enable_neon_fpu();
+    disable_strict_align_check();
+
+    rt_components_board_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+/*@}*/

bsp/imx6ul/drivers/board.h

@@ -0,0 +1,36 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard    the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <registers.h>
+#include <irq_numbers.h>
+
+#define CONFIG_MX6
+#define CONFIG_MX6UL
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x80000000 + 32 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/imx6ul/drivers/iomux/iomux_config.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+
+// Function to configure iomux for i.MX6SL board MCIMX6SLEVK rev. B.
+void iomux_config(void)
+{
+    uart1_iomux_config();
+}

bsp/imx6ul/drivers/iomux/iomux_config.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: iomux_config.h
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#ifndef _IOMUX_CONFIG_H_
+#define _IOMUX_CONFIG_H_
+
+// Board and Module IOMUXC configuration function prototypes.
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Board IOMUXC configuration function.
+void iomux_config(void);
+
+// Module IOMUXC configuration functions.
+void uart1_iomux_config(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // _IOMUX_CONFIG_H_

bsp/imx6ul/drivers/iomux/uart_iomux_config.c

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: uart_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsuart.h"
+#include "iomux_register.h"
+#include "io.h"
+#include <assert.h>
+
+#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1	(IOMUXC_BASE_ADDR+0x084)
+#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1	(IOMUXC_BASE_ADDR+0x088)
+#define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624)
+
+void uart1_iomux_config(void)
+{
+    /* UART1 TXD */
+    MX6UL_PAD_UART1_TX_DATA__UART1_TX(0x10b0);
+    /* UART1 RXD */
+    MX6UL_PAD_UART1_RX_DATA__UART1_RX(0x10b0);
+}
+
+void uart2_iomux_config(void)
+{
+}
+
+void uart3_iomux_config(void)
+{
+}
+
+void uart4_iomux_config(void)
+{
+}
+
+void uart5_iomux_config(void)
+{
+}
+
+void uart6_iomux_config(void)
+{
+}
+
+void uart7_iomux_config(void)
+{
+}
+
+void uart8_iomux_config(void)
+{
+}
+
+
+void uart_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_UART1:
+            return uart1_iomux_config();
+
+        case HW_UART2:
+            return uart2_iomux_config();
+
+        case HW_UART3:
+            return uart3_iomux_config();
+
+        case HW_UART4:
+            return uart4_iomux_config();
+
+        case HW_UART5:
+            return uart5_iomux_config();
+
+        case HW_UART6:
+            return uart5_iomux_config();
+
+        case HW_UART7:
+            return uart5_iomux_config();       
+
+        case HW_UART8:
+            return uart5_iomux_config(); 
+                             
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6ul/drivers/serial.c

@@ -0,0 +1,202 @@
+/*
+ *  serial.c UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#include <rthw.h>
+#include <registers/regsuart.h>
+#include <imx_uart.h>
+
+#include <rtdevice.h>
+
+#include "serial.h"
+
+struct hw_uart_device
+{
+    uint32_t instance;
+    int irqno;
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t baudrate;
+    uint8_t parity, stopbits, datasize, flowcontrol;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    baudrate = cfg->baud_rate;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        datasize = EIGHTBITS;
+        break;
+    case DATA_BITS_7:
+        datasize = SEVENBITS;
+        break;
+    }
+    if (cfg->stop_bits == STOP_BITS_1) stopbits = STOPBITS_ONE;
+    else if (cfg->stop_bits == STOP_BITS_2) stopbits = STOPBITS_TWO;
+
+    parity = PARITY_NONE;
+    flowcontrol = FLOWCTRL_OFF;
+
+    /* Initialize UART */
+    uart_init(uart->instance, baudrate, parity, stopbits, datasize, flowcontrol);
+
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart");
+    rt_hw_interrupt_mask(uart->irqno);
+
+    /* Set the IRQ mode for the Rx FIFO */
+    uart_set_FIFO_mode(uart->instance, RX_FIFO, 1, IRQ_MODE);
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    uart_putchar(uart->instance, (uint8_t*)&c);
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    ch = uart_getchar(uart->instance);
+    if (ch == NONE_CHAR) ch = -1;
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+#ifdef RT_USING_UART0
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    HW_UART0,
+    IMX_INT_UART0
+};
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+/* UART1 device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    HW_UART1,
+    IMX_INT_UART1
+};
+static struct rt_serial_device _serial1;
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config;
+
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
+
+#ifdef RT_USING_UART0
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif
+
+#ifdef RT_USING_UART1
+    uart = &_uart1_device;
+    _serial1.ops = &_uart_ops;
+    _serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);

bsp/imx6ul/drivers/serial.h

@@ -0,0 +1,39 @@
+/*
+ *  UART driver
+ *
+ * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  This file is part of RT-Thread (http://www.rt-thread.org)
+ *  Maintainer: bernard.xiong <bernard.xiong at gmail.com>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-03-30     Bernard      the first verion
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <board.h>
+
+int rt_hw_uart_init(void);
+
+#endif
+
+

bsp/imx6ul/imx6.lds

@@ -0,0 +1,99 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+SECTIONS
+{
+    . = 0x80100000;
+
+    __text_start = .;
+    .text :
+    {
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    __data_start = .;
+    . = ALIGN(4);
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = __data_end;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}

bsp/imx6ul/platform/SConscript

@@ -0,0 +1,26 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+drivers/epit.c
+drivers/gpt.c
+drivers/imx_timer.c
+drivers/imx_i2c.c
+drivers/imx_uart.c
+cpu/armv7_cache.c
+cpu/gic.c
+cpu/ccm_pll2.c
+cpu/mmu.c
+cpu/cortex_a_gcc.S
+''')
+
+CPPPATH = [ cwd + '/cpu',
+cwd + '/include', 
+cwd + '/include/mx6ul',
+cwd + '/include/mx6ul/registers'
+]
+CPPDEFINES = ['CHIP_MX6UL']
+
+group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/imx6ul/platform/cpu/arm_cp_registers.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup cortexa9
+//! @{
+
+/*!
+ * @file  arm_cp_registers.h
+ * @brief Definitions for ARM coprocessor registers.
+ */
+
+#ifndef __ARM_CP_REGISTERS_H__
+#define __ARM_CP_REGISTERS_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name ACTLR
+//@{
+#define BM_ACTLR_SMP (1 << 6)
+//@}
+
+//! @name DFSR
+//@{
+#define BM_DFSR_WNR (1 << 11)   //!< Write not Read bit. 0=read, 1=write.
+#define BM_DFSR_FS4 (0x400)      //!< Fault status bit 4..
+#define BP_DFSR_FS4 (10)        //!< Bit position for FS[4].
+#define BM_DFSR_FS (0xf)      //!< Fault status bits [3:0].
+//@}
+
+//! @name SCTLR
+//@{
+#define BM_SCTLR_TE (1 << 30)  //!< Thumb exception enable.
+#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable.
+#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable.
+#define BM_SCTLR_NMFI (1 << 27)    //!< Non-maskable FIQ support.
+#define BM_SCTLR_EE (1 << 25)  //!< Exception endianess.
+#define BM_SCTLR_VE (1 << 24)  //!< Interrupt vectors enable.
+#define BM_SCTLR_FI (1 << 21)   //!< Fast interrupt configurable enable.
+#define BM_SCTLR_RR (1 << 14)  //!< Round Robin
+#define BM_SCTLR_V (1 << 13)   //!< Vectors
+#define BM_SCTLR_I (1 << 12)   //!< Instruction cache enable
+#define BM_SCTLR_Z (1 << 11)   //!< Branch prediction enable
+#define BM_SCTLR_SW (1 << 10)  //!< SWP and SWPB enable
+#define BM_SCTLR_CP15BEN (1 << 5)  //!< CP15 barrier enable
+#define BM_SCTLR_C (1 << 2)    //!< Data cache enable
+#define BM_SCTLR_A (1 << 1)    //!< Alignment check enable
+#define BM_SCTLR_M (1 << 0)    //!< MMU enable
+//@}
+
+//! @}
+
+#endif // __ARM_CP_REGISTERS_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/cpu/armv7_cache.c

@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cortex_a.h"
+#include "arm_cp_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Check if dcache is enabled or disabled
+int arm_dcache_state_query()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (sctlr & BM_SCTLR_C)
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+void arm_dcache_enable()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (!(sctlr & BM_SCTLR_C))
+    {
+        // set  C bit (data caching enable) 
+        sctlr |= BM_SCTLR_C;
+        
+        // write modified sctlr
+        _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+        
+        // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+        _ARM_DSB();
+    }
+}
+
+void arm_dcache_disable()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // set  C bit (data caching enable) 
+    sctlr &= ~BM_SCTLR_C;
+
+    // write modified sctlr
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate()
+{
+    uint32_t csid;    // Cache Size ID
+    uint32_t wayset;  // wayset parameter 
+    int num_sets; // number of sets  
+    int num_ways; // number of ways
+
+    _ARM_MRC(15, 1, csid, 0, 0, 0);    // Read Cache Size ID 
+    
+    // Fill number of sets  and number of ways from csid register  This walues are decremented by 1
+    num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT)
+    
+    // Invalidation all lines (all Sets in all ways) 
+    while (num_ways >= 0)
+    {
+        num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK) >> csid_NUMSETS_SHIFT)
+        while (num_sets >= 0 )
+        {
+            wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_sets << 3SETWAY_WAY_SHIFT)
+            // invalidate line if we know set and way 
+            _ARM_MCR(15, 0, wayset, 7, 6, 2);
+            num_sets--;
+        }
+        num_ways--;
+    }
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+
+    // Invalidate data cache line by va to PoC (Point of Coherency). 
+    _ARM_MCR(15, 0, va, 7, 6, 1);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_invalidate_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);
+
+    // align the address with line
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+            
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 6, 1);
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush()
+{
+    uint32_t csid;    // Cache Size ID
+    uint32_t wayset;  // wayset parameter 
+    int num_sets; // number of sets  
+    int num_ways; // number of ways
+
+    _ARM_MRC(15, 1, csid, 0, 0, 0);    // Read Cache Size ID 
+    
+    // Fill number of sets  and number of ways from csid register  This walues are decremented by 1
+    num_ways = (csid >> 0x03) & 0x3FFu; //((csid& csid_ASSOCIATIVITY_MASK) >> csid_ASSOCIATIVITY_SHIFT`)
+    while (num_ways >= 0)
+    {
+        num_sets = (csid >> 0x0D) & 0x7FFFu; //((csid & csid_NUMSETS_MASK)      >> csid_NUMSETS_SHIFT       )
+        while (num_sets >= 0 )
+        {
+            wayset = (num_sets << 5u) | (num_ways << 30u); //(num_sets << SETWAY_SET_SHIFT) | (num_ways << 3SETWAY_WAY_SHIFT)
+            // FLUSH (clean) line if we know set and way 
+            _ARM_MCR(15, 0, wayset, 7, 10, 2);
+            num_sets--;
+        }
+        num_ways--;
+    }
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+    
+    // Clean data cache line to PoC (Point of Coherence) by va. 
+    _ARM_MCR(15, 0, va, 7, 10, 1);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+void arm_dcache_flush_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);
+    
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size  - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 10, 1);
+        
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete
+    _ARM_DSB();
+}
+
+int arm_icache_state_query()
+{
+    uint32_t sctlr; // System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+        
+    if (sctlr & BM_SCTLR_I)
+    {
+        return 1;
+    }
+
+    return 0;
+}
+
+void arm_icache_enable()
+{
+    uint32_t sctlr  ;// System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // ignore the operation if I is enabled already
+    if(!(sctlr & BM_SCTLR_I))
+    {	
+        // set  I bit (instruction caching enable)
+        sctlr |= BM_SCTLR_I;
+        
+        // write modified sctlr
+        _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+        
+        // synchronize context on this processor 
+        _ARM_ISB();
+    }
+}
+
+void arm_icache_disable()
+{
+    uint32_t sctlr  ;// System Control Register 
+    
+    // read sctlr 
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // Clear  I bit (instruction caching enable) 
+    sctlr &= ~BM_SCTLR_I;
+
+    // write modified sctlr
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate()
+{
+    uint32_t SBZ = 0x0u;
+    
+    _ARM_MCR(15, 0, SBZ, 7, 5, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_is()
+{
+    uint32_t SBZ = 0x0u;
+    
+    _ARM_MCR(15, 0, SBZ, 7, 1, 0);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_line(const void * addr)
+{
+    uint32_t csidr = 0, line_size = 0;
+    uint32_t va;
+    
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    va = (uint32_t) addr & (~(line_size - 1)); //addr & va_VIRTUAL_ADDRESS_MASK
+    
+    // Invalidate instruction cache by va to PoU (Point of unification). 
+    _ARM_MCR(15, 0, va, 7, 5, 1);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+void arm_icache_invalidate_mlines(const void * addr, size_t length)
+{
+    uint32_t va;
+    uint32_t csidr = 0, line_size = 0;
+    const void * end_addr = (const void *)((uint32_t)addr + length);
+
+    // get the cache line size
+    _ARM_MRC(15, 1, csidr, 0, 0, 0);
+    line_size = 1 << ((csidr & 0x7) + 4);    
+    
+    do
+    {
+        // Clean data cache line to PoC (Point of Coherence) by va. 
+        va = (uint32_t) ((uint32_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK
+        _ARM_MCR(15, 0, va, 7, 5, 1);
+        // increment addres to next line and decrement lenght 
+        addr = (const void *) ((uint32_t)addr + line_size);
+    } while (addr < end_addr);
+    
+    // synchronize context on this processor 
+    _ARM_ISB();
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/ccm_pll.h

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CCM_PLL_H_
+#define _CCM_PLL_H_
+
+#include "sdk_types.h"
+
+//! @addtogroup diag_clocks
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+#define CLK_SRC_32K         32768
+
+//! @brief Create a clock gate bit mask value.
+//! @param x 0..15, for CG0 to CG15
+#define CG(x) (3 << (x*2))
+
+//! @brief Constants for CCM CCGR register fields.
+enum _clock_gate_constants
+{
+    CLOCK_ON = 0x3, //!< Clock always on in both run and stop modes.
+    CLOCK_ON_RUN = 0x1, //!< Clock on only in run mode.
+    CLOCK_OFF = 0x0 //!< Clocked gated off.
+};
+
+//! @brief Low power mdoes.
+typedef enum _lp_modes {
+    RUN_MODE,
+    WAIT_MODE,
+    STOP_MODE,
+} lp_modes_t;
+
+//! @brief Main clock sources.
+typedef enum _main_clocks {
+    CPU_CLK,
+    AXI_CLK,
+    MMDC_CH0_AXI_CLK,
+    AHB_CLK,
+    IPG_CLK,
+    IPG_PER_CLK,
+    MMDC_CH1_AXI_CLK,
+} main_clocks_t;
+
+//! @brief Peripheral clocks.
+typedef enum _peri_clocks {
+    UART1_MODULE_CLK,
+    UART2_MODULE_CLK,
+    UART3_MODULE_CLK,
+    UART4_MODULE_CLK,
+    UART5_MODULE_CLK,
+    UART6_MODULE_CLK,
+    UART7_MODULE_CLK,
+    UART8_MODULE_CLK,
+    SSI1_BAUD,
+    SSI2_BAUD,
+    CSI_BAUD,
+    MSTICK1_CLK,
+    MSTICK2_CLK,
+    RAWNAND_CLK,
+    USB_CLK,
+    VPU_CLK,
+    SPI_CLK,
+    CAN_CLK
+} peri_clocks_t;
+
+//! @brief Available PLLs.
+typedef enum plls {
+    PLL1,
+    PLL2,
+    PLL3,
+    PLL4,
+    PLL5,
+} plls_t;
+
+extern const uint32_t PLL1_OUTPUT;
+extern const uint32_t PLL2_OUTPUT[];
+extern const uint32_t PLL3_OUTPUT[];
+extern const uint32_t PLL4_OUTPUT;
+extern const uint32_t PLL5_OUTPUT;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Set/unset clock gating for a peripheral.
+//! @param   base_address configure clock gating for that module from the base address.
+//! @param   gating_mode clock gating mode: CLOCK_ON or CLOCK_OFF.
+void clock_gating_config(uint32_t base_address, uint32_t gating_mode);
+
+//! @brief Returns the frequency of a clock in megahertz.
+uint32_t get_main_clock(main_clocks_t clk);
+
+//! @brief Returns the frequency of a clock in megahertz.
+uint32_t get_peri_clock(peri_clocks_t clk);
+
+//! @brief Inits clock sources.
+void ccm_init(void);
+
+//! @brief Prepare and enter in a low power mode.
+//! @param lp_mode low power mode : WAIT_MODE or STOP_MODE.
+void ccm_enter_low_power(lp_modes_t lp_mode);
+
+//! @brief Mask/unmask an interrupt source that can wake up the processor when in a
+//! low power mode.
+//!
+//! @param   irq_id ID of the interrupt to mask/unmask.
+//! @param   doEnable Pass true to unmask the source ID.
+void ccm_set_lpm_wakeup_source(uint32_t irq_id, bool doEnable);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/ccm_pll2.c

@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sdk.h"
+#include "registers/regsccm.h"
+#include "registers/regsccmanalog.h"
+#include "registers/regsuart.h"
+#include "registers/regsepit.h"
+#include "registers/regsspba.h"
+#include "registers/regssdmaarm.h"
+#include "registers/regsgpt.h"
+#include "registers/regsi2c.h"
+#include "registers/regsecspi.h"
+#include "ccm_pll.h"
+//#include "hardware.h"
+//#include "soc_memory_map.h"
+#define HW_ANADIG_REG_CORE		(ANATOP_IPS_BASE_ADDR + 0x140)
+#define HW_ANADIG_PLL_SYS_RW  (ANATOP_IPS_BASE_ADDR + 0x000)
+#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x)	((((x)-700)/25) << 0)
+#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x)	((((x)-700)/25) << 18)
+#define HW_ANADIG_REG_CORE_V_CORE_MSK		0x1F
+#define HW_ANADIG_REG_CORE_V_SOC_MSK		(0x1F << 18)
+
+uint32_t g_arm_clk = 528000000;
+
+const uint32_t PLL2_OUTPUT[] = { 528000000, 396000000, 352000000, 198000000 };
+const uint32_t PLL3_OUTPUT[] = { 480000000, 720000000, 540000000, 508235294, 454736842 };
+const uint32_t PLL4_OUTPUT = 650000000;
+const uint32_t PLL5_OUTPUT = 650000000;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void set_soc_core_voltage(unsigned int v_core_mv, unsigned int v_soc_mv)
+{
+    unsigned int val, val_v_core, val_v_soc;
+
+    val = reg32_read(HW_ANADIG_REG_CORE);
+    val &= ~HW_ANADIG_REG_CORE_V_CORE_MSK;
+    val &= ~HW_ANADIG_REG_CORE_V_SOC_MSK;
+
+    val_v_core = HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(v_core_mv);
+    val_v_soc = HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(v_soc_mv);
+
+    val |= val_v_core | val_v_soc;
+    reg32_write(HW_ANADIG_REG_CORE, val);
+}
+
+void setup_clk(void)
+{
+		uint32_t div_select;
+		uint32_t temp;	
+		uint32_t arm_clk = g_arm_clk/1000000;
+	  
+		switch(arm_clk)
+		{
+			case 400:
+				div_select = 33;
+				set_soc_core_voltage(1150, 1175);
+				return;
+			case 528:
+				div_select = 44;
+				set_soc_core_voltage(1250, 1250);
+				break;
+			case 756:
+				div_select = 63;
+    		set_soc_core_voltage(1250, 1250);
+    		printf("ARM Clock set to 756MHz\r\n");
+    		break;
+			default:
+				return;
+    }      	    			   	    			
+    	
+    // first, make sure ARM_PODF is clear
+    HW_CCM_CACRR_WR(0);
+    // write the div_select value into HW_ANADIG_PLL_SYS_RW
+    // this will re-program the PLL to the new freq
+
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+    temp |= 0x10000;// set BYBASS 
+    writel(temp, HW_ANADIG_PLL_SYS_RW);
+
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+    temp &= ~(0x0000007F);
+    temp |= div_select;  // Update div 
+    writel(temp, HW_ANADIG_PLL_SYS_RW);
+
+		/* Wait for PLL to lock */
+		while(!(readl(HW_ANADIG_PLL_SYS_RW) & 0x80000000));
+
+		/*disable BYPASS*/
+    temp = readl(HW_ANADIG_PLL_SYS_RW);
+		temp &= ~0x10000;
+    writel(temp, HW_ANADIG_PLL_SYS_RW);		
+}
+
+void ccm_init(void)
+{
+    HW_CCM_CCGR0_WR(0xffffffff);
+    HW_CCM_CCGR1_WR(0xffffffff);    // EPIT, ESAI, GPT enabled by driver
+    HW_CCM_CCGR2_WR(0xffffffff);    // I2C enabled by driver
+    HW_CCM_CCGR3_WR(0xffffffff);
+    HW_CCM_CCGR4_WR(0xffffffff);    // GPMI, Perfmon enabled by driver
+    HW_CCM_CCGR5_WR(0xffffffff);    // UART, SATA enabled by driver
+    HW_CCM_CCGR6_WR(0xffffffff);
+
+    /*
+     * Keep default settings at reset.
+     * pre_periph_clk_sel is by default at 0, so the selected output
+     * of PLL2 is the main output at 528MHz.
+     * => by default, ahb_podf divides by 4 => AHB_CLK@132MHz.
+     * => by default, ipg_podf divides by 2 => IPG_CLK@66MHz.
+     */    
+    HW_CCM_CBCDR.U = BF_CCM_CBCDR_AHB_PODF(3)
+        | BF_CCM_CBCDR_AXI_PODF(1)
+        | BF_CCM_CBCDR_IPG_PODF(1);
+    
+    setup_clk();
+
+    /* Power up 480MHz PLL */
+    reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00001000, 0x00001000);
+
+    /* Enable 480MHz PLL */
+    reg32_write_mask(HW_CCM_ANALOG_PLL_USB1_ADDR, 0x00002000, 0x00002000);
+    
+    reg32_write_mask(HW_CCM_CSCDR1_ADDR, 0x00000000, 0x0000003F);
+}
+
+uint32_t get_main_clock(main_clocks_t clock)
+{
+    uint32_t ret_val = 0;
+    uint32_t pre_periph_clk_sel = HW_CCM_CBCMR.B.PRE_PERIPH_CLK_SEL;
+
+    switch (clock) {
+    case CPU_CLK:
+        ret_val = g_arm_clk;
+        break;
+    case AXI_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AXI_PODF + 1);
+        break;
+    case MMDC_CH0_AXI_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.MMDC_CH0_AXI_PODF + 1);
+        break;
+    case AHB_CLK:
+        ret_val = PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF + 1);
+        break;
+    case IPG_CLK:
+        ret_val =
+            PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
+                                               1) / (HW_CCM_CBCDR.B.IPG_PODF + 1);
+        break;
+    case IPG_PER_CLK:
+        ret_val =
+            PLL2_OUTPUT[pre_periph_clk_sel] / (HW_CCM_CBCDR.B.AHB_PODF +
+                                               1) / (HW_CCM_CBCDR.B.IPG_PODF +
+                                                     1) / (HW_CCM_CSCMR1.B.PERCLK_PODF + 1);
+        break;
+    default:
+        break;
+    }
+
+    return ret_val;
+}
+
+uint32_t get_peri_clock(peri_clocks_t clock)
+{
+    uint32_t ret_val = 0;
+
+    switch (clock)
+    {
+        case UART1_MODULE_CLK:
+        case UART2_MODULE_CLK:
+        case UART3_MODULE_CLK:
+        case UART4_MODULE_CLK:
+       	case UART5_MODULE_CLK:
+     		case UART6_MODULE_CLK:
+   			case UART7_MODULE_CLK:
+   			case UART8_MODULE_CLK:   				
+            // UART source clock is a fixed PLL3 / 6
+            ret_val = PLL3_OUTPUT[0] / 6 / (HW_CCM_CSCDR1.B.UART_CLK_PODF + 1);
+            break;
+        case SPI_CLK:
+            ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCDR2.B.ECSPI_CLK_PODF + 1);
+            break;
+        case RAWNAND_CLK:
+            ret_val =
+                PLL3_OUTPUT[0] / (HW_CCM_CS2CDR.B.ENFC_CLK_PRED + 1) / (HW_CCM_CS2CDR.B.ENFC_CLK_PODF +
+                                                                        1);
+            break;
+        case CAN_CLK:
+            // For i.mx6dq/sdl CAN source clock is a fixed PLL3 / 8
+        	ret_val = PLL3_OUTPUT[0] / 8 / (HW_CCM_CSCMR2.B.CAN_CLK_PODF + 1);
+        	break;
+        default:
+            break;
+    }
+
+    return ret_val;
+}
+
+void ccm_ccgr_config(uint32_t ccm_ccgrx, uint32_t cgx_offset, uint32_t gating_mode)
+{
+    if (gating_mode == CLOCK_ON)
+    {
+        *(volatile uint32_t *)(ccm_ccgrx) |= cgx_offset;
+    }
+    else
+    {
+        *(volatile uint32_t *)(ccm_ccgrx) &= ~cgx_offset;
+    }
+}
+
+void clock_gating_config(uint32_t base_address, uint32_t gating_mode)
+{
+    uint32_t ccm_ccgrx = 0;
+    uint32_t cgx_offset = 0;
+
+    switch (base_address)
+    {
+        case REGS_UART1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(12);
+            break;         	
+        case REGS_UART2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR0_ADDR;
+            cgx_offset = CG(14);
+            break;        	
+        case REGS_UART3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(5);
+            break;           	
+        case REGS_UART4_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(12);
+            break;         	
+        case REGS_UART5_BASE:
+            ccm_ccgrx = HW_CCM_CCGR3_ADDR;
+            cgx_offset = CG(1);
+            break;         	
+        case REGS_UART6_BASE:
+            ccm_ccgrx = HW_CCM_CCGR3_ADDR;
+            cgx_offset = CG(3);
+            break;          	
+        case REGS_UART7_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(13);
+            break;          	
+        case REGS_UART8_BASE:
+            ccm_ccgrx = HW_CCM_CCGR6_ADDR;
+            cgx_offset = CG(7);
+            break;
+        case REGS_SPBA_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(6);
+            break;
+        case REGS_SDMAARM_BASE:
+            ccm_ccgrx = HW_CCM_CCGR5_ADDR;
+            cgx_offset = CG(3);
+            break;
+        case REGS_EPIT1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(6);
+            break;
+        case REGS_EPIT2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(7);
+            break;
+        case REGS_GPT1_BASE:
+        case REGS_GPT2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(10)|CG(11);
+            break;            
+        case REGS_I2C1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(3);
+            break;
+        case REGS_I2C2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(4);
+            break;
+        case REGS_I2C3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR2_ADDR;
+            cgx_offset = CG(5);
+            break;
+        case REGS_ECSPI1_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(0);
+            break;        
+        case REGS_ECSPI2_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(1);
+            break;        
+        case REGS_ECSPI3_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(2);
+            break;        
+        case REGS_ECSPI4_BASE:
+            ccm_ccgrx = HW_CCM_CCGR1_ADDR;
+            cgx_offset = CG(3);
+            break;        
+        default:
+            break;
+    }
+
+    // apply changes only if a valid address was found 
+    if (ccm_ccgrx != 0)
+    {
+        ccm_ccgr_config(ccm_ccgrx, cgx_offset, gating_mode);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+// End of file
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/cortex_a.h

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__CORTEX_A_H__)
+#define __CORTEX_A9H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+//! @addtogroup cortexa9
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Instruction macros
+//@{
+#define _ARM_NOP()  asm volatile ("nop\n\t")
+#define _ARM_WFI()  asm volatile ("wfi\n\t")
+#define _ARM_WFE()  asm volatile ("wfe\n\t")
+#define _ARM_SEV()  asm volatile ("sev\n\t")
+#define _ARM_DSB()  asm volatile ("dsb\n\t")
+#define _ARM_ISB()  asm volatile ("isb\n\t")
+
+#define _ARM_MRC(coproc, opcode1, Rt, CRn, CRm, opcode2)	\
+    asm volatile ("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r" (Rt))
+    
+#define _ARM_MCR(coproc, opcode1, Rt, CRn, CRm, opcode2)	\
+    asm volatile ("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" :: [input] "r" (Rt))
+//@}
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+//! @name Misc
+//@{
+//! @brief Enable or disable the IRQ and FIQ state.
+bool arm_set_interrupt_state(bool enable);
+
+//! @brief Get current CPU ID.
+int cpu_get_current(void);
+
+//! @brief Enable the NEON MPE.
+void enable_neon_fpu(void);
+
+//! @brief Disable aborts on unaligned accesses.
+void disable_strict_align_check(void);
+
+//! @brief Get base address of private perpherial space.
+//!
+//! @return The address of the ARM CPU's private peripherals.
+uint32_t get_arm_private_peripheral_base(void);
+//@}
+
+//! @name Data cache operations
+//@{
+
+//! @brief Check if dcache is enabled or disabled.
+int arm_dcache_state_query();
+
+//! @brief Enables data cache at any available cache level.
+//!
+//! Works only if MMU is enabled!
+void arm_dcache_enable();
+
+//! @brief Disables the data cache at any available cache level.
+void arm_dcache_disable();
+
+//! @brief Invalidates the entire data cache.
+void arm_dcache_invalidate();
+
+//! @brief Invalidate a line of data cache.
+void arm_dcache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of data cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+//! Size of line for A9 L1 cache is 32B.
+void arm_dcache_invalidate_mlines(const void * addr, size_t length);
+
+//! @brief Flush (clean) all lines of cache (all sets in all ways).
+void arm_dcache_flush();
+
+//! @brief Flush (clean) one line of cache.
+void arm_dcache_flush_line(const void * addr);
+
+// @brief Flush (clean) multiple lines of cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_dcache_flush_mlines(const void * addr, size_t length);
+//@}
+
+//! @name Instrution cache operations
+//@{
+
+//! @brief Check if icache is enabled or disabled.
+int arm_icache_state_query();
+
+//! @brief Enables instruction cache at any available cache level.
+//!
+//! Works without enabled MMU too!
+void arm_icache_enable();
+
+//! @brief Disables the instruction cache at any available cache level.
+void arm_icache_disable();
+
+//! @brief Invalidates the entire instruction cache.
+void arm_icache_invalidate();
+
+//! @brief Invalidates the entire instruction cache inner shareable.
+void arm_icache_invalidate_is();
+
+//! @brief Invalidate a line of the instruction cache.
+void arm_icache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of instruction cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_icache_invalidate_mlines(const void * addr, size_t length);
+//@}
+
+//! @name TLB operations
+//@{
+//! @brief Invalidate entire unified TLB.
+void arm_unified_tlb_invalidate(void);
+
+//! @brief Invalidate entire unified TLB Inner Shareable.
+void arm_unified_tlb_invalidate_is(void);
+//@}
+
+//! @name Branch predictor operations
+//@{
+//! @brief Enable branch prediction.
+void arm_branch_prediction_enable(void);
+
+//! @brief Disable branch prediction.
+void arm_branch_prediction_disable(void);
+
+//! @brief Invalidate entire branch predictor array.
+void arm_branch_target_cache_invalidate(void);
+
+//! @brief Invalidate entire branch predictor array Inner Shareable
+void arm_branch_target_cache_invalidate_is(void);
+//@}
+
+//! @name SCU
+//@{
+//! @brief Enables the SCU.
+void scu_enable(void);
+
+//! @brief Set this CPU as participating in SMP.
+void scu_join_smp(void);
+
+//! @brief Set this CPU as not participating in SMP.
+void scu_leave_smp(void);
+
+//! @brief Determine which CPUs are participating in SMP.
+//!
+//! The return value is 1 bit per core:
+//! - bit 0 - CPU 0
+//! - bit 1 - CPU 1
+//! - etc...
+unsigned int scu_get_cpus_in_smp(void);
+
+//! @brief Enable the broadcasting of cache & TLB maintenance operations.
+//!
+//! When enabled AND in SMP, broadcast all "inner sharable"
+//! cache and TLM maintenance operations to other SMP cores
+void scu_enable_maintenance_broadcast(void);
+
+//! @brief Disable the broadcasting of cache & TLB maintenance operations.
+void scu_disable_maintenance_broadcast(void);
+
+//! @brief Invalidates the SCU copy of the tag rams for the specified core.
+//!
+//! Typically only done at start-up.
+//! Possible flow:
+//! - Invalidate L1 caches
+//! - Invalidate SCU copy of TAG RAMs
+//! - Join SMP
+//!
+//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
+//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
+void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __CORTEX_A_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/cortex_a_gcc.S

@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file cortexA9.s
+ * @brief This file contains cortexA9 functions
+ *
+ */
+ 
+    .code 32
+    .section ".text","ax"
+
+/*
+ * bool arm_set_interrupt_state(bool enable)
+ */
+    .global arm_set_interrupt_state
+    .func arm_set_interrupt_state
+arm_set_interrupt_state:
+    mrs             r2,CPSR            @ read CPSR (Current Program Status Register)
+    teq     r0,#0
+    bicne   r1,r2,#0xc0        @ disable IRQ and FIQ
+    orreq   r1,r2,#0xc0        @ enable IRQ and FIQ
+    msr     CPSR_c,r1
+    tst     r2,#0x80
+    movne   r0,#0
+    moveq   r0,#1
+    bx      lr
+    .endfunc
+
+  .global cpu_get_current
+  @ int cpu_get_current(void)@
+  @ get current CPU ID
+  .func cpu_get_current
+cpu_get_current: 
+    mrc   p15, 0, r0, c0, c0, 5
+    and   r0, r0, #3
+	BX	  lr
+  .endfunc    @cpu_get_current()@
+
+  .global enable_neon_fpu
+  .func enable_neon_fpu
+enable_neon_fpu:
+	/* set NSACR, both Secure and Non-secure access are allowed to NEON */
+	MRC p15, 0, r0, c1, c1, 2
+	ORR r0, r0, #(0x3<<10) @ enable fpu/neon
+	MCR p15, 0, r0, c1, c1, 2
+	/* Set the CPACR for access to CP10 and CP11*/
+	LDR r0, =0xF00000
+	MCR p15, 0, r0, c1, c0, 2
+	/* Set the FPEXC EN bit to enable the FPU */
+	MOV r3, #0x40000000 
+	@VMSR FPEXC, r3
+	MCR p10, 7, r3, c8, c0, 0
+  .endfunc
+
+  .global disable_strict_align_check
+  .func disable_strict_align_check
+disable_strict_align_check:
+  	/*Ray's note: disable strict alignment fault checking.
+ 	without disabling this, data abort will happen when accessing
+	the BPB structure of file system since it is packed.*/
+    
+  	push	{r0, lr}
+	
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<1) @clear A bit of SCTLR 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0, pc}
+  .endfunc
+
+  .global disable_L1_cache
+  .func disable_L1_cache
+disable_L1_cache:
+    push	{r0-r6, lr}
+
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, r0, #(0x1<<12) 
+	bic r0, r0, #(0x1<<11) 
+	bic r0, r0, #(0x1<<2) 
+	bic r0, r0, #(0x1<<0) 
+	mcr p15, 0, r0, c1, c0, 0
+
+    pop {r0-r6, pc}
+
+  .endfunc
+
+  .global get_arm_private_peripheral_base
+  @ uint32_t get_arm_private_peripheral_base(void)@
+  .func get_arm_private_peripheral_base
+get_arm_private_peripheral_base: 
+
+  @ Get base address of private perpherial space
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+  bx      lr
+  
+  .endfunc    @get_arm_private_peripheral_base()@
+
+@ ------------------------------------------------------------
+@ TLB
+@ ------------------------------------------------------------
+
+  .global arm_unified_tlb_invalidate
+  @ void arm_unified_tlb_invalidate(void)@
+  .func arm_unified_tlb_invalidate
+arm_unified_tlb_invalidate:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c7, 0                 @ TLBIALL - Invalidate entire unified TLB
+  dsb
+  bx      lr
+  .endfunc
+
+  .global arm_unified_tlb_invalidate_is
+  @ void arm_unified_tlb_invalidate_is(void)@
+  .func arm_unified_tlb_invalidate_is
+arm_unified_tlb_invalidate_is:
+  mov     r0, #1
+  mcr     p15, 0, r0, c8, c3, 0                 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable
+  dsb
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ Branch Prediction
+@ ------------------------------------------------------------
+
+  .global arm_branch_prediction_enable
+  @ void arm_branch_prediction_enable(void)
+  .func arm_branch_prediction_enable
+arm_branch_prediction_enable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  orr     r0, r0, #(1 << 11)                    @ Set the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+
+  .global arm_branch_prediction_disable
+  @ void arm_branch_prediction_disable(void)
+  .func arm_branch_prediction_disable
+arm_branch_prediction_disable:
+  mrc     p15, 0, r0, c1, c0, 0                 @ Read SCTLR
+  bic     r0, r0, #(1 << 11)                    @ Clear the Z bit (bit 11)
+  mcr     p15, 0,r0, c1, c0, 0                  @ Write SCTLR
+  bx      lr
+  .endfunc
+  
+  .global arm_branch_target_cache_invalidate
+  @ void arm_branch_target_cache_invalidate(void)
+  .func arm_branch_target_cache_invalidate
+arm_branch_target_cache_invalidate:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c5, 6                 @ BPIALL - Invalidate entire branch predictor array
+  bx      lr
+  .endfunc
+
+  .global arm_branch_target_cache_invalidate_is
+  @ void arm_branch_target_cache_invalidate_is(void)
+  .func arm_branch_target_cache_invalidate_is
+arm_branch_target_cache_invalidate_is:
+  mov     r0, #0
+  mcr     p15, 0, r0, c7, c1, 6                 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+@ SCU
+@ ------------------------------------------------------------
+
+  @ SCU offset from base of private peripheral space --> 0x000
+
+  .global scu_enable
+  @ void scu_enable(void)
+  @ Enables the SCU
+  .func scu_enable
+scu_enable:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r1, [r0, #0x0]          @ Read the SCU Control Register
+  orr     r1, r1, #0x1            @ Set bit 0 (The Enable bit)
+  str     r1, [r0, #0x0]          @ Write back modifed value
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global  scu_join_smp
+  @ void scu_join_smp(void)
+  @ Set this CPU as participating in SMP
+  .func scu_join_smp
+scu_join_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  orr     r0, r0, #0x040          @ Set bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_leave_smp
+  @ void scu_leave_smp(void)
+  @ Set this CPU as NOT participating in SMP
+  .func scu_leave_smp
+scu_leave_smp:
+
+  @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg
+
+  mrc     p15, 0, r0, c1, c0, 1   @ Read ACTLR
+  bic     r0, r0, #0x040          @ Clear bit 6
+  mcr     p15, 0, r0, c1, c0, 1   @ Write ACTLR
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_get_cpus_in_smp
+  @ unsigned int scu_get_cpus_in_smp(void)
+  @ The return value is 1 bit per core:
+  @ bit 0 - CPU 0
+  @ bit 1 - CPU 1
+  @ etc...
+  .func scu_get_cpus_in_smp
+scu_get_cpus_in_smp:
+
+  mrc     p15, 4, r0, c15, c0, 0  @ Read periph base address
+
+  ldr     r0, [r0, #0x004]        @ Read SCU Configuration register
+  mov     r0, r0, lsr #4          @ Bits 7:4 gives the cores in SMP mode, shift then mask
+  and     r0, r0, #0x0F
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_enable_maintenance_broadcast
+  @ void scu_enable_maintenance_broadcast(void)
+  @ Enable the broadcasting of cache & TLB maintenance operations
+  @ When enabled AND in SMP, broadcast all "inner sharable"
+  @ cache and TLM maintenance operations to other SMP cores
+  .func scu_enable_maintenance_broadcast
+scu_enable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  orr     r0, r0, #0x01           @ Set the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_disable_maintenance_broadcast
+  @ void scu_disable_maintenance_broadcast(void)
+  @ Disable the broadcasting of cache & TLB maintenance operations
+  .func scu_disable_maintenance_broadcast
+scu_disable_maintenance_broadcast:
+  mrc     p15, 0, r0, c1, c0, 1   @ Read Aux Ctrl register
+  bic     r0, r0, #0x01           @ Clear the FW bit (bit 0)
+  mcr     p15, 0, r0, c1, c0, 1   @ Write Aux Ctrl register
+
+  bx      lr
+  .endfunc
+
+@ ------------------------------------------------------------
+
+  .global scu_secure_invalidate
+  @ void scu_secure_invalidate(unsigned int cpu, unsigned int ways)
+  @ cpu: 0x0=CPU 0 0x1=CPU 1 etc...
+  @ This function invalidates the SCU copy of the tag rams
+  @ for the specified core.  typically only done at start-up.
+  @ Possible flow:
+  @ - Invalidate L1 caches
+  @ - Invalidate SCU copy of TAG RAMs
+  @ - Join SMP
+  .func scu_secure_invalidate
+scu_secure_invalidate:
+  and     r0, r0, #0x03           @ Mask off unused bits of CPU ID
+  mov     r0, r0, lsl #2          @ Convert into bit offset (four bits per core)
+  
+  and     r1, r1, #0x0F           @ Mask off unused bits of ways
+  mov     r1, r1, lsl r0          @ Shift ways into the correct CPU field
+
+  mrc     p15, 4, r2, c15, c0, 0  @ Read periph base address
+
+  str     r1, [r2, #0x0C]         @ Write to SCU Invalidate All in Secure State
+  
+  bx      lr
+
+  .endfunc
+
+@ ------------------------------------------------------------
+@ End of cortexA9.s
+@ ------------------------------------------------------------
+    .end

bsp/imx6ul/platform/cpu/gic.c

@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <assert.h>
+#include "gic.h"
+#include "gic_registers.h"
+#include "cortex_a.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static inline gicd_t * gic_get_gicd(void);
+static inline gicc_t * gic_get_gicc(void);
+static inline uint32_t irq_get_register_offset(uint32_t irqID);
+static inline uint32_t irq_get_bit_offset(uint32_t irqID);
+static inline uint32_t irq_get_bit_mask(uint32_t irqID);
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+static inline gicd_t * gic_get_gicd(void)
+{
+    uint32_t base = get_arm_private_peripheral_base() + kGICDBaseOffset;
+    return (gicd_t *)base;
+}
+
+static inline gicc_t * gic_get_gicc(void)
+{
+    uint32_t base = get_arm_private_peripheral_base() + kGICCBaseOffset;
+    return (gicc_t *)base;
+}
+
+static inline uint32_t irq_get_register_offset(uint32_t irqID)
+{
+    return irqID / 32;
+}
+
+static inline uint32_t irq_get_bit_offset(uint32_t irqID)
+{
+    return irqID & 0x1f;
+}
+
+static inline uint32_t irq_get_bit_mask(uint32_t irqID)
+{
+    return 1 << irq_get_bit_offset(irqID);    
+}
+
+void gic_enable(bool enableIt)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    if (enableIt)
+    {
+        // Enable both secure and non-secure.
+        gicd->CTLR |= kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1;
+    }
+    else
+    {
+        // Clear the enable bits.
+        gicd->CTLR &= ~(kBM_GICD_CTLR_EnableGrp0 | kBM_GICD_CTLR_EnableGrp1);
+    }
+}
+
+void gic_set_irq_security(uint32_t irqID, bool isSecure)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    uint32_t reg = irq_get_register_offset(irqID);
+    uint32_t mask = irq_get_bit_mask(irqID);
+    
+    uint32_t value = gicd->IGROUPRn[reg];
+    if (!isSecure)
+    {
+        value &= ~mask;
+    }
+    else
+    {
+        value |= mask;
+    }
+    gicd->IGROUPRn[reg] = value;
+}
+
+void gic_enable_irq(uint32_t irqID, bool isEnabled)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    uint32_t reg = irq_get_register_offset(irqID);
+    uint32_t mask = irq_get_bit_mask(irqID);
+    
+    // Select set-enable or clear-enable register based on enable flag.
+    if (isEnabled)
+    {
+        gicd->ISENABLERn[reg] = mask;
+    }
+    else
+    {
+        gicd->ICENABLERn[reg] = mask;
+    }
+}
+
+void gic_set_irq_priority(uint32_t ID, uint32_t priority)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    // Update the priority register. The priority registers are byte accessible, and the register
+    // struct has the priority registers as a byte array, so we can just index directly by the
+    // interrupt ID.
+    gicd->IPRIORITYRn[ID] = priority & 0xff;
+}
+
+void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt)
+{
+    // Make sure the CPU number is valid.
+    assert(cpuNumber <= 7);
+    
+    gicd_t * gicd = gic_get_gicd();
+    uint8_t cpuMask = 1 << cpuNumber;
+    
+    // Like the priority registers, the target registers are byte accessible, and the register
+    // struct has the them as a byte array, so we can just index directly by the
+    // interrupt ID.
+    if (enableIt)
+    {
+        gicd->ITARGETSRn[irqID] |= (cpuMask & 0xff);
+    }
+    else
+    {
+        gicd->ITARGETSRn[irqID] &= ~(cpuMask & 0xff);
+    }
+}
+
+void gic_send_sgi(uint32_t irqID, uint32_t target_list, uint32_t filter_list)
+{
+    gicd_t * gicd = gic_get_gicd();
+    
+    gicd->SGIR = (filter_list << kBP_GICD_SGIR_TargetListFilter)
+                    | (target_list << kBP_GICD_SGIR_CPUTargetList)
+                    | (irqID & 0xf);
+}
+
+void gic_cpu_enable(bool enableIt)
+{
+    gicc_t * gicc = gic_get_gicc();
+    
+    if (enableIt)
+    {
+        gicc->CTLR |= kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS;
+    }
+    else
+    {
+        gicc->CTLR &= ~(kBM_GICC_CTLR_EnableS | kBM_GICC_CTLR_EnableNS);
+    }
+}
+
+void gic_set_cpu_priority_mask(uint32_t priority)
+{
+    gicc_t * gicc = gic_get_gicc();
+    gicc->PMR = priority & 0xff;    
+}
+
+uint32_t gic_read_irq_ack(void)
+{
+    gicc_t * gicc = gic_get_gicc();
+    return gicc->IAR;
+}
+
+void gic_write_end_of_irq(uint32_t irqID)
+{
+    gicc_t * gicc = gic_get_gicc();
+    gicc->EOIR = irqID;
+}
+
+void gic_init(void)
+{
+    gicd_t * gicd = gic_get_gicd();
+
+    // First disable the distributor.
+    gic_enable(false);
+    
+    // Clear all pending interrupts.
+    int i;
+    for (i = 0; i < 32; ++i)
+    {
+        gicd->ICPENDRn[i] = 0xffffffff;
+    }
+    
+    // Set all interrupts to secure.
+    for (i = 0; i < 8; ++i)
+    {
+        gicd->IGROUPRn[i] = 0;
+    }
+
+    // Init the GIC CPU interface.
+    gic_init_cpu();
+    
+    // Now enable the distributor.
+    gic_enable(true);
+}
+
+void gic_init_cpu(void)
+{
+    // Init the GIC CPU interface.
+    gic_set_cpu_priority_mask(0xff);
+
+    // Disable preemption.
+    gicc_t * gicc = gic_get_gicc();
+    gicc->BPR = 7;
+
+    // Enable signaling the CPU.
+    gic_cpu_enable(true);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/gic_registers.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "sdk_types.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Offsets to the GIC registers.
+enum _gic_base_offsets
+{
+    kGICDBaseOffset = 0x1000,   //!< GIC distributor offset.
+#if defined(CHIP_MX6UL)
+    kGICCBaseOffset = 0x2000     //!< GIC CPU interface offset.
+#else    
+    kGICCBaseOffset = 0x100     //!< GIC CPU interface offset.
+#endif    
+};
+
+//! @brief GIC distributor registers.
+//!
+//! Uses the GICv2 register names, but does not include GICv2 registers.
+//!
+//! The IPRIORITYRn and ITARGETSRn registers are byte accessible, so their types are uint8_t
+//! instead of uint32_t to reflect this. These members are indexed directly with the interrupt
+//! number.
+struct _gicd_registers
+{
+    uint32_t CTLR;              //!< Distributor Control Register.
+    uint32_t TYPER;             //!< Interrupt Controller Type Register.
+    uint32_t IIDR;              //!< Distributor Implementer Identification Register.
+    uint32_t _reserved0[29];
+    uint32_t IGROUPRn[8];       //!< Interrupt Group Registers.
+    uint32_t _reserved1[24];
+    uint32_t ISENABLERn[32];    //!< Interrupt Set-Enable Registers.
+    uint32_t ICENABLERn[32];    //!< Interrupt Clear-Enable Registers.
+    uint32_t ISPENDRn[32];      //!< Interrupt Set-Pending Registers.
+    uint32_t ICPENDRn[32];      //!< Interrupt Clear-Pending Registers.
+    uint32_t ICDABRn[32];       //!< Active Bit Registers.
+    uint32_t _reserved2[32];
+    uint8_t IPRIORITYRn[255 * sizeof(uint32_t)];  //!< Interrupt Priority Registers. (Byte accessible)
+    uint32_t _reserved3;
+    uint8_t ITARGETSRn[255 * sizeof(uint32_t)];   //!< Interrupt Processor Targets Registers. (Byte accessible)
+    uint32_t _reserved4;
+    uint32_t ICFGRn[64];        //!< Interrupt Configuration Registers.
+    uint32_t _reserved5[128];
+    uint32_t SGIR;              //!< Software Generated Interrupt Register
+};
+
+//! @brief Bitfields constants for the GICD_CTLR register.
+enum _gicd_ctlr_fields
+{
+    kBM_GICD_CTLR_EnableGrp1 = (1 << 1),
+    kBM_GICD_CTLR_EnableGrp0 = (1 << 0)
+};
+
+//! @brief Bitfields constants for the GICD_SGIR register.
+enum _gicd_sgir_fields
+{
+    kBP_GICD_SGIR_TargetListFilter = 24,
+    kBM_GICD_SGIR_TargetListFilter = (0x3 << kBP_GICD_SGIR_TargetListFilter),
+    
+    kBP_GICD_SGIR_CPUTargetList = 16,
+    kBM_GICD_SGIR_CPUTargetList = (0xff << kBP_GICD_SGIR_CPUTargetList),
+    
+    kBP_GICD_SGIR_NSATT = 15,
+    kBM_GICD_SGIR_NSATT = (1 << kBP_GICD_SGIR_NSATT),
+    
+    kBP_GICD_SGIR_SGIINTID = 0,
+    kBM_GICD_SGIR_SGIINTID = 0xf
+};
+
+//! @brief GIC CPU interface registers.
+//!
+//! Uses the GICv2 register names. Does not include GICv2 registers.
+struct _gicc_registers
+{
+    uint32_t CTLR;  //!< CPU Interface Control Register.
+    uint32_t PMR;   //!< Interrupt Priority Mask Register.
+    uint32_t BPR;   //!< Binary Point Register.
+    uint32_t IAR;   //!< Interrupt Acknowledge Register.
+    uint32_t EOIR;  //!< End of Interrupt Register.
+    uint32_t RPR;   //!< Running Priority Register.
+    uint32_t HPPIR; //!< Highest Priority Pending Interrupt Register.
+    uint32_t ABPR;  //!< Aliased Binary Point Register. (only visible with a secure access)
+    uint32_t _reserved[56];
+    uint32_t IIDR;  //!< CPU Interface Identification Register.
+};
+
+//! @brief Bitfields constants for the GICC_CTLR register.
+enum _gicc_ctlr_fields
+{
+    kBP_GICC_CTLR_EnableS = 0,
+    kBM_GICC_CTLR_EnableS = (1 << 0),
+    
+    kBP_GICC_CTLR_EnableNS = 1,
+    kBM_GICC_CTLR_EnableNS = (1 << 1),
+    
+    kBP_GICC_CTLR_AckCtl = 2,
+    kBM_GICC_CTLR_AckCtl = (1 << 2),
+    
+    kBP_GICC_CTLR_FIQEn = 3,
+    kBM_GICC_CTLR_FIQEn = (1 << 3),
+    
+    kBP_GICC_CTLR_SBPR = 4,
+    kBM_GICC_CTLR_SBPR = (1 << 4)
+};
+
+//! @brier Type for the GIC distributor registers.
+typedef volatile struct _gicd_registers gicd_t;
+
+//! @brier Type for the GIC CPU interface registers.
+typedef volatile struct _gicc_registers gicc_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/mmu.c

@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file  mmu.c
+ * @brief System memory arangement.
+ */
+#include "cortex_a.h"
+#include "mmu.h"
+#include "arm_cp_registers.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Size in bytes of the first-level page table.
+#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024)
+
+//! @brief First-level 1MB section descriptor entry.
+typedef union mmu_l1_section {
+    uint32_t u;
+    struct {
+        uint32_t id:2;  //!< ID
+        uint32_t b:1;   //!< Bufferable
+        uint32_t c:1;   //!< Cacheable
+        uint32_t xn:1;  //!< Execute-not
+        uint32_t domain:4;  //!< Domain
+        uint32_t _impl_defined:1;   //!< Implementation defined, should be zero.
+        uint32_t ap1_0:2;  //!< Access permissions AP[1:0]
+        uint32_t tex:3; //!< TEX remap
+        uint32_t ap2:1; //!< Access permissions AP[2] 
+        uint32_t s:1;   //!< Shareable
+        uint32_t ng:1;  //!< Not-global
+        uint32_t _zero:1;   //!< Should be zero.
+        uint32_t ns:1;  //!< Non-secure
+        uint32_t address:12;   //!< Physical base address
+    };
+} mmu_l1_section_t;
+
+enum {
+    kMMU_L1_Section_ID = 2,  //!< ID value for a 1MB section first-level entry.
+    kMMU_L1_Section_Address_Shift = 20  //!< Bit offset of the physical base address field.
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+
+extern char __l1_page_table_start;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void mmu_enable()
+{
+    // invalidate all tlb 
+    arm_unified_tlb_invalidate();
+
+    // read SCTLR 
+    uint32_t sctlr;
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // set MMU enable bit 
+    sctlr |= BM_SCTLR_M;
+
+    // write modified SCTLR
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+}
+
+void mmu_disable()
+{
+    // read current SCTLR 
+    uint32_t sctlr;
+    _ARM_MRC(15, 0, sctlr, 1, 0, 0);
+    
+    // clear MMU enable bit 
+    sctlr &=~ BM_SCTLR_M;
+
+    // write modified SCTLR
+    _ARM_MCR(15, 0, sctlr, 1, 0, 0);
+}
+
+void mmu_init()
+{
+    // Get the L1 page table base address.
+    uint32_t * table = (uint32_t *)&__l1_page_table_start;
+    uint32_t share_attr = kShareable;
+
+    // write table address to TTBR0
+    _ARM_MCR(15, 0, table, 2, 0, 0);
+
+    // set Client mode for all Domains
+    uint32_t dacr = 0x55555555; 
+    _ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
+
+    // Clear the L1 table.
+    bzero(table, MMU_L1_PAGE_TABLE_SIZE);
+    
+    // Create default mappings.
+    mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
+    mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
+    mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
+   
+    // Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable.
+    uint32_t actlr = 0x0;
+    _ARM_MRC(15, 0, actlr, 1, 0, 1);
+    if (actlr & BM_ACTLR_SMP)
+    {
+        share_attr = kShareable;
+    }
+    else
+    {
+        share_attr = kNonshareable;
+    }
+
+#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL)
+    mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR
+#elif defined(CHIP_MX6SL) || defined(CHIP_MX6UL)
+    mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR
+#else
+#error Unknown chip type!
+#endif
+}
+
+void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access)
+{
+    register mmu_l1_section_t entry;
+    entry.u = 0;
+    
+    // Set constant attributes.
+    entry.id = kMMU_L1_Section_ID;
+    entry.xn = 0; // Allow execution
+    entry.domain = 0; // Domain 0
+    entry.ng = 0; // Global
+    entry.ns = 0; // Secure
+    
+    // Set attributes based on the selected memory type.
+    switch (memoryType)
+    {
+        case kStronglyOrdered:
+            entry.c = 0;
+            entry.b = 0;
+            entry.tex = 0;
+            entry.s = 1; // Ignored
+            break;
+        case kDevice:
+            if (isShareable)
+            {
+                entry.c = 0;
+                entry.b = 1;
+                entry.tex = 0;
+                entry.s = 1; // Ignored
+            }
+            else
+            {
+                entry.c = 0;
+                entry.b = 0;
+                entry.tex = 2;
+                entry.s = 0; // Ignored
+            }
+            break;
+        case kOuterInner_WB_WA:
+            entry.c = 1;
+            entry.b = 1;
+            entry.tex = 1;
+            entry.s = isShareable;
+            break;
+        case kOuterInner_WT:
+            entry.c = 1;
+            entry.b = 0;
+            entry.tex = 0;
+            entry.s = isShareable;
+            break;
+        case kNoncacheable:
+            entry.c = 0;
+            entry.b = 0;
+            entry.tex = 1;
+            entry.s = isShareable;
+            break;
+    }
+    
+    // Set attributes from specified access mode.
+    switch (access)
+    {
+        case kNoAccess:
+            entry.ap2 = 0;
+            entry.ap1_0 = 0;
+            break;
+        case kROAccess:
+            entry.ap2 = 1;
+            entry.ap1_0 = 3;
+            break;
+        case kRWAccess:
+            entry.ap2 = 0;
+            entry.ap1_0 = 3;
+            break;
+    }
+    
+    // Get the L1 page table base address.
+    uint32_t * table = (uint32_t *)&__l1_page_table_start;
+    
+    // Convert addresses to 12-bit bases.
+    uint32_t vbase = va >> kMMU_L1_Section_Address_Shift;
+    uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift;
+    uint32_t entries = length >> kMMU_L1_Section_Address_Shift;
+
+    // Fill in L1 page table entries.
+    for (; entries > 0; ++pbase, ++vbase, --entries)
+    {
+        entry.address = pbase;
+        table[vbase] = entry.u;
+    }
+    
+    // Invalidate TLB
+    arm_unified_tlb_invalidate();
+}
+
+bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress)
+{
+    uint32_t pa = 0;
+    
+    // VA to PA translation with privileged read permission check  
+    _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0);
+    
+    // Read PA register 
+    _ARM_MRC(15, 0, pa, 7, 4, 0);
+    
+    // First bit of returned value is Result of conversion (0 is successful translation) 
+    if (pa & 1)
+    {
+        // We can try write permission also 
+        // VA to PA translation with privileged write permission check  
+        _ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1);
+        
+        // Read PA register 
+        _ARM_MRC(15, 0, pa, 7, 4, 0);
+        
+        // First bit of returned value is Result of conversion (0 is successful translation) 
+        if (pa & 1)
+        {
+            return false;
+        }
+    }
+    
+    if (physicalAddress)
+    {
+        // complete address returning base + offset
+        pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff);
+        *physicalAddress = pa;
+    }
+    
+    return true;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/cpu/mmu.h

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_mmu
+//! @{
+
+/*!
+ * @file  mmu.h
+ * @brief System memory arrangement.
+ */
+
+#ifndef _MMU_H_
+#define _MMU_H_
+
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Memory region attributes.
+typedef enum _mmu_memory_type
+{
+    kStronglyOrdered,
+    kDevice,
+    kOuterInner_WB_WA,
+    kOuterInner_WT,
+    kNoncacheable,
+} mmu_memory_type_t;
+
+//! @brief Memory region shareability options.
+typedef enum _mmu_shareability
+{
+    kShareable = 1,
+    kNonshareable = 0
+} mmu_shareability_t;
+
+//! @brief Access permissions for a memory region.
+typedef enum _mmu_access
+{
+    kNoAccess,
+    kROAccess,
+    kRWAccess
+} mmu_access_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable the MMU.
+ *
+ * The L1 page tables and MMU settings must have already been configured by
+ * calling mmu_init() before the MMU is enabled.
+ */
+void mmu_enable();
+
+/*!
+ * @brief Disable the MMU.
+ */
+void mmu_disable();
+
+/*!
+ * @brief Set up the default first-level page table.
+ *
+ * Initializes the L1 page table with the following regions:
+ *  - 0x00000000...0x00900000 : ROM and peripherals, strongly-ordered
+ *  - 0x00900000...0x00a00000 : OCRAM, strongly-ordered
+ *  - For MX6DQ or MX6SDL: 0x10000000...0x90000000 : DDR, normal, outer inner, write-back, write-allocate
+ *  - For MX6SL: 0x80000000...0xc0000000 : DDR, normal, outer inner, write-back, write-allocate
+ *
+ * If the CPU is participating in SMP, then the DDR regions are made shareable. Otherwise they
+ * are marked as non-shareable.
+ *
+ * The TTBR0 register is set to the base of the L1 table.
+ *
+ * All memory domains are configured to allow client access. However, note that only domain 0 is
+ * used by mmu_map_l1_range().
+ */
+void mmu_init();
+
+/*!
+ * @brief Maps a range of memory in the first-level page table.
+ *
+ * Entries in the first-level page table are filled in for the range of virtual addresses
+ * starting at @a va and continuing for @a length bytes. These virtual addreses are mapped
+ * to the physical addresses starting at @a pa and continuing for @a length bytes. All table
+ * entries for the range of mapped memory have the same attributes, which are selected with
+ * the @a memoryType, @a isShareable, and @a access parameters.
+ *
+ * @param pa The base physical address of the range to which the virtual address will be mapped.
+ * @param va The base virtual address of the range.
+ * @param length The size of the range to be mapped, in bytes. This value must be divisible by 1MB.
+ * @param memoryType The type of the memory region. This controls caching, buffering, ordering of
+ *      memory accesses, and other attributes of the region.
+ * @param isShareable The shareability of the physical memory. Ignored for strongly-ordered memory.
+ * @param access Access permissions.
+ */
+void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access);
+
+/*!
+ * @brief Convert virtual address to physical.
+ *
+ * First attempts a priviledged read translation for the current security mode. If that fails,
+ * a priviledged write translation, also for the current security mode, is attempted. If this
+ * second attempt at translation fails, then false will be returned.
+ *
+ * @param virtualAddress Virtual address to convert to a physical address.
+ * @param[out] physicalAddress This parameter is filled in with the physical address corresponding
+ *      to the virtual address passed in @a virtualAddress.
+ * @retval true The address returned through @a physicalAddress is valid.
+ * @retval false The conversion failed for some reason.
+ */
+bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // _MMU_H_
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/drivers/epit.c

@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file epit.c
+ * @brief EPIT driver source file.
+ *
+ * @ingroup diag_timer
+ */
+
+#include "epit.h"
+
+#include "imx_timer.h"
+#include "interrupt.h"
+#include "ccm_pll.h"
+#include "registers/regsepit.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void epit_reload_counter(uint32_t instance, uint32_t load_val)
+{
+    // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1 
+    HW_EPIT_LR_WR(instance, load_val);
+}
+
+uint32_t epit_get_counter_value(uint32_t instance)
+{
+    return HW_EPIT_CNR_RD(instance);
+}
+
+void epit_set_compare_event(uint32_t instance, uint32_t compare_val)
+{
+    HW_EPIT_CMPR_WR(instance, compare_val);
+}
+
+uint32_t epit_get_compare_event(uint32_t instance)
+{
+    uint32_t status_register;
+
+    // get the status 
+    status_register = HW_EPIT_SR_RD(instance);
+    
+    // clear it if found set 
+    if (status_register & BM_EPIT_SR_OCIF)
+    {
+        HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+    }
+
+    // return the read value before the bit was cleared 
+    return status_register & BM_EPIT_SR_OCIF;
+}
+
+void epit_counter_disable(uint32_t instance)
+{
+    /* temporary workaround for the discovered issue when disabling the
+     * counter during end of count/reload/set compare flag ??.
+     * Set to the max value so that it ensures that the counter couldn't
+     * reach 0 when it is disabled.
+     */
+    HW_EPIT_LR_WR(instance, 0xFFFFFFFF);
+
+    // disable the counter 
+    HW_EPIT_CR_CLR(instance, BM_EPIT_CR_EN);
+
+    // ensure to leave the counter in a proper state
+    // by disabling the output compare interrupt
+    HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
+    
+    // and clearing possible remaining compare event 
+    HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+}
+
+void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode)
+{
+    // set the load register especially if RLD=reload_mode=SET_AND_FORGET=1
+    // and if the value is different from 0 which is the lowest counter value
+    if (load_val != 0)
+    {
+        HW_EPIT_LR_WR(instance, load_val);
+    }
+
+    // ensure to start the counter in a proper state
+    // by clearing possible remaining compare event
+    HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
+
+    // set the mode when the output compare event occur: IRQ or polling 
+    if (irq_mode == IRQ_MODE)
+    {
+        HW_EPIT_CR_SET(instance, BM_EPIT_CR_OCIEN);
+    }
+    else
+    {
+        // polling 
+        HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
+    }
+
+    // finally, enable the counter 
+    HW_EPIT_CR_SET(instance, BM_EPIT_CR_EN);
+}
+
+void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt)
+{
+    uint32_t irq_id = EPIT_IRQS(instance);
+
+    if (enableIt)
+    {    
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ 
+        enable_interrupt(irq_id, CPU_0, 0);
+    }
+    else
+    {
+        // disable the IRQ 
+        disable_interrupt(irq_id, CPU_0);
+    }
+}
+
+void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
+               uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode)
+{
+    uint32_t control_reg_tmp = 0;
+    uint32_t base = REGS_EPIT_BASE(instance);
+
+    // enable the source clocks to the EPIT port 
+    clock_gating_config(base, CLOCK_ON);
+
+    // start with a known state by disabling and reseting the module 
+    HW_EPIT_CR_WR(instance, BM_EPIT_CR_SWR);
+    
+    // wait for the reset to complete 
+    while ((HW_EPIT_CR(instance).B.SWR) != 0) ;
+
+    // set the reference source clock for the counter 
+    control_reg_tmp |= BF_EPIT_CR_CLKSRC(clock_src);
+
+    // set the counter clock prescaler value - 0 to 4095 
+    control_reg_tmp |= BF_EPIT_CR_PRESCALAR(prescaler-1);
+
+    // set the reload mode 
+    if (reload_mode == SET_AND_FORGET)
+    {
+        control_reg_tmp |= BM_EPIT_CR_RLD;
+    }
+
+    // set behavior for low power mode 
+    if (low_power_mode & WAIT_MODE_EN)
+    {
+        control_reg_tmp |= BM_EPIT_CR_WAITEN;
+    }
+    if (low_power_mode & STOP_MODE_EN)
+    {
+        control_reg_tmp |= BM_EPIT_CR_STOPEN;
+    }
+
+    // make the counter start from a known value when enabled, this is loaded from
+    // EPITLR register if RLD=reload_mode=1 or 0xFFFFFFFF if RLD=reload_mode=0
+    control_reg_tmp |= BM_EPIT_CR_IOVW | BM_EPIT_CR_ENMOD;
+
+    // finally write the control register 
+    HW_EPIT_CR_WR(instance, control_reg_tmp);
+
+    // initialize the load register especially if RLD=reload_mode=SET_AND_FORGET=1 
+    // and if the value is different from 0 which is the lowest counter value
+    if (load_val != 0)
+    {
+        HW_EPIT_LR_WR(instance, load_val);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/gpt.c

@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file gpt.c
+ * @brief  GPT driver source file.
+ *
+ * @ingroup diag_timer
+ */
+
+#include "sdk.h"
+#include "gpt.h"
+
+#include "imx_timer.h"
+#include "registers/regsgpt.h"
+#include "interrupt.h"
+#include "ccm_pll.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+static inline void gpt_clear_all_events(void)
+{
+    HW_GPT_SR_WR(kGPTAllEvents);
+}
+
+uint32_t gpt_get_rollover_event(void)
+{
+    // clear it if found set 
+    if (HW_GPT_SR.B.ROV)
+    {
+        HW_GPT_SR_WR(BM_GPT_SR_ROV);
+        return kGPTRollover;
+    }
+
+    // return the read value before the bit was cleared 
+    return 0;
+}
+
+uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val)
+{
+    // get the capture status bit 
+    flag &= kGPTInputCapture1 | kGPTInputCapture2;
+    uint32_t status_register = HW_GPT_SR_RD() & flag;
+    
+    // Read the captured timer value.
+    if (capture_val)
+    {
+        if (status_register == kGPTInputCapture1)
+        {
+            *(uint32_t *) capture_val = HW_GPT_ICR1.B.CAPT;
+        }
+        else if (status_register == kGPTInputCapture2)
+        {
+            *(uint32_t *) capture_val = HW_GPT_ICR2.B.CAPT;
+        }
+    }
+    
+    // Clear the flag.
+    HW_GPT_SR_WR(status_register);
+
+    // return the read value before the bit was cleared 
+    return status_register;
+}
+
+void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode)
+{
+    // set the new input mode 
+    switch (cap_input)
+    {
+        case kGPTInputCapture1:
+            HW_GPT_CR.B.IM1 = cap_input_mode;
+            break;
+            
+        case kGPTInputCapture2:
+            HW_GPT_CR.B.IM2 = cap_input_mode;
+            break;
+    }
+}
+
+uint32_t gpt_get_compare_event(uint8_t flag)
+{
+    // get the active compare flags 
+    flag &= kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3;
+    uint32_t status_register = HW_GPT_SR_RD() & flag;
+    
+    // clear flags which are active 
+    if (status_register)
+    {
+        HW_GPT_SR_WR(status_register);
+    }
+
+    // return the read value before the flags were cleared
+    return status_register;
+}
+
+void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value)
+{
+    // set the value to compare with 
+    switch (cmp_output)
+    {
+        case kGPTOutputCompare1:
+            BW_GPT_CR_OM1(cmp_output_mode);
+            HW_GPT_OCR1_WR(cmp_value);
+            break;
+
+        case kGPTOutputCompare2:
+            BW_GPT_CR_OM2(cmp_output_mode);
+            HW_GPT_OCR2_WR(cmp_value);
+            break;
+
+        case kGPTOutputCompare3:
+            BW_GPT_CR_OM3(cmp_output_mode);
+            HW_GPT_OCR3_WR(cmp_value);
+            break;
+    }
+}
+
+void gpt_counter_disable(void)
+{
+    // disable the counter 
+    HW_GPT_CR.B.EN = 0;
+
+    // ensure to leave the counter in a proper state by disabling the interrupt sources
+    HW_GPT_IR_WR(0);
+    
+    // and by clearing possible remaining events 
+    gpt_clear_all_events();
+}
+
+void gpt_counter_enable(uint32_t irq_mode)
+{
+    // ensure to start the counter in a proper state by clearing possible remaining events
+    gpt_clear_all_events();
+
+    // enable the interrupts or clear the register for polling 
+    HW_GPT_IR_WR(irq_mode & kGPTAllEvents);
+
+    // finally, enable the counter 
+    HW_GPT_CR.B.EN = 1;
+}
+
+void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt)
+{
+    uint32_t irq_id = IMX_INT_GPT;
+
+    if (enableIt)
+    {    
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ 
+        enable_interrupt(irq_id, CPU_0, 0);
+    }
+    else
+    {
+        // disable the IRQ 
+        disable_interrupt(irq_id, CPU_0);
+    }
+}
+
+void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode)
+{
+    uint32_t control_reg_tmp = 0;
+    uint32_t base = GPT_BASE_ADDR;
+
+    // enable the source clocks to the GPT port 
+    clock_gating_config(base, CLOCK_ON);
+
+    // start with a known state by disabling and reseting the module 
+    HW_GPT_CR_WR(BM_GPT_CR_SWR);
+    
+    // wait for the reset to complete 
+    while (HW_GPT_CR.B.SWR != 0) ;
+
+    // set the reference source clock for the counter 
+    if (clock_src == CLKSRC_CKIL)
+    {
+        // CKIL source is 0x4 for GPT but 0x3 for EPIT
+        clock_src++;
+    }
+    control_reg_tmp |= BF_GPT_CR_CLKSRC(clock_src);
+
+    // the prescaler can be changed at any time, and 
+    // this affects the output clock immediately
+    HW_GPT_PR_WR(BF_GPT_PR_PRESCALER(prescaler - 1));
+
+    // set the counter mode 
+    control_reg_tmp |= BF_GPT_CR_FRR(counter_mode);
+
+    // set behavior for low power mode 
+    if (low_power_mode & WAIT_MODE_EN)
+    {
+        control_reg_tmp |= BM_GPT_CR_WAITEN;
+    }
+    if (low_power_mode & STOP_MODE_EN)
+    {
+        control_reg_tmp |= BM_GPT_CR_STOPEN;
+    }
+
+    // specify from where the counter starts to count when enabled 
+    // this code makes it start from 0 
+    control_reg_tmp |= BM_GPT_CR_ENMOD;
+
+    // finally write the control register 
+    HW_GPT_CR_WR(control_reg_tmp);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_i2c.c

@@ -0,0 +1,540 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file imx_i2c.c
+ * @brief Main driver for the I2C controller. It initializes the controller
+ *        and handles the master mode.
+ *
+ * @ingroup diag_i2c
+ */
+
+#include "sdk.h"
+#include "imx_i2c.h"
+#include "imx_i2c_internal.h"
+#include "registers/regsi2c.h"
+#include "ccm_pll.h"
+#include "interrupt.h"
+
+//! Set this macro to 1 to enable tracing of data send and receive.
+#define TRACE_I2C 0
+
+//! @brief Get the irq id of I2C by instance number.
+//! @param x I2C instance number, from 1 through 3.
+#define I2C_IRQS(x) ( (x) == HW_I2C1 ? IMX_INT_I2C1 : (x) == HW_I2C2 ? IMX_INT_I2C2 : (x) == HW_I2C3 ? IMX_INT_I2C3 : 0xFFFFFFFF)
+
+////////////////////////////////////////////////////////////////////////////////
+// Constants
+////////////////////////////////////////////////////////////////////////////////
+
+static const uint16_t i2c_freq_div[50][2] = {
+        { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
+        { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
+        { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
+        { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
+        { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
+        { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
+        { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
+        { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
+        { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
+        { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
+        { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
+        { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
+        { 3072, 0x1E }, { 3840, 0x1F }
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static inline int is_bus_free(unsigned int instance);
+static int wait_till_busy(uint32_t instance);
+static inline void imx_send_stop(unsigned int instance);
+static int wait_op_done(uint32_t instance, int is_tx);
+static int tx_byte(uint8_t * data, uint32_t instance);
+static int rx_bytes(uint8_t * data, uint32_t instance, int sz);
+static void set_i2c_clock(uint32_t instance, uint32_t baud);
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+unsigned i2c_get_request_instance(const imx_i2c_request_t * rq)
+{
+    // First see if there device info is set.
+    if (rq->device)
+    {
+        // Use the instance number in the device info.
+        return rq->device->port;
+    }
+    
+    // Check if the ctl_addr is within the range of instances.
+    if (rq->ctl_addr >= 1 && rq->ctl_addr <= HW_I2C_INSTANCE_COUNT)
+    {
+        // Valid instance number, so use it directly.
+        return rq->ctl_addr;
+    }
+    else
+    {
+        // Not a valid instance, so treat it as a base address.
+        return REGS_I2C_INSTANCE(rq->ctl_addr);
+    }
+}
+
+/*!
+ * @brief Loop status register for IBB to go 0.
+ *
+ * The loop also breaks on max number of iterations.
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static inline int is_bus_free(unsigned int instance)
+{
+    int i = WAIT_RXAK_LOOPS;
+
+    while (HW_I2C_I2SR(instance).B.IBB && (--i > 0));
+
+    if (i <= 0) {
+        debug_printf("Error: I2C Bus not free!\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+/*!
+ * @brief Loop status register for IBB to go 1.
+ *
+ * It breaks the loop if there's an arbitration lost occurred or the maximum
+ * number of iterations has been reached.
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int wait_till_busy(uint32_t instance)
+{
+    int i = WAIT_BUSY_LOOPS;
+
+    while (!HW_I2C_I2SR(instance).B.IBB && (--i > 0)) {
+        if (HW_I2C_I2SR(instance).B.IAL) {
+            debug_printf("Error: arbitration lost!\n");
+            return -1;
+        }
+    }
+
+    if (i <= 0) {
+        debug_printf("I2C Error: timeout in %s; %d\n", __FUNCTION__, __LINE__);
+        return -1;
+    }
+
+    return 0;
+}
+
+/*!
+ * Generates a STOP signal, called by rx and tx routines
+ *
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  none
+ */
+static inline void imx_send_stop(unsigned int instance)
+{
+    HW_I2C_I2CR(instance).B.MSTA = 0;
+}
+
+/*!
+ * @brief Wait for operation done.
+ *
+ * This function loops until we get an interrupt. On timeout it returns -1.
+ * It reports arbitration lost if IAL bit of I2SR register is set
+ * Clears the interrupt
+ * If operation is transfer byte function will make sure we received an ack
+ *
+ * @param instance Instance number of the I2C module.
+ * @param   is_tx       Pass 1 for transfering, 0 for receiving 
+ *
+ * @return  0 if successful; negative integer otherwise
+ */
+static int wait_op_done(uint32_t instance, int is_tx)
+{
+    hw_i2c_i2sr_t v;
+    int i = WAIT_RXAK_LOOPS;
+
+    // Loop until we get an interrupt 
+    do {
+        v.U = HW_I2C_I2SR_RD(instance);
+    } while (!v.B.IIF && (--i > 0));
+
+    // If timeout error occurred return error 
+    if (i <= 0) {
+        debug_printf("I2C Error: timeout unexpected\n");
+        return -1;
+    }
+
+    // Clear the interrupts 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // Check for arbitration lost 
+    if (v.B.IAL) {
+        debug_printf("Error %d: Arbitration lost\n", __LINE__);
+        return ERR_ARB_LOST;
+    }
+
+    // Check for ACK received in transmit mode 
+    if (is_tx) {
+        if (v.B.RXAK) {
+            // No ACK received, generate STOP by clearing MSTA bit 
+            debug_printf("Error %d: no ack received\n", __LINE__);
+            
+            // Generate a STOP signal 
+            imx_send_stop(instance);
+            return ERR_NO_ACK;
+        }
+    }
+
+    return 0;
+}
+
+/*!
+ * @brief Implements a loop to send a byte to I2C slave.
+ *
+ * For master transmit. Always expect a RXAK signal to be set!
+ *
+ * @param   data        return buffer for data
+ * @param instance Instance number of the I2C module.
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int tx_byte(uint8_t * data, uint32_t instance)
+{
+#if TRACE_I2C
+    debug_printf("%s(data=0x%02x, instance=%d)\n", __FUNCTION__, *data, instance);
+#endif // TRACE_I2C
+
+    // clear both IAL and IIF bits 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // write to data register 
+    HW_I2C_I2DR_WR(instance, *data);
+
+    // wait for transfer of byte to complete 
+    return wait_op_done(instance, 1);
+}
+
+/*!
+ * @brief Implements a loop to receive bytes from I2C slave.
+ *
+ * For master receive.
+ *
+ * @param   data        return buffer for data
+ * @param instance Instance number of the I2C module.
+ * @param   sz          number of bytes to receive
+ *
+ * @return  0 if successful; -1 otherwise
+ */
+static int rx_bytes(uint8_t * data, uint32_t instance, int sz)
+{
+    int i;
+
+    for (i = 0; sz > 0; sz--, i++) {
+        if (wait_op_done(instance, 0) != 0) {
+            return -1;
+        }
+
+        // the next two if-statements setup for the next read control register value 
+        if (sz == 1) {
+            // last byte --> generate STOP 
+            // generate STOP by clearing MSTA bit 
+            imx_send_stop(instance);
+        }
+
+        if (sz == 2) {
+            // 2nd last byte --> set TXAK bit to NOT generate ACK 
+            HW_I2C_I2CR(instance).B.TXAK = 1;
+        }
+        
+        // read the true data 
+        data[i] = HW_I2C_I2DR_RD(instance);
+#if TRACE_I2C
+
+        debug_printf("OK 0x%02x\n", data[i]);
+#endif // TRACE_I2C
+    }
+
+    return 0;
+}
+
+static void set_i2c_clock(uint32_t instance, uint32_t baud)
+{
+    // Adjust the divider to get the closest SCL frequency to baud rate 
+    uint32_t src_clk = get_main_clock(IPG_PER_CLK);
+    uint32_t divider = src_clk / baud;
+    uint8_t index = 0;
+    
+    if (divider < i2c_freq_div[0][0])
+    {
+        divider = i2c_freq_div[0][0];
+        index = 0;
+        debug_printf("Warning :can't find a smaller divider than %d.\n", divider);
+        debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
+    }
+    else if (divider > i2c_freq_div[49][0])
+    {
+        divider = i2c_freq_div[49][0];
+        index = 49;
+        debug_printf("Warning: can't find a bigger divider than %d.\n", divider);
+        debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
+    }
+    else
+    {
+        for (index = 0; i2c_freq_div[index][0] < divider; index++);
+        divider = i2c_freq_div[index][0];
+    }
+    
+    HW_I2C_IFDR_WR(instance, BF_I2C_IFDR_IC(i2c_freq_div[index][1]));
+}
+
+int i2c_xfer(const imx_i2c_request_t *rq, int dir)
+{
+    uint32_t reg;
+    uint32_t ret = 0;
+    uint16_t i2cr;
+    uint8_t i;
+    uint8_t data;
+    uint32_t instance = i2c_get_request_instance(rq);
+    uint8_t address = (rq->device ? rq->device->address : rq->dev_addr) << 1;
+
+    if (rq->buffer_sz == 0 || rq->buffer == NULL) {
+        debug_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n",
+               rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer);
+        return ERR_INVALID_REQUEST;
+    }
+
+    // clear the status register 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // enable the I2C controller 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
+
+    // Check if bus is free, if not return error 
+    if (is_bus_free(instance) != 0) {
+        return -1;
+    }
+    
+    // If the request has device info attached and it has a non-zero bit rate, then
+    // change the clock to the specified rate.
+    if (rq->device && rq->device->freq)
+    {
+        set_i2c_clock(instance, rq->device->freq);
+    }
+
+    // Step 1: Select master mode, assert START signal and also indicate TX mode 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN | BM_I2C_I2CR_MSTA | BM_I2C_I2CR_MTX);
+
+    // make sure bus is busy after the START signal 
+    if (wait_till_busy(instance) != 0) {
+        debug_printf("1\n");
+        return -1;
+    }
+    
+    // Step 2: send slave address + read/write at the LSB 
+    data = address | I2C_WRITE;
+
+    if ((ret = tx_byte(&data, instance)) != 0) {
+        debug_printf("START TX ERR %d\n", ret);
+
+        if (ret == ERR_NO_ACK) {
+            return ERR_NO_ACK_ON_START;
+        } else {
+            return ret;
+        }
+    }
+    
+    // Step 3: send I2C device register address 
+    if (rq->reg_addr_sz > 4) {
+        debug_printf("Warning register address size %d should less than 4\n", rq->reg_addr_sz);
+        return ERR_INVALID_REQUEST;
+    }
+
+    reg = rq->reg_addr;
+
+    for (i = 0; i < rq->reg_addr_sz; i++, reg >>= 8) {
+        data = reg & 0xFF;
+        
+#if TRACE_I2C
+        debug_printf("sending I2C=%d device register: data=0x%x, byte %d\n", instance, data, i);
+#endif // TRACE_I2C
+
+        if (tx_byte(&data, instance) != 0) {
+            return -1;
+        }
+    }
+
+    // Step 4: read/write data 
+    if (dir == I2C_READ) {
+        // do repeat-start 
+        HW_I2C_I2CR(instance).B.RSTA = 1;
+
+        // make sure bus is busy after the REPEATED START signal 
+        if (wait_till_busy(instance) != 0) {
+            return ERR_TX;
+        }
+        
+        // send slave address again, but indicate read operation 
+        data = address | I2C_READ;
+
+        if (tx_byte(&data, instance) != 0) {
+            return -1;
+        }
+
+        // change to receive mode 
+        i2cr = HW_I2C_I2CR_RD(instance) & ~BM_I2C_I2CR_MTX;
+        
+        // if only one byte to read, make sure don't send ack 
+        if (rq->buffer_sz == 1) {
+            i2cr |= BM_I2C_I2CR_TXAK;
+        }
+        HW_I2C_I2CR_WR(instance, i2cr);
+
+        // dummy read 
+        data = HW_I2C_I2DR_RD(instance);
+
+        // now reading ... 
+        if (rx_bytes(rq->buffer, instance, rq->buffer_sz) != 0) {
+            return -1;
+        }
+    } else {
+        // I2C_WRITE 
+        for (i = 0; i < rq->buffer_sz; i++) {
+            // send device register value 
+            data = rq->buffer[i];
+
+            if ((ret = tx_byte(&data, instance)) != 0) {
+                break;
+            }
+        }
+    }
+
+    // generate STOP by clearing MSTA bit 
+    imx_send_stop(instance);
+
+    // Check if bus is free, if not return error 
+    if (is_bus_free(instance) != 0) {
+        debug_printf("WARNING: bus is not free\n");
+    }
+    
+    // disable the controller 
+    HW_I2C_I2CR_WR(instance, 0);
+
+    return ret;
+}
+
+int i2c_read(const imx_i2c_request_t *rq)
+{
+    return i2c_xfer(rq, I2C_READ);
+}
+
+int i2c_write(const imx_i2c_request_t *rq)
+{
+    return i2c_xfer(rq, I2C_WRITE);
+}
+
+void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state)
+{
+    uint32_t irq_id = I2C_IRQS(instance);
+
+    if (state) {
+        // register the IRQ sub-routine 
+        register_interrupt_routine(irq_id, irq_subroutine);
+        
+        // enable the IRQ at the ARM core level 
+        enable_interrupt(irq_id, CPU_0, 0);
+        
+        // clear the status register 
+        HW_I2C_I2SR_WR(instance, 0);
+        
+        // and enable the interrupts in the I2C controller 
+        HW_I2C_I2CR(instance).B.IIEN = 1;
+    } else {
+        // disable the IRQ at the ARM core level 
+        disable_interrupt(irq_id, CPU_0);
+        
+        // and disable the interrupts in the I2C controller 
+        HW_I2C_I2CR(instance).B.IIEN = 0;
+        
+        // clear the status register 
+        HW_I2C_I2SR_WR(instance, 0);
+    }
+}
+
+int i2c_init(uint32_t base, uint32_t baud)
+{
+    int instance;
+    
+    // Accept either an instance or base address for the base param.
+    if (base >= 1 && base <= HW_I2C_INSTANCE_COUNT)
+    {
+        instance = base;
+    }
+    else
+    {
+        instance = REGS_I2C_INSTANCE(base);
+    }
+    
+    // enable the source clocks to the I2C port 
+    clock_gating_config(REGS_I2C_BASE(instance), CLOCK_ON);
+
+    // Set iomux configuration 
+    i2c_iomux_config(instance);
+
+    // reset I2C 
+    HW_I2C_I2CR_WR(instance, 0);
+
+    // Set clock.
+    set_i2c_clock(instance, baud);
+
+    // set an I2C slave address 
+    HW_I2C_IADR_WR(instance, IMX6_DEFAULT_SLAVE_ID);
+
+    // clear the status register 
+    HW_I2C_I2SR_WR(instance, 0);
+
+    // enable the I2C controller 
+    HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
+
+    return 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_i2c_internal.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IMX_I2C_INTERNAL_H__
+#define __IMX_I2C_INTERNAL_H__
+
+#include "imx_i2c.h"
+#include "registers/regsi2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! Max number of operations to wait to receive ack.
+#define WAIT_RXAK_LOOPS     1000000
+
+//! Max number of operations to wait until busy.
+#define WAIT_BUSY_LOOPS     100000
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Setup I2C interrupt.
+ *
+ * It enables or disables the related HW module interrupt, and attached the related
+ * sub-routine into the vector table.
+ *
+ * @param   port Pointer to the I2C module structure.
+ * @param   state Enable or disable the interrupt. Pass true to enable.
+ */
+void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state);
+
+/*!
+ * @brief I2C interrupt routine for slave transfers.
+ */
+void i2c_slave_interrupt_routine(void);
+
+//! @brief Returns the I2C controller instance from a request struct.
+unsigned i2c_get_request_instance(const imx_i2c_request_t * rq);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // __IMX_I2C_INTERNAL_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/drivers/imx_timer.c

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file timer.c
+ * @brief Basic timer functions
+ *
+ * @ingroup diag_timer
+ */
+
+#include <assert.h>
+
+#include "imx_timer.h"
+#include "sdk.h"
+#include "epit.h"
+#include "registers/regsarmglobaltimer.h"
+#include "ccm_pll.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Prototypes
+////////////////////////////////////////////////////////////////////////////////
+
+static void time_init_global_timer();
+
+////////////////////////////////////////////////////////////////////////////////
+// Variables
+////////////////////////////////////////////////////////////////////////////////
+
+uint32_t g_microsecondTimerMultiple=8;
+
+////////////////////////////////////////////////////////////////////////////////
+// Code
+////////////////////////////////////////////////////////////////////////////////
+
+void hal_delay_us(uint32_t usecs)
+{
+    uint32_t instance = g_system_timer_port;
+    if (usecs == 0) {
+        return;
+    }
+
+    /* enable the counter first */
+    epit_counter_enable(instance, usecs, POLLING_MODE);
+    
+    /* wait for the compare event */
+    while (!epit_get_compare_event(instance)) ;
+    
+    /* disable the counter to save power */
+    epit_counter_disable(instance);
+}
+
+void system_time_init(void)
+{
+    uint32_t freq;
+    // Init microsecond tick counter.
+    time_init_global_timer();
+    
+    /* EPIT1 is used for the delay function */
+    /* Initialize the EPIT timer used for system time functions */
+    /* typical IPG_CLK is in MHz, so divide it to get a reference
+       clock of 1MHz => 1us per count */
+    freq = get_main_clock(IPG_CLK);
+    epit_init(g_system_timer_port, CLKSRC_IPG_CLK, freq / 1000000,
+              SET_AND_FORGET, 1000, WAIT_MODE_EN | STOP_MODE_EN);
+}
+
+#if defined(CHIP_MX6UL)
+//! Init the ARM global timer to a microsecond-frequency clock.
+void time_init_global_timer()
+{
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0;
+    
+    HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTER_HI_WR(0);
+    HW_ARMGLOBALTIMER_COUNTER_LO_WR(0);
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+}
+
+uint64_t time_get_microseconds()
+{
+    // First read upper.
+    uint32_t upper = HW_ARMGLOBALTIMER_COUNTER_HI_RD();
+    uint32_t lower = HW_ARMGLOBALTIMER_COUNTER_LO_RD();
+
+    return (((uint64_t)upper << 32) | (uint64_t)lower)/8;
+}
+#else
+//! Init the ARM global timer to a microsecond-frequency clock.
+void time_init_global_timer()
+{
+    // The ARM private peripheral clock is half the CPU clock.
+    uint32_t periphClock = get_main_clock(CPU_CLK) / 2;
+    uint32_t prescaler = (periphClock / 1000000) - 1;
+    
+    // Divide down the prescaler until it fits into 8 bits. We add up the number of ticks
+    // it takes to equal a microsecond interval.
+    g_microsecondTimerMultiple = 1;
+    while (prescaler > 0xff)
+    {
+        prescaler /= 2;
+        ++g_microsecondTimerMultiple;
+    }
+    
+    // Make sure the timer is off.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0;
+    
+    // Clear counter.
+    HW_ARMGLOBALTIMER_COUNTERn_WR(0, 0);
+    HW_ARMGLOBALTIMER_COUNTERn_WR(1, 0);
+    
+    // Set prescaler and clear other flags.
+    HW_ARMGLOBALTIMER_CONTROL_WR(BF_ARMGLOBALTIMER_CONTROL_PRESCALER(prescaler));
+    
+    // Now turn on the timer.
+    HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1;
+}
+
+uint64_t time_get_microseconds()
+{
+    // First read upper.
+    uint32_t upper = HW_ARMGLOBALTIMER_COUNTERn_RD(1);
+    uint32_t lower;
+    
+    while (true)
+    {
+        // Read lower.
+        lower = HW_ARMGLOBALTIMER_COUNTERn_RD(0);
+        
+        // Read upper again.
+        uint32_t newUpper = HW_ARMGLOBALTIMER_COUNTERn_RD(1);
+        
+        // If the first and second read of the upper bits are the same, then return.
+        if (newUpper == upper)
+        {
+            return (((uint64_t)upper << 32) | (uint64_t)lower) / g_microsecondTimerMultiple;
+        }
+        
+        // Otherwise, start over again.
+        upper = newUpper;
+    }
+    
+    return 0;
+}
+#endif
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////
+

bsp/imx6ul/platform/drivers/imx_uart.c

@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file imx_uart.c
+ * @brief UART driver.
+
+ * @ingroup diag_uart
+ */
+
+#include "sdk.h"
+#include "registers/regsuart.h"
+#include "imx_uart.h"
+#include "ccm_pll.h"
+#include "interrupt.h"
+
+#define UART_UFCR_RFDIV    BF_UART_UFCR_RFDIV(4) 
+//#define UART_UFCR_RFDIV     UART_UFCR_RFDIV_4
+//#define UART_UFCR_RFDIV     UART_UFCR_RFDIV_7
+
+uint32_t uart_get_reffreq(uint32_t instance)
+{
+    uint32_t div = UART_UFCR_RFDIV;
+    uint32_t ret = 0;
+    uint32_t freq = get_peri_clock(UART_MODULE_CLK(instance));
+
+    if (div == BF_UART_UFCR_RFDIV(4))
+        ret = freq / 2;
+    else if (div == BF_UART_UFCR_RFDIV(2))
+        ret = freq / 4;
+    else if (div == BF_UART_UFCR_RFDIV(6))
+        ret = freq / 7;
+
+    return ret;
+}
+
+uint8_t uart_putchar(uint32_t instance, uint8_t * ch)
+{
+    /* Wait for Tx FIFO not full */
+    while (HW_UART_UTS(instance).B.TXFULL);
+
+    HW_UART_UTXD_WR(instance, *ch);
+
+    return *ch;
+}
+
+uint8_t uart_getchar(uint32_t instance)
+{
+    uint32_t read_data;
+
+    /* If Rx FIFO has no data ready */
+    if (!(HW_UART_USR2(instance).B.RDR))
+        return NONE_CHAR;
+
+    read_data = HW_UART_URXD_RD(instance); 
+
+    /* If error are detected */
+    if (read_data & 0x7C00)
+        return NONE_CHAR;
+
+    return (uint8_t) read_data;
+}
+
+void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level,
+                        uint8_t service_mode)
+{
+    if (fifo == TX_FIFO) {
+        /* Configure the TX_FIFO trigger level */
+        HW_UART_UFCR_CLR(instance,BM_UART_UFCR_TXTL);
+        HW_UART_UFCR_SET(instance, BF_UART_UFCR_TXTL(trigger_level)); 
+        /* Configure the TX_FIFO service mode */
+        /* Default mode is polling: IRQ and DMA requests are disabled */
+        HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_TRDYEN | BM_UART_UCR1_TXDMAEN));
+        if (service_mode == DMA_MODE)
+           HW_UART_UCR1_SET(instance,BM_UART_UCR1_TXDMAEN);
+        else if (service_mode == IRQ_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_TRDYEN); 
+    } else {                    /* fifo = RX_FIFO */
+        /* Configure the RX_FIFO trigger level */
+         HW_UART_UFCR_CLR(instance,BM_UART_UFCR_RXTL);
+        HW_UART_UFCR_SET(instance,BF_UART_UFCR_RXTL(trigger_level)); 
+        /* Configure the RX_FIFO service mode */
+        /* Default mode is polling: IRQ and DMA requests are disabled */
+        HW_UART_UCR1_CLR(instance,(BM_UART_UCR1_RRDYEN | BM_UART_UCR1_RXDMAEN)); 
+        if (service_mode == DMA_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_RXDMAEN); 
+        else if (service_mode == IRQ_MODE)
+            HW_UART_UCR1_SET(instance,BM_UART_UCR1_RRDYEN); 
+    }
+}
+
+void uart_set_loopback_mode(uint32_t instance, uint8_t state)
+{
+    if (state == TRUE)
+	HW_UART_UTS_SET(instance, BM_UART_UTS_LOOP);
+    else
+        HW_UART_UTS_CLR(instance, BM_UART_UTS_LOOP);
+}
+
+void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state)
+{
+    uint32_t irq_id = UART_IRQS(instance);
+
+    if (state == TRUE) {
+        /* register the IRQ sub-routine */
+        register_interrupt_routine(irq_id, irq_subroutine);
+        /* enable the IRQ */
+        enable_interrupt(irq_id, CPU_0, 0);
+    } else
+        /* disable the IRQ */
+        disable_interrupt(irq_id, CPU_0);
+}
+
+void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,
+               uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol)
+{
+    uint32_t base = REGS_UART_BASE(instance);
+
+   /* configure the I/O for the port */
+    uart_iomux_config(instance);
+
+    /* enable the source clocks to the UART port */
+    clock_gating_config(base, CLOCK_ON);
+
+    /* Wait for UART to finish transmitting before changing the configuration */
+    while (!(HW_UART_UTS(instance).B.TXEMPTY)) ;
+
+    /* Disable UART */
+    HW_UART_UCR1_CLR(instance,BM_UART_UCR1_UARTEN );
+
+    /* Configure FIFOs trigger level to half-full and half-empty */
+    HW_UART_UFCR_WR(instance, BF_UART_UFCR_RXTL(16) | UART_UFCR_RFDIV | BF_UART_UFCR_TXTL(16)); 
+
+    /* Setup One Millisecond timer */
+    HW_UART_ONEMS_WR(instance, uart_get_reffreq(instance) / 1000);
+
+    /* Set parity */
+    if (parity == PARITY_NONE)
+        HW_UART_UCR2_CLR(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE)); 
+    else if (parity == PARITY_ODD)
+        HW_UART_UCR2_SET(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
+    else {                      /* parity == PARITY_EVEN */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_PREN);
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_PROE);
+    }
+
+    /* Set stop bit */
+    if (stopbits == STOPBITS_ONE)
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_STPB);
+    else                        /* stopbits == STOPBITS_TWO */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_STPB);
+
+    /* Set data size */
+    if (datasize == EIGHTBITS)
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_WS);
+    else                        /* stopbits == STOPBITS_TWO */
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_WS);
+
+    /* Configure the flow control */
+    if (flowcontrol == FLOWCTRL_ON) {
+        /* transmit done when RTS asserted */
+        HW_UART_UCR2_CLR(instance, BM_UART_UCR2_IRTS );
+        /* CTS controlled by the receiver */
+        HW_UART_UCR2_SET(instance, BM_UART_UCR2_CTSC );
+    } else {                    /* flowcontrol == FLOWCTRL_OFF */
+        /* Ignore RTS */
+        HW_UART_UCR2_SET(instance,  BM_UART_UCR2_IRTS);
+        /* CTS controlled by the CTS bit */
+        HW_UART_UCR2_CLR(instance,  BM_UART_UCR2_CTSC);
+    }
+
+    /* the reference manual says that this bit must always be set */
+    HW_UART_UCR3_SET(instance,  BM_UART_UCR3_RXDMUXSEL);
+
+    /* Enable UART */
+    HW_UART_UCR1_SET(instance, BM_UART_UCR1_UARTEN);
+
+    /* Enable FIFOs and does software reset to clear status flags, reset
+       the transmit and receive state machine, and reset the FIFOs */
+    HW_UART_UCR2_SET(instance, BM_UART_UCR2_TXEN | BM_UART_UCR2_RXEN | BM_UART_UCR2_SRST);
+
+    /* Set the numerator value minus one of the BRM ratio */
+    HW_UART_UBIR_WR(instance, (baudrate / 100) - 1);
+
+    /* Set the denominator value minus one of the BRM ratio */
+    HW_UART_UBMR_WR(instance,  ((uart_get_reffreq(instance) / 1600) - 1));
+
+    /* Optional: prevent the UART to enter debug state. Useful when debugging
+       the code with a JTAG and without active IRQ */
+    HW_UART_UTS_SET(instance, BM_UART_UTS_DBGEN);
+}
+

bsp/imx6ul/platform/include/epit.h

@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_epit
+//! @{
+
+/*!
+ * @file epit.h
+ * @brief EPIT driver public interface.
+ */
+
+#ifndef __EPIT_H__
+#define __EPIT_H__
+
+#include "imx_timer.h"
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Free running reload mode.
+//!
+//! When the counter reaches zero it rolls over to 0xFFFF_FFFF.
+#define FREE_RUNNING    0
+
+//! @brief Set and forget reload mode.
+//!
+//! When the counter reaches zero it reloads from the modulus register.
+#define SET_AND_FORGET  1
+
+//! @brief Pass to epit_counter_enable() to enable interrupts.
+#define IRQ_MODE 1
+
+//! @brief Get the irq id of RPIT by instance number.
+//! @param x I2C instance number, from 1 through 2.
+#define EPIT_IRQS(x) ( (x) == HW_EPIT1 ? IMX_INT_EPIT1 : (x) == HW_EPIT2 ? IMX_INT_EPIT2 : 0xFFFFFFFF)
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize the EPIT timer.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK,
+ *                      CLKSRC_PER_CLK, CLKSRC_CKIL.
+ * @param   prescaler Prescaler of source clock from 1 to 4096.
+ * @param   reload_mode Counter reload mode: FREE_RUNNING or SET_AND_FORGET.
+ * @param   load_val Load value from where the counter start.
+ * @param   low_power_mode Low power during which the timer is enabled:
+ *                           WAIT_MODE_EN and/or STOP_MODE_EN.
+ */
+void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
+               uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode);
+
+/*!
+ * @brief Setup EPIT interrupt.
+ *
+ * It enables or disables the related HW module interrupt, and attached the related sub-routine
+ * into the vector table.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   irq_subroutine the EPIT interrupt interrupt routine.
+ * @param   enableIt True to enable the interrupt, false to disable.
+ */
+void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt);
+
+/*!
+ * @brief Enable the EPIT module. 
+ *
+ * Used typically when the epit_init is done, and other interrupt related settings are ready.
+ *
+ * In interrupt mode, when the interrupt fires you should call epit_get_compare_event() to
+ * clear the compare flag.
+ *
+ * @param   instance the EPIT instance number.
+ * @param   load_val Load value from where the counter starts.
+ * @param   irq_mode Interrupt mode: IRQ_MODE or POLLING_MODE.
+ */
+void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode);
+
+/*!
+ * @brief Disable the counter.
+ *
+ * It saves energy when not used.
+ *
+ * @param   instance the EPIT instance number.
+ */
+void epit_counter_disable(uint32_t instance);
+
+/*!
+ * @brief Get the output compare status flag and clear it if set.
+ * 
+ * This function can typically be used for polling method, but
+ * is also used to clear the status compare flag in IRQ mode.
+ *
+ * @param   instance the EPIT instance number.
+ * @return  Value of the compare event flag.
+ */
+uint32_t epit_get_compare_event(uint32_t instance);
+
+/*!
+ * @brief Set the output compare register.
+ * 
+ *
+ * @param   instance the EPIT instance number.
+ * @param   Value of the compare register.
+ */
+void epit_set_compare_event(uint32_t instance, uint32_t compare_val);
+
+/*!
+ * @brief Get the counter value.
+ * 
+ *
+ * @param   instance the EPIT instance number.
+ * @return  Value of the counter register.
+ */
+uint32_t epit_get_counter_value(uint32_t instance);
+
+/*!
+ * @brief Reload the counter with a known value.
+ *
+ * @param instance the EPIT instance number.
+ * @param load_val Value loaded into the timer counter.
+ */
+void epit_reload_counter(uint32_t instance, uint32_t load_val);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif //__EPIT_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/gic.h

@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __GIC_H__
+#define __GIC_H__
+
+#include "sdk_types.h"
+
+//! @addtogroup gic
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Options for sending a software generated interrupt.
+//!
+//! These options are used for the @a filter_list parameter of the gic_send_sgi()
+//! function. They control how to select which CPUs that the interrupt is
+//! sent to.
+enum _gicd_sgi_filter
+{
+    //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
+    kGicSgiFilter_UseTargetList = 0,
+    
+    //! Forward the interrupt to all CPU interfaces except that of the processor that requested
+    //! the interrupt.
+    kGicSgiFilter_AllOtherCPUs = 1,
+    
+    //! Forward the interrupt only to the CPU interface of the processor that requested the
+    //! interrupt.
+    kGicSgiFilter_OnlyThisCPU = 2
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @name Initialization
+//@{
+//! @brief Init interrupt handling.
+//!
+//! This function is intended to be called only by the primary CPU init code, so it will
+//! only be called once during system bootup.
+//!
+//! Also inits the current CPU. You don't need to call gic_init_cpu() separately.
+//!
+//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts
+//!     that were pending are cleared, and all interrupts are made secure (group 0).
+void gic_init(void);
+
+//! @brief Init the current CPU's GIC interface.
+//!
+//! @post Enables the CPU interface and sets the priority mask to 255. Interrupt preemption
+//!     is disabled by setting the Binary Point to a value of 7.
+void gic_init_cpu(void);
+//@}
+
+//! @name GIC Interrupt Distributor Functions
+//@{
+//! @brief Enable or disable the GIC Distributor.
+//!
+//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure
+//! (group 1) interrupts to the CPU interfaces.
+//!
+//! @param enableIt Pass true to enable or false to disable.
+void gic_enable(bool enableIt);
+
+//! @brief Set the security mode for an interrupt.
+//!
+//! @param irqID The interrupt number.
+//! @param isSecure Whether the interrupt is taken to secure mode.
+void gic_set_irq_security(uint32_t irqID, bool isSecure);
+
+//! @brief Enable or disable an interrupt.
+//!
+//! @param irqID The number of the interrupt to control.
+//! @param isEnabled Pass true to enable or false to disable.
+void gic_enable_irq(uint32_t irqID, bool isEnabled);
+
+//! @brief Set whether a CPU will receive a particular interrupt.
+//!
+//! @param irqID The interrupt number.
+//! @param cpuNumber The CPU number. The first CPU core is 0.
+//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable
+//!     or false to disable.
+void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt);
+
+//! @brief Set an interrupt's priority.
+//!
+//! @param irq_id The interrupt number.
+//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with
+//!     0 being the highest priority.
+void gic_set_irq_priority(uint32_t irq_id, uint32_t priority);
+
+//! @brief Send a software generated interrupt to a specific CPU.
+//!
+//! @param irq_id The interrupt number to send.
+//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded.
+//!     Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt
+//!     will not be forwarded to any CPUs. This parameter is only used if @a filter_list
+//!     is set to #kGicSgiFilter_UseTargetList.
+//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected
+//!     option determines which CPUs the interrupt will be sent to. If the value
+//!     is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used.
+void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list);
+//@}
+
+//! @name GIC CPU Interface Functions
+//@{
+//! @brief Enable or disable the interface to the GIC for the current CPU.
+//!
+//! @param enableIt Pass true to enable or false to disable.
+void gic_cpu_enable(bool enableIt);
+
+//! @brief Set the mask of which interrupt priorities the CPU will receive.
+//!
+//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to
+//!     allow all priority interrupts to signal the CPU.
+void gic_set_cpu_priority_mask(uint32_t priority);
+
+//! @brief Acknowledge starting of interrupt handling and get the interrupt number.
+//!
+//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC
+//! that you are starting to handle an interupt, and returns the number of the interrupt you
+//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq()
+//! to signal that the interrupt is completely handled.
+//!
+//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles
+//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated
+//! but nothing else.
+//!
+//! @return The number for the highest priority interrupt available for the calling CPU. If
+//!     the return value is 1022 or 1023, a spurious interrupt has occurred.
+uint32_t gic_read_irq_ack(void);
+
+//! @brief Signal the end of handling an interrupt.
+//!
+//! @param irq_id The number of the interrupt for which handling has finished.
+void gic_write_end_of_irq(uint32_t irq_id);
+//@}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __GIC_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/gpt.h

@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_gpt
+//! @{
+
+/*!
+ * @file gpt.h
+ * @brief GPT driver public interface.
+ */
+
+#ifndef __GPT_H__
+#define __GPT_H__
+
+#include "imx_timer.h"
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Possible events for the GPT.
+//!
+//! These constants are intended to be combined together to form a bitmask. Several
+//! of the GPT driver APIs use such a bitmask. For instance, gpt_counter_enable()
+//! accepts a bitmask that selects the events for which interrupts should be enabled.
+//!
+//! Note that the values of these enums happen to be the bitmasks for the respective
+//! fields in the HW_GPT_SR and HW_GPT_IR registers, so a mask constructed from them
+//! can be used directly with register values.
+enum _gpt_events
+{
+    kGPTNoEvent = 0,               //!< No events enabled.
+    kGPTRollover = 1 << 5,         //!< Rollover event.
+    kGPTInputCapture1 = 1 << 3,    //!< Input capture 1 event.
+    kGPTInputCapture2 = 1 << 4,    //!< Input capture 2 event.
+    kGPTOutputCompare1 = 1 << 0,   //!< Output compare 1 event.
+    kGPTOutputCompare2 = 1 << 1,   //!< Output compare 2 event.
+    kGPTOutputCompare3 = 1 << 2,   //!< Output compare 3 event.
+    
+    //! Combined mask of all GPT events.
+    kGPTAllEvents = kGPTRollover | kGPTInputCapture1 | kGPTInputCapture2
+                    | kGPTOutputCompare1 | kGPTOutputCompare2 | kGPTOutputCompare3
+};
+
+//! @brief GPT counter modes.
+enum _gpt_counter_mode
+{
+    RESTART_MODE = 0,
+    FREE_RUN_MODE = 1
+};
+
+//! @brief Supported input capture modes.
+enum _gpt_capture_modes
+{
+    INPUT_CAP_DISABLE = 0,      //!< input capture event disabled
+    INPUT_CAP_RISING_EDGE = 1,  //!< input capture event on a rising edge
+    INPUT_CAP_FALLING_EDGE = 2, //!< input capture event on a falling edge
+    INPUT_CAP_BOTH_EDGE = 3     //!< input capture event on a both edge
+};
+
+//! @brief Supported output modes.
+enum _gpt_compare_modes
+{
+    OUTPUT_CMP_DISABLE = 0,     //!< output disconnected from pad
+    OUTPUT_CMP_TOGGLE = 1,      //!< output toggle mode
+    OUTPUT_CMP_CLEAR = 2,       //!< output set low mode
+    OUTPUT_CMP_SET = 3,         //!< output set high mode
+    OUTPUT_CMP_LOWPULSE = 4     //!< output set high mode
+};
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize the GPT timer.
+ *
+ * @param   clock_src Source clock of the counter: CLKSRC_OFF, CLKSRC_IPG_CLK,
+ *                      CLKSRC_PER_CLK, CLKSRC_CKIL, CLKSRC_CLKIN.
+ * @param   prescaler Prescaler of the source clock from 1 to 4096.
+ * @param   counter_mode Counter mode: FREE_RUN_MODE or RESTART_MODE.
+ * @param   low_power_mode Low power during which the timer is enabled:
+ *                           WAIT_MODE_EN and/or STOP_MODE_EN.
+ */
+void gpt_init(uint32_t clock_src, uint32_t prescaler, uint32_t counter_mode, uint32_t low_power_mode);
+
+/*!
+ * @brief Setup GPT interrupt.
+ *
+ * It enables or disables the related HW module interrupt, and attached the
+ * related sub-routine into the vector table.
+ *
+ * @param   irq_subroutine the GPT interrupt interrupt routine.
+ * @param   enableIt Pass true to enable the interrupt.
+ */
+void gpt_setup_interrupt(void (*irq_subroutine)(void), bool enableIt);
+
+/*!
+ * @brief Enable the GPT module.
+ *
+ * Used typically when the gpt_init is done, and other interrupt related settings are ready.
+ *
+ * If a value of #kGPTNoEvent is passed for @a irq_mode, then no interrupts will be enabled.
+ * This effectively puts the timer into polling mode, where you must call gpt_get_x_event()
+ * to check for an event having occurred.
+ *
+ * @param   irq_mode Mask of events to enable interrupts for, such as #kGPTRollover or
+ *      #kGPTOutputCompare1. See the #_gpt_events enum for the complete list. Pass
+ *      #kGPTNoEvent to prevent any interrupts from being enabled, which effectively puts
+ *      the timer into polling mode.
+ */
+void gpt_counter_enable(uint32_t irq_mode);
+
+/*!
+ * @brief Disable the counter.
+ *
+ * It saves power when not used.
+ *
+ */
+void gpt_counter_disable(void);
+
+/*!
+ * @brief Get rollover event flag and clear it if set.
+ *
+ * This function can typically be used for polling method, but
+ * is also used to clear the status compare flag in IRQ mode.
+ *
+ * @return  Either 0 of kGPTRollover.
+ */
+uint32_t gpt_get_rollover_event(void);
+
+/*!
+ * @brief Get a captured value when an event occured, and clear the flag if set.
+ *
+ * Use this function to check for an input capture event having occurred, either in
+ * the event ISR or to check manually in polling mode. Pass the input channel to check
+ * in the @a flag parameter. If that channel fired, its captured timer value will be
+ * read and placed in @a capture_val (if not NULL). The event that fired will be cleared
+ * and its event mask returned as the return value from the function. If no event
+ * occurred, the function returns 0.
+ *
+ * @param   flag Which channel to check, either #kGPTInputCapture1 or #kGPTInputCapture2.
+ *      Only one channel may be specified.
+ * @param   capture_val The capture register value is returned through this parameter if
+ *      the specified event occurred. May be NULL if not required.
+ * @return  Mask of input specified capture event that occurred, or 0 if no event occurred.
+ */
+uint32_t gpt_get_capture_event(uint8_t flag, uint32_t * capture_val);
+
+/*!
+ * @brief Set the input capture mode.
+ *
+ * @param   cap_input The input capture channel to configure, either #kGPTInputCapture1
+ *      or #kGPTInputCapture2.
+ * @param   cap_input_mode Capture input mode: #INPUT_CAP_DISABLE, #INPUT_CAP_BOTH_EDGE,
+ *                            #INPUT_CAP_FALLING_EDGE, #INPUT_CAP_RISING_EDGE.
+ */
+void gpt_set_capture_event(uint8_t cap_input, uint8_t cap_input_mode);
+
+/*!
+ * @brief Get a compare event flag and clear it if set.
+ *
+ * This function can typically be used for polling method, but
+ * is also used to clear the status compare flag in IRQ mode.
+ *
+ * @param   flag Checked compare event flag such GPTSR_OF1, GPTSR_OF2, GPTSR_OF3.
+ * @return  The value of the compare event flag.
+ */
+uint32_t gpt_get_compare_event(uint8_t flag);
+
+/*!
+ * @brief Set a compare event by programming the compare register and 
+ * compare output mode.
+ *
+ * @param   cmp_output The channel to configure. Must be one of #kGPTOutputCompare1,
+ *      #kGPTOutputCompare2, or #kGPTOutputCompare3.
+ * @param   cmp_output_mode Compare output mode: #OUTPUT_CMP_DISABLE, #OUTPUT_CMP_TOGGLE,
+ *                            #OUTPUT_CMP_CLEAR, #OUTPUT_CMP_SET, #OUTPUT_CMP_LOWPULSE.
+ * @param   cmp_value Compare value for the compare register.
+ */
+void gpt_set_compare_event(uint8_t cmp_output, uint8_t cmp_output_mode, uint32_t cmp_value);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif //__GPT_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/imx_i2c.h

@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IMX_I2C_H__
+#define __IMX_I2C_H__
+
+#include "sdk_types.h"
+
+//! @addtogroup diag_i2c
+
+//! @{
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Read/write address bits
+//!
+//! Bit 0 of the i2c device address cycle to indicate r/w. 0 is for write, 1 is for read.
+enum _i2c_rq {
+    I2C_WRITE = 0,
+    I2C_READ = 1
+};
+
+//! @brief I2C Error Codes
+enum _i2c_err {
+    ERR_TX = -1,
+    ERR_RX = -2,
+    ERR_ARB_LOST = -3,
+    ERR_NO_ACK = -4,
+    ERR_XFER = -5,
+    ERR_RX_ACK = -6,
+    ERR_NO_ACK_ON_START = -7,
+    ERR_INVALID_REQUEST = -8
+};
+
+//! Default slave address used for the MX6.
+enum _i2c_slave_id {
+    IMX6_DEFAULT_SLAVE_ID = 0x60
+};
+
+//! @brief Info required to talk to an I2C device.
+//!
+//! Pairs an I2C port number with a device address.
+//!
+//! While the device address is often fixed and known in advance by the driver,
+//! some devices have configurable addresses that can be changed with pin
+//! settings. Thus, the same device may have different adresses on different
+//! boards depending on how these pins are tied.
+//!
+//! Note that the @a address member's value is @i not pre-shifted. The 7-bit
+//! address is right aligned within the byte, and the top bit is always set to 0.
+typedef struct i2c_device_info {
+    uint8_t port;       //!< I2C controller instance to which the device is connected. Starts at 1.
+    uint8_t address;    //!< I2C device address in lower 7 bits.
+    uint32_t freq;       //!< Maximum transfer speed in bits per second.
+} i2c_device_info_t;
+
+/*!
+ * @brief An I2C transfer descriptor.
+ *
+ * To perform an I2C transfer, the caller first fills in an instance of this struct. Then
+ * i2c_xfer() is called, passing a pointer to the #imx_i2c_request_t struct.
+ *
+ * @a ctl_addr should be set to either a valid controller instance number from 1 through
+ * the number of I2C instances on the chip, or the base address of the controller.
+ *
+ * If @a device is set to a non-NULL value, it is a pointer to an #i2c_device_info_t struct
+ * to use instead of the @a ctl_addr and @a dev_addr members of this struct.
+ */
+typedef struct imx_i2c_request {
+    uint32_t ctl_addr;          //!< Either the I2C controller base address or instance number starting at 1.
+    uint32_t dev_addr;          //!< The I2C device address.
+    uint32_t reg_addr;          //!< The register address within the target device.
+    uint32_t reg_addr_sz;       //!< Number of bytes for the address of I2C device register.
+    uint8_t *buffer;            //!< Buffer to hold the data.
+    uint32_t buffer_sz;         //!< The number of bytes for read/write.
+    int32_t (*slave_receive) (const struct imx_i2c_request *rq);  //!< Function for slave to receive data from master.
+    int32_t (*slave_transmit) (const struct imx_i2c_request *rq); //!< Function for slave to transmit data to master.
+    const i2c_device_info_t * device; //!< Optional pointer to device info struct. Overrides @a ctl_addr and @a dev_addr if set.
+} imx_i2c_request_t;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize the I2C module
+ *
+ * Mainly enable the I2C clock, module itself and the I2C clock prescaler.
+ *
+ * @param   base Either the base address of I2C module or the module's instance number. (also assigned for I2Cx_CLK)
+ * @param   baud The desired data rate in bits per second.
+ *
+ * @return  0 if successful; non-zero otherwise
+ */
+int i2c_init(uint32_t base, uint32_t baud);
+
+/*!
+ * @brief Perform a single I2C transfer in the selected direction.
+ *
+ * This is a rather simple function that can be used for most I2C devices.
+ *
+ * Common steps for both READ and WRITE:
+ *     - step 1: issue start signal
+ *     - step 2: put I2C device addr on the bus (always 1 byte write. the dir always I2C_WRITE)
+ *     - step 3: offset of the I2C device write (offset within the device. can be 1-4 bytes)
+ *
+ * For READ:
+ *     - step 4: do repeat-start
+ *     - step 5: send slave address again, but indicate a READ operation by setting LSB bit
+ *     - Step 6: change to receive mode
+ *     - Step 7: dummy read
+ *     - Step 8: reading
+ *
+ * For WRITE:
+ *     - Step 4: do data write
+ *     - Step 5: generate STOP by clearing MSTA bit
+ *
+ * @param   rq        Pointer to #imx_i2c_request_t.
+ * @param   dir       #I2C_READ or #I2C_WRITE
+ *
+ * @return  0 on success; non-zero otherwise
+ */
+int i2c_xfer(const imx_i2c_request_t *rq, int dir);
+
+/*!
+ * @brief Perform I2C read transfer.
+ *
+ * @param rq Pointer to #imx_i2c_request_t.
+ */
+int i2c_read(const imx_i2c_request_t *rq);
+
+/*!
+ * @brief Perform I2C write transfer.
+ *
+ * @param rq Pointer to #imx_i2c_request_t.
+ */
+int i2c_write(const imx_i2c_request_t *rq);
+
+/*!
+ * @brief I2C handler for the slave mode.
+ *
+ * The function is based on the flow chart for typical I2C polling routine described in the
+ * I2C controller chapter of the reference manual.
+ *
+ * @param   rq Pointer to #imx_i2c_request_t.
+ */
+void i2c_slave_handler(const imx_i2c_request_t *rq);
+
+/*!
+ * @brief Handle the I2C transfers in slave mode.
+ *
+ * The slave mode behaves like any device with g_addr_cycle of address + g_data_cycle of data.
+ * Master read =
+ * START - SLAVE_ID/W - ACK - MEM_ADDR - ACK - START - SLAVE_ID/R - ACK - DATAx - NACK - STOP
+ * 
+ * Example for a 16-bit address access:
+ * - 1st IRQ - receive the slave address and Write flag from master.
+ * - 2nd IRQ - receive the lower byte of the requested 16-bit address.
+ * - 3rd IRQ - receive the higher byte of the requested 16-bit address.
+ * - 4th IRQ - receive the slave address and Read flag from master.
+ * - 5th and next IRQ - transmit the data as long as NACK and STOP is not asserted.
+ *
+ * Master write =
+ * START - SLAVE_ID/W - ACK - MEM_ADDR - ACK - DATAx - NACK - STOP
+ *
+ * - 1st IRQ - receive the slave address and Write flag from master.
+ * - 2nd IRQ - receive the lower byte of the requested 16-bit address.
+ * - 3rd IRQ - receive the higher byte of the requested 16-bit address.
+ * - 4th and next IRQ - receive the data as long STOP is not asserted.
+ *
+ * @param   port Pointer to the I2C module structure.
+ * @param   rq Pointer to #imx_i2c_request_t.
+ */
+void i2c_slave_xfer(imx_i2c_request_t *rq);
+
+////////////////////////////////////////////////////////////////////////////////
+// Board support
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Board support functions
+//!
+//! These functions are called by the driver in order to factor out board
+//! specific functionality. They must be defined by the board support
+//! library or the application.
+//@{
+//! @brief Configure IOMUX for the I2C driver.
+void i2c_iomux_config(int instance);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif /* __IMX_I2C_H__ */
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/imx_timer.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+//! @addtogroup diag_timer
+//! @{
+
+/*!
+ * @file timer.h
+ * @brief various defines used by the timer driver.
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Constants
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Options for low power mode support for the timers.
+//!
+//! These constants are bit masks that are or'd together to select in which low
+//! power modes the timer will continue counting.
+enum _timer_low_power_modes
+{
+    WAIT_MODE_EN = 1,   //!< Timer is enabled in wait mode.
+    STOP_MODE_EN = 2    //!< Timer is enabled in stop mode.
+};
+
+//! @brief Available clock sources for the timers.
+enum _timer_clock_sources
+{
+    CLKSRC_OFF = 0,     //!< clock source is OFF
+    CLKSRC_IPG_CLK = 1, //!< clock source is peripheral clock
+    CLKSRC_PER_CLK = 2, //!< clock source is high-freq reference clock
+    CLKSRC_CLKIN = 3,   //!< clock source is external from a CLKIN input
+    CLKSRC_CKIL = 3     //!< clock source is low-freq reference clock
+};
+
+//! @brief Do not enable interrupts.
+#define POLLING_MODE 0
+
+////////////////////////////////////////////////////////////////////////////////
+// Externs
+////////////////////////////////////////////////////////////////////////////////
+extern uint32_t g_system_timer_port;
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Delay for a given number of microseconds.
+//!
+//! system_time_init() must have been called before using this function.
+//!
+//! @param usecs Delay in microseconds.
+void hal_delay_us(uint32_t usecs);
+
+//! @brief Init system timer facilities.
+//!
+//! Inits the EPIT timer used for delay, and inits the microsecond counter.
+void system_time_init(void);
+
+//! @brief Return the current microsecond counter value.
+//!
+//! @return The number of microseconds elapsed since system_time_init()
+//!     was called. This value may roll over before reaching all ones.
+uint64_t time_get_microseconds();
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif // __TIMER_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/imx_uart.h

@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*!
+ * @file imx_uart.h
+ * @brief various defines used by imx_uart.c
+ */
+
+#ifndef __IMX_UART_H__
+#define __IMX_UART_H__
+
+#include "sdk.h"
+
+//! @addtogroup diag_uart
+//! @{
+
+//////////////////////////////////////////////////////////////////////////
+//Constants
+/////////////////////////////////////////////////////////////////////////
+
+/* UART specific defines */
+//! @brief Modes of the PARITY for UART transfer.
+enum _uart_parity
+{
+	PARITY_NONE = 0, //!< PARITY mode is PARITY_NONE.
+	PARITY_EVEN = 2, //!< PARITY mode is PARITY_EVEN.
+        PARITY_ODD  = 3  //!< PARITY mode is PARITY_ODD. 
+};
+
+//!  @brief Number of stopbits after a character.
+enum _uart_stopbits
+{
+	STOPBITS_ONE = 0, //!< One stopbits after a character.
+	STOPBITS_TWO = 1  //!< Two stopbits after a character.
+};
+
+//!  @brief Flow control mode for UART transfer.
+enum _uart_flowctrl
+{
+	FLOWCTRL_OFF = 0, //!< Flow control off for UART transfer.
+	FLOWCTRL_ON  = 1  //!< Flow control on for UART transfer.
+};
+
+//!  @brief Specify the FIFO for UART transfer.
+enum _uart_fifo
+{
+	TX_FIFO = 0,	  //!< Config the TX fifo for UART transfer.
+	RX_FIFO = 1	  //!< Config the RX fifo for UART transfer.
+};   	
+
+//! @brief Specify the number of bits in a data
+enum _uart_bits
+{
+	SEVENBITS = 0,	  //!< Config seven bits in a data.
+	EIGHTBITS = 1     //!< Config eight bits in a data.
+};
+
+//! @brief Specify the service mode
+#define	DMA_MODE  2	  //!< Config the service mode for dma request.
+#define	IRQ_MODE  1      //!< Config the service mode for interrupt.
+
+#define UART_MODULE_CLK(x) ((x) == HW_UART1 ? UART1_MODULE_CLK : (x) == HW_UART2 ? UART2_MODULE_CLK : (x) == HW_UART3 ? UART3_MODULE_CLK : (x) == HW_UART4 ? UART4_MODULE_CLK : -1)
+
+#define UART_IRQS(x) ((x) == HW_UART1 ? IMX_INT_UART1 : (x) == HW_UART2 ? IMX_INT_UART2 : (x) == HW_UART3 ? IMX_INT_UART3 : (x) == HW_UART4 ? IMX_INT_UART4 : (x) == HW_UART5 ? IMX_INT_UART5 : 0xFFFFFFFF)
+
+//////////////////////////////////////////////////////////////////////////
+//API
+/////////////////////////////////////////////////////////////////////////
+
+
+/*!
+ * @brief   Initialize the UART port
+ *
+ * @param   instance the UART instance number.
+ * @param   baudrate serial baud rate such 9600, 57600, 115200, etc.
+ * @param   parity enable parity checking: PARITY_NONE, PARITY_EVEN,
+ *                   PARITY_ODD.
+ * @param   stopbits number of stop bits: STOPBITS_ONE, STOPBITS_TWO.
+ * @param   datasize number of bits in a data: SEVENBITS, EIGHTBITS,
+ *                     NINEBITS (like RS-485 but not supported).
+ * @param   flowcontrol enable (RTS/CTS) hardware flow control:
+ *                        FLOWCTRL_ON, FLOWCTRL_OFF.
+ */
+void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol);
+
+/*!
+ * @brief   Output a character to UART port
+ *
+ * @param   instance the UART instance number.
+ * @param   ch pointer to the character for output
+ * @return  the character that has been sent
+ */
+uint8_t uart_putchar(uint32_t instance, uint8_t * ch);
+
+/*!
+ * @brief   Receive a character on the UART port
+ *
+ * @param   instance the UART instance number.
+ * @return  a character received from the UART port; if the RX FIFO
+ *          is empty or errors are detected, it returns NONE_CHAR
+ */
+uint8_t uart_getchar(uint32_t instance);
+
+/*!
+ * @brief   Configure the RX or TX FIFO level and trigger mode
+ *
+ * @param   instance the UART instance number.
+ * @param   fifo FIFO to configure: RX_FIFO or TX_FIFO.
+ * @param   trigger_level set the trigger level of the FIFO to generate
+ *                          an IRQ or a DMA request: number of characters.
+ * @param   service_mode FIFO served with DMA or IRQ or polling (default).
+ */
+void uart_set_FIFO_mode(uint32_t instance, uint8_t fifo, uint8_t trigger_level,
+                        uint8_t service_mode);
+
+/*!
+ * @brief   Enables UART loopback test mode
+ *
+ * @param   instance the UART instance number.
+ * @param   state enable/disable the loopback mode
+ */
+void uart_set_loopback_mode(uint32_t instance, uint8_t state);
+
+/*!
+ * @brief   Setup UART interrupt. It enables or disables the related HW module
+ * interrupt, and attached the related sub-routine into the vector table.
+ *
+ * @param   instance the UART instance number.
+ * @param   irq_subroutine the UART interrupt interrupt routine.
+ * @param   state ENABLE or DISABLE the interrupt.
+ */
+void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state);
+
+
+/*!
+ * @brief   Obtain UART reference frequency
+ *
+ * @param   instance the UART instance number.
+ * @return  reference frequency in Hz
+ */
+uint32_t uart_get_reffreq(uint32_t instance);
+
+//! @name Board support functions
+//!
+//! These functions are called by the driver in order to factor out board
+//! specific functionality. They must be defined by the board support
+//! library or the application.
+//@{
+//! @brief Configure IOMUX for the UART driver.
+void uart_iomux_config(int instance);
+//@}
+
+//! @}
+
+#endif //__IMX_UART_H__

bsp/imx6ul/platform/include/interrupt.h

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2009-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include "sdk_types.h"
+#include "irq_numbers.h"
+
+//! @addtogroup diag_interrupt
+//! @{
+
+/*!
+ * @file interrupt.h
+ * @brief Interface for the interrupt manager.
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief
+typedef enum {
+    CPU_0,
+    CPU_1,
+    CPU_2,
+    CPU_3,
+} cpuid_e;
+
+//! @brief Interrupt service routine.
+typedef void (*irq_hdlr_t) (void);
+
+////////////////////////////////////////////////////////////////////////////////
+// API
+////////////////////////////////////////////////////////////////////////////////
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//! @brief Enable an interrupt.
+//!
+//! Sets the interrupt priority and makes it non-secure. Then the interrupt is
+//! enabled on the CPU specified by @a cpu_id.
+//!
+//! @param irq_id The interrupt number to enable.
+//! @param cpu_id The index of the CPU for which the interrupt will be enabled.
+//! @param priority The interrupt priority, from 0-255. Lower numbers have higher priority.
+void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority);
+
+//! @brief Disable an interrupt on the specified CPU.
+//!
+//! @param irq_id The interrupt number to disabled.
+//! @param cpu_id The index of the CPU for which the interrupt will be disabled.
+void disable_interrupt(uint32_t irq_id, uint32_t cpu_id);
+
+//! @brief Set the interrupt service routine for the specified interrupt.
+//!
+//! @param irq_id The interrupt number.
+//! @param isr Function that will be called to handle the interrupt.
+void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr);
+
+//! @brief Interrupt handler that simply prints a message.
+void default_interrupt_routine(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+//! @}
+
+#endif
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/io.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file io.h
+ * @brief Register access macros.
+ *
+ * @ingroup diag_init
+ */
+#ifndef __IO_H__
+#define __IO_H__
+
+#include "sdk_types.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "sdk.h"
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Register read functions
+//@{
+#define reg8_read(addr)       *((volatile uint8_t *)(addr))
+#define reg16_read(addr)      *((volatile uint16_t *)(addr))
+#define reg32_read(addr)      *((volatile uint32_t *)(addr))
+//@}
+
+//! @name Register write functions
+//@{
+#define reg8_write(addr,val)  *((volatile uint8_t *)(addr)) = (val)
+#define reg16_write(addr,val) *((volatile uint16_t *)(addr)) = (val)
+#define reg32_write(addr,val) *((volatile uint32_t *)(addr)) = (val)
+//@}
+
+//! @name Memory read functions
+//@{
+#define mem8_read(addr)       *((volatile uint8_t *)(addr))
+#define mem16_read(addr)      *((volatile uint16_t *)(addr))
+#define mem32_read(addr)      *((volatile uint32_t *)(addr))
+//@}
+
+//! @name Memory write functions
+//@{
+#define mem8_write(addr,val)  *((volatile uint8_t *)(addr)) = (val)
+#define mem16_write(addr,val) *((volatile uint16_t *)(addr)) = (val)
+#define mem32_write(addr,val) *((volatile uint32_t *)(addr)) = (val)
+//@}
+
+//! @name Read functions
+//@{
+#define readb(a)        reg8_read(a)
+#define readw(a)        reg16_read(a)
+#define readl(a)        reg32_read(a)
+//@}
+
+//! @name Write functrions
+//!
+//! The prefered method to access registers.
+//@{
+#define writeb(v, a)    reg8_write(a, v)
+#define writew(v, a)    reg16_write(a, v)
+#define writel(v, a)    reg32_write(a, v)
+//@}
+
+//! @name Bit set/clear functions
+//@{
+#define  reg8setbit(addr,bitpos) \
+         reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos))))
+
+#define  reg16setbit(addr,bitpos) \
+         reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos))))
+
+#define  reg32setbit(addr,bitpos) \
+         reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos))))
+
+#define  reg8clrbit(addr,bitpos) \
+         reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos)))))
+
+#define  reg16clrbit(addr,bitpos) \
+         reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos)))))
+
+#define  reg32clrbit(addr,bitpos) \
+         reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
+//@}
+
+//! @name Masked write functions
+//@{
+#define reg8_write_mask(addr, data, mask) \
+        reg8_write((addr),((reg8_read(addr) & (~mask)) | (mask & data)))
+
+#define reg16_write_mask(addr, data, mask) \
+        reg16_write((addr),((reg16_read(addr) & (~mask)) | (mask & data)))
+
+#define reg32_write_mask(addr, data, mask) \
+        reg32_write((addr),((reg32_read(addr) & (~mask)) | (mask & data)))
+
+#define gen_msk32(start, end)	((0xFFFFFFFF << (start)) ^ (0xFFFFFFFF << ((end + 1))))
+#define reg32_set_field(addr, start, end, val) \
+		reg32_write_mask(addr, (val) << (start), gen_msk32((start, end)))
+//@}
+
+/*!
+ * This macro is used to get certain bit field from a number
+ */
+#define GET_FIELD(val, len, sh)          ((val >> sh) & ((1 << len) - 1))
+
+/*!
+ * This macro is used to set certain bit field inside a number
+ */
+#define SET_FIELD(val, len, sh, nval)    ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#endif // __IO_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/mx6ul/ccm_pll_reg_define.h

@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+#ifndef _CCM_PLL_REG_DEFINE_H_
+#define _CCM_PLL_REG_DEFINE_H_
+
+//#########################################
+//# DPLLIP peripheral defines
+//#########################################
+#define DPLLIP_DP_CTL_OFFSET	0x000
+#define DPLLIP_DP_CONFIG_OFFSET	0x004
+#define DPLLIP_DP_OP_OFFSET	0x008
+#define DPLLIP_DP_MFD_OFFSET	0x00C
+#define DPLLIP_DP_MFN_OFFSET	0x010
+#define DPLLIP_DP_MFNMINUS_OFFSET	0x014
+#define DPLLIP_DP_MFNPLUS_OFFSET	0x018
+#define DPLLIP_DP_HFS_OP_OFFSET	0x01C
+#define DPLLIP_DP_HFS_MFD_OFFSET	0x020
+#define DPLLIP_DP_HFS_MFN_OFFSET	0x024
+#define DPLLIP_DP_MFN_TOGC_OFFSET	0x028
+#define DPLLIP_DP_DESTAT_OFFSET	0x02C
+
+#define DPLLIP1_DP_CONFIG          DPLLIP1_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
+#define DPLLIP1_DP_CTL             DPLLIP1_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
+#define DPLLIP1_DP_OP              DPLLIP1_BASE_ADDR+DPLLIP_DP_OP_OFFSET
+#define DPLLIP1_DP_MFD             DPLLIP1_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
+#define DPLLIP1_DP_MFN             DPLLIP1_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
+
+#define DPLLIP2_DP_CONFIG          DPLLIP2_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
+#define DPLLIP2_DP_CTL             DPLLIP2_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
+#define DPLLIP2_DP_OP              DPLLIP2_BASE_ADDR+DPLLIP_DP_OP_OFFSET
+#define DPLLIP2_DP_MFD             DPLLIP2_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
+#define DPLLIP2_DP_MFN             DPLLIP2_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
+
+#define DPLLIP3_DP_CONFIG          DPLLIP3_BASE_ADDR+DPLLIP_DP_CONFIG_OFFSET
+#define DPLLIP3_DP_CTL             DPLLIP3_BASE_ADDR+DPLLIP_DP_CTL_OFFSET
+#define DPLLIP3_DP_OP              DPLLIP3_BASE_ADDR+DPLLIP_DP_OP_OFFSET
+#define DPLLIP3_DP_MFD             DPLLIP3_BASE_ADDR+DPLLIP_DP_MFD_OFFSET
+#define DPLLIP3_DP_MFN             DPLLIP3_BASE_ADDR+DPLLIP_DP_MFN_OFFSET
+
+//#########################################
+//# CCM peripheral defines
+//#########################################
+#define CCM_CCR_OFFSET  0x00
+#define CCM_CCDR_OFFSET 0x04
+#define CCM_CSR_OFFSET  0x08
+#define CCM_CCSR_OFFSET 0x0C
+#define CCM_CACRR_OFFSET        0x10
+#define CCM_CBCDR_OFFSET        0x14
+#define CCM_CBCMR_OFFSET 0X18
+#define CCM_CSCMR1_OFFSET 0x1c
+#define CCM_CSCMR2_OFFSET 0x20
+#define CCM_CSCDR1_OFFSET 0x24
+#define CCM_CS1CDR_OFFSET 0x28
+#define CCM_CS2CDR_OFFSET 0x2c
+#define CCM_CDCDR_OFFSET 0x30
+#define CCM_CHSCCDR_OFFSET 0x34
+#define CCM_CSCDR2_OFFSET 0x38
+#define CCM_CSCDR3_OFFSET 0x3c
+#define CCM_CSCDR4_OFFSET 0x40
+#define CCM_CWDR_OFFSET   0x44
+#define CCM_CDHIPR_OFFSET 0x48
+#define CCM_CDCR_OFFSET   0x4c
+#define CCM_CTOR_OFFSET   0x50
+#define CCM_CLPCR_OFFSET  0x54
+#define CCM_CISR_OFFSET 0x58
+#define CCM_CIMR_OFFSET 0x5c
+#define CCM_CCOSR_OFFSET 0x60
+#define CCM_CGPR_OFFSET 0x64
+#define CCM_CCGR0_OFFSET 0x68
+#define CCM_CCGR1_OFFSET 0x6c
+#define CCM_CCGR2_OFFSET 0x70
+#define CCM_CCGR3_OFFSET 0x74
+#define CCM_CCGR4_OFFSET 0x78
+#define CCM_CCGR5_OFFSET 0x7c
+#define CCM_CCGR6_OFFSET 0x80
+#define CCM_CCGR7_OFFSET 0x84
+#define CCM_CMEOR_OFFSET 0x88
+
+#define CCM_CCR     CCM_BASE_ADDR+CCM_CCR_OFFSET
+#define CCM_CCDR    CCM_BASE_ADDR+CCM_CCDR_OFFSET
+#define CCM_CSR     CCM_BASE_ADDR+CCM_CSR_OFFSET
+#define CCM_CCSR    CCM_BASE_ADDR+CCM_CCSR_OFFSET
+#define CCM_CACRR   CCM_BASE_ADDR+CCM_CACRR_OFFSET
+#define CCM_CBCDR   CCM_BASE_ADDR+CCM_CBCDR_OFFSET
+#define CCM_CBCMR   CCM_BASE_ADDR+CCM_CBCMR_OFFSET
+#define CCM_CSCMR1  CCM_BASE_ADDR+CCM_CSCMR1_OFFSET
+#define CCM_CSCMR2  CCM_BASE_ADDR+CCM_CSCMR2_OFFSET
+#define CCM_CSCDR1  CCM_BASE_ADDR+CCM_CSCDR1_OFFSET
+#define CCM_CS1CDR  CCM_BASE_ADDR+CCM_CS1CDR_OFFSET
+#define CCM_CS2CDR  CCM_BASE_ADDR+CCM_CS2CDR_OFFSET
+#define CCM_CDCDR   CCM_BASE_ADDR+CCM_CDCDR_OFFSET
+#define CCM_CHSCCDR CCM_BASE_ADDR+CCM_CHSCCDR_OFFSET
+#define CCM_CSCDR2  CCM_BASE_ADDR+CCM_CSCDR2_OFFSET
+#define CCM_CSCDR3  CCM_BASE_ADDR+CCM_CSCDR3_OFFSET
+#define CCM_CSCDR4  CCM_BASE_ADDR+CCM_CSCDR4_OFFSET
+#define CCM_CWDR    CCM_BASE_ADDR+CCM_CWDR_OFFSET
+#define CCM_CDHIPR  CCM_BASE_ADDR+CCM_CDHIPR_OFFSET
+#define CCM_CDCR    CCM_BASE_ADDR+CCM_CDCR_OFFSET
+#define CCM_CTOR    CCM_BASE_ADDR+CCM_CTOR_OFFSET
+#define CCM_CLPCR   CCM_BASE_ADDR+CCM_CLPCR_OFFSET
+#define CCM_CISR    CCM_BASE_ADDR+CCM_CISR_OFFSET
+#define CCM_CIMR    CCM_BASE_ADDR+CCM_CIMR_OFFSET
+#define CCM_CCOSR   CCM_BASE_ADDR+CCM_CCOSR_OFFSET
+#define CCM_CGPR    CCM_BASE_ADDR+CCM_CGPR_OFFSET
+#define CCM_CCGR0   CCM_BASE_ADDR+CCM_CCGR0_OFFSET
+#define CCM_CCGR1   CCM_BASE_ADDR+CCM_CCGR1_OFFSET
+#define CCM_CCGR2   CCM_BASE_ADDR+CCM_CCGR2_OFFSET
+#define CCM_CCGR3   CCM_BASE_ADDR+CCM_CCGR3_OFFSET
+#define CCM_CCGR4   CCM_BASE_ADDR+CCM_CCGR4_OFFSET
+#define CCM_CCGR5   CCM_BASE_ADDR+CCM_CCGR5_OFFSET
+#define CCM_CCGR6   CCM_BASE_ADDR+CCM_CCGR6_OFFSET
+#define CCM_CCGR7   CCM_BASE_ADDR+CCM_CCGR7_OFFSET
+#define CCM_CMEOR   CCM_BASE_ADDR+CCM_CMEOR_OFFSET
+
+//#########################################
+//# CCM peripheral defines used by prog_pll.c and hardware.c
+//#########################################
+#define CLKCTL_CCGR1        CCM_CCGR1_OFFSET
+#define CLKCTL_CSCMR1       CCM_CSCMR1_OFFSET
+#define CLKCTL_CSCDR1       CCM_CSCDR1_OFFSET
+#define CLKCTL_CBCMR        CCM_CBCMR_OFFSET
+#define CLKCTL_CBCDR        CCM_CBCDR_OFFSET
+#define CLKCTL_CCSR         CCM_CCSR_OFFSET
+#define CLKCTL_CDHIPR       CCM_CDHIPR_OFFSET
+#define CLKCTL_CACRR        CCM_CACRR_OFFSET
+#define CLKCTL_CSCDR2       CCM_CSCDR2_OFFSET
+#define CLKCTL_CS1CDR       CCM_CS1CDR_OFFSET
+#define CLKCTL_CS2CDR       CCM_CS2CDR_OFFSET
+
+#define CLKCTL_CSCMR2       CCM_CSCMR2_OFFSET
+
+#define PLL1_BASE_ADDR      DPLLIP1_BASE_ADDR
+#define PLL2_BASE_ADDR      DPLLIP2_BASE_ADDR
+#define PLL3_BASE_ADDR      DPLLIP3_BASE_ADDR
+#define PLL4_BASE_ADDR      DPLLIP4_BASE_ADDR
+
+#define PLL_DP_CTL          DPLLIP_DP_CTL_OFFSET
+#define PLL_DP_CONFIG       DPLLIP_DP_CONFIG_OFFSET
+#define PLL_DP_OP           DPLLIP_DP_OP_OFFSET
+#define PLL_DP_MFD          DPLLIP_DP_MFD_OFFSET
+#define PLL_DP_MFN          DPLLIP_DP_MFN_OFFSET
+#define PLL_DP_MFNMINUS     DPLLIP_DP_MFNMINUS_OFFSET
+#define PLL_DP_MFNPLUS      DPLLIP_DP_MFNPLUS_OFFSET
+#define PLL_DP_HFS_OP       DPLLIP_DP_HFS_OP_OFFSET
+#define PLL_DP_HFS_MFD      DPLLIP_DP_HFS_MFD_OFFSET
+#define PLL_DP_HFS_MFN      DPLLIP_DP_HFS_MFN_OFFSET
+#define PLL_DP_TOGC         DPLLIP_DP_MFN_TOGC_OFFSET
+#define PLL_DP_DESTAT       DPLLIP_DP_DESTAT_OFFSET
+
+#endif

bsp/imx6ul/platform/include/mx6ul/fsl_bitaccess.h

@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _FSL_BITACCESS_H
+#define _FSL_BITACCESS_H  1
+
+#include <stdint.h>
+#include <stdlib.h>
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*
+ * Macros for single instance registers
+ */
+
+#define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
+#define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
+#define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
+
+#define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RD(reg, field)        HW_##reg.B.field
+#define BF_WR(reg, field, v)     BW_##reg##_##field(v)
+
+#define BF_CS1(reg, f1, v1)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+/*
+ * Macros for multiple instance registers
+ */
+
+#define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
+#define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
+#define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
+
+#define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RDn(reg, n, field)        HW_##reg(n).B.field
+#define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+/*
+ * Macros for single instance MULTI-BLOCK registers
+ */
+
+#define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
+#define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
+#define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
+
+#define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
+#define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
+#define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
+
+#define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
+#define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
+
+#define BFn_CS1(reg, blk, f1, v1)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
+
+#define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+/*
+ * Macros for MULTI-BLOCK multiple instance registers
+ */
+
+#define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
+#define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
+#define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
+
+#define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
+#define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
+#define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
+
+#define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
+#define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BFn_CS1n(reg, blk, n, f1, v1)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
+
+#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+#endif /* _FSL_BITACCESS_H */
+
+/******************************************************************************/

bsp/imx6ul/platform/include/mx6ul/functions.h

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+/*!
+ * @file functions.h
+ * @brief This header file contains functions info.
+ *
+ */
+#ifndef FUNCTIONS_H
+#define FUNCTIONS_H
+
+//----------------------------------------------------------------------
+//  Some Genaral Macros
+//----------------------------------------------------------------------
+//#define FALSE 0
+//#define TRUE  1
+
+#define DUMMY_INFO 0xf00f00
+
+#define reg8_read(addr)       *((BYTE *)(addr))
+#define reg16_read(addr)      *((HALF *)(addr))
+#define reg32_read(addr)      *(WORD *)((addr))
+
+#define reg32_read_bit(addr,bitpos) (reg32_read(addr) & (1<<(bitpos)))
+
+#define reg8_write(addr,val)  *((BYTE *)(addr)) = (val)
+#define reg16_write(addr,val) *((HALF *)(addr)) = (val)
+#define reg32_write(addr,val) *((WORD *)(addr)) = (val)
+
+#define mem8_read(addr)       *((BYTE *)(addr))
+#define mem16_read(addr)      *((HALF *)(addr))
+#define mem32_read(addr)      *(WORD *)((addr))
+
+#define mem8_write(addr,val)  *((BYTE *)(addr)) = (val)
+#define mem16_write(addr,val) *((HALF *)(addr)) = (val)
+#define mem32_write(addr,val) *((WORD *)(addr)) = (val)
+
+#define  reg8setbit(addr,bitpos) \
+         reg8_write((addr),(reg8_read((addr)) | (1<<(bitpos))))
+
+#define  reg16setbit(addr,bitpos) \
+         reg16_write((addr),(reg16_read((addr)) | (1<<(bitpos))))
+
+#define  reg32setbit(addr,bitpos) \
+         reg32_write((addr),(reg32_read((addr)) | (1<<(bitpos))))
+
+#define  reg8clrbit(addr,bitpos) \
+         reg8_write((addr),(reg8_read((addr)) & (0xFF ^ (1<<(bitpos)))))
+
+#define  reg16clrbit(addr,bitpos) \
+         reg16_write((addr),(reg16_read((addr)) & (0xFFFF ^ (1<<(bitpos)))))
+
+#define  reg32clrbit(addr,bitpos) \
+         reg32_write((addr),(reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
+
+// #####   EXPORTED TYPE DEFINITIONS   ################################################# {{{1
+
+typedef volatile unsigned long WORD;
+typedef volatile unsigned short HALF;
+typedef volatile unsigned char BYTE;
+
+//----------------------------------------------------------------------
+//  Write With Mask (write only certain bits)
+//----------------------------------------------------------------------
+void reg8_write_mask(WORD addr, BYTE wdata, BYTE mask);
+void reg16_write_mask(WORD addr, HALF wdata, HALF mask);
+void reg32_write_mask(WORD addr, WORD wdata, WORD mask);
+
+#endif //FUNCTIONS_H

bsp/imx6ul/platform/include/mx6ul/gpio_define.h

@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+#ifndef _GPIO_DEFINE_H_
+#define  _GPIO_DEFINE_H_
+
+#if 0
+#define GPIO_DR_OFFSET              0x0000
+#define GPIO_GDIR_OFFSET            0x0004
+#define GPIO_PSR_OFFSET             0x0008
+#endif
+
+typedef enum {
+    GPIO_PORT1 = 0,
+    GPIO_PORT2 = 1,
+    GPIO_PORT3 = 2,
+    GPIO_PORT4 = 3,
+    GPIO_PORT5 = 4,
+    GPIO_PORT6 = 5,
+    GPIO_PORT7 = 6,
+} GPIO_PORT;
+
+typedef struct {
+    unsigned int DR;
+    unsigned int GDIR;
+    unsigned int PSR;
+    unsigned int ICR1;
+    unsigned int ICR2;
+    unsigned int IMR;
+    unsigned int ISR;
+    unsigned int EDGE_SEL;
+} CSP_GPIO_REGS, *PCSP_GPIO_REGS;
+
+#define GPIO_GDIR_INPUT             0   // GPIO pin is input
+#define GPIO_GDIR_OUTPUT            1   // GPIO pin is output
+
+#define GPIO_LOW_LEVEL              0   // GPIO pin is low
+#define GPIO_HIGH_LEVEL             1   // GPIO pin is high
+
+#define GPIO_ICR_LOW_LEVEL          0   // Interrupt is low-level
+#define GPIO_ICR_HIGH_LEVEL         1   // Interrupt is high-level
+#define GPIO_ICR_RISE_EDGE          2   // Interrupt is rising edge
+#define GPIO_ICR_FALL_EDGE          3   // Interrupt is falling edge
+
+#define GPIO_IMR_MASKED             0   // Interrupt is masked
+#define GPIO_IMR_UNMASKED           1   // Interrupt is unmasked
+
+#define GPIO_EDGE_SEL_DISABLE       0   // Edge select is disabled
+#define GPIO_EDGE_SEL_ENABLE        1   // Edge select is enabled
+
+#define GPIO_PIN_MASK(pin)          (1U << (pin))
+#define GPIO_PIN_VAL(val, pin)      ((val) << (pin))
+#define GPIO_ICR_MASK(pin)          (0x3U << ((pin) << 1))
+#define GPIO_ICR_VAL(val, pin)      ((val) << ((pin) << 1))
+
+//#########################################
+//# GPIO peripheral defines
+//#########################################
+#define GPIO_DR0_OFFSET	0x00    //  32bit gpio pta data direction reg
+#define GPIO_GDIR0_OFFSET	0x04    //  32bit gpio pta output config 1 reg
+#define GPIO_PSR0_OFFSET	0x08    //  32bit gpio pta output config 2 reg
+#define GPIO_ICR1_OFFSET	0x0C    //  32bit gpio pta input config A1 reg
+#define GPIO_ICR2_OFFSET	0x10    //  32bit gpio pta input config A2 reg
+#define GPIO_IMR_OFFSET	0x14    //  32bit gpio pta input config B1 reg
+#define GPIO_ISR_OFFSET	0x18    // GPIO Interrupt Status Register
+#define GPIO_EDGE_SEL_OFFSET	0x1C    // GPIO Edge Detect Register
+
+#define GPIO1_DR                   GPIO1_BASE_ADDR+0x00
+#define GPIO1_GDIR                 GPIO1_BASE_ADDR+0x04
+#define GPIO1_PSR                  GPIO1_BASE_ADDR+0x08
+#define GPIO1_ICR1                 GPIO1_BASE_ADDR+0x0C
+#define GPIO1_ICR2                 GPIO1_BASE_ADDR+0x10
+#define GPIO1_IMR                  GPIO1_BASE_ADDR+0x14
+#define GPIO1_ISR                  GPIO1_BASE_ADDR+0x18
+#define GPIO1_EDGE_SEL             GPIO1_BASE_ADDR+0x1C
+
+#define GPIO2_DR                   GPIO2_BASE_ADDR+0x00
+#define GPIO2_GDIR                 GPIO2_BASE_ADDR+0x04
+#define GPIO2_PSR                  GPIO2_BASE_ADDR+0x08
+#define GPIO2_ICR1                 GPIO2_BASE_ADDR+0x0C
+#define GPIO2_ICR2                 GPIO2_BASE_ADDR+0x10
+#define GPIO2_IMR                  GPIO2_BASE_ADDR+0x14
+#define GPIO2_ISR                  GPIO2_BASE_ADDR+0x18
+#define GPIO2_EDGE_SEL             GPIO2_BASE_ADDR+0x1C
+
+#define GPIO3_DR                   GPIO3_BASE_ADDR+0x00
+#define GPIO3_GDIR                 GPIO3_BASE_ADDR+0x04
+#define GPIO3_PSR                  GPIO3_BASE_ADDR+0x08
+#define GPIO3_ICR1                 GPIO3_BASE_ADDR+0x0C
+#define GPIO3_ICR2                 GPIO3_BASE_ADDR+0x10
+#define GPIO3_IMR                  GPIO3_BASE_ADDR+0x14
+#define GPIO3_ISR                  GPIO3_BASE_ADDR+0x18
+#define GPIO3_EDGE_SEL             GPIO3_BASE_ADDR+0x1C
+
+#define GPIO4_DR                   GPIO4_BASE_ADDR+0x00
+#define GPIO4_GDIR                 GPIO4_BASE_ADDR+0x04
+#define GPIO4_PSR                  GPIO4_BASE_ADDR+0x08
+#define GPIO4_ICR1                 GPIO4_BASE_ADDR+0x0C
+#define GPIO4_ICR2                 GPIO4_BASE_ADDR+0x10
+#define GPIO4_IMR                  GPIO4_BASE_ADDR+0x14
+#define GPIO4_ISR                  GPIO4_BASE_ADDR+0x18
+#define GPIO4_EDGE_SEL             GPIO4_BASE_ADDR+0x1C
+
+#define GPIO5_DR                   GPIO5_BASE_ADDR+0x00
+#define GPIO5_GDIR                 GPIO5_BASE_ADDR+0x04
+#define GPIO5_PSR                  GPIO5_BASE_ADDR+0x08
+#define GPIO5_ICR1                 GPIO5_BASE_ADDR+0x0C
+#define GPIO5_ICR2                 GPIO5_BASE_ADDR+0x10
+#define GPIO5_IMR                  GPIO5_BASE_ADDR+0x14
+#define GPIO5_ISR                  GPIO5_BASE_ADDR+0x18
+#define GPIO5_EDGE_SEL             GPIO5_BASE_ADDR+0x1C
+
+#define GPIO6_DR                   GPIO6_BASE_ADDR+0x00
+#define GPIO6_GDIR                 GPIO6_BASE_ADDR+0x04
+#define GPIO6_PSR                  GPIO6_BASE_ADDR+0x08
+#define GPIO6_ICR1                 GPIO6_BASE_ADDR+0x0C
+#define GPIO6_ICR2                 GPIO6_BASE_ADDR+0x10
+#define GPIO6_IMR                  GPIO6_BASE_ADDR+0x14
+#define GPIO6_ISR                  GPIO6_BASE_ADDR+0x18
+#define GPIO6_EDGE_SEL             GPIO6_BASE_ADDR+0x1C
+
+#define GPIO7_DR                   GPIO7_BASE_ADDR+0x00
+#define GPIO7_GDIR                 GPIO7_BASE_ADDR+0x04
+#define GPIO7_PSR                  GPIO7_BASE_ADDR+0x08
+#define GPIO7_ICR1                 GPIO7_BASE_ADDR+0x0C
+#define GPIO7_ICR2                 GPIO7_BASE_ADDR+0x10
+#define GPIO7_IMR                  GPIO7_BASE_ADDR+0x14
+#define GPIO7_ISR                  GPIO7_BASE_ADDR+0x18
+#define GPIO7_EDGE_SEL             GPIO7_BASE_ADDR+0x1C
+
+#endif

bsp/imx6ul/platform/include/mx6ul/hardware.h

@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+/*!
+ * @file hardware.h
+ * @brief header file with chip defines to be included by all the tests/utils
+ *
+ * @ingroup diag_init
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+#include "soc_memory_map.h"
+#include "functions.h"
+#include "io.h"
+#include "iomux_define.h"
+#include "iomux_register.h"
+
+#include "iomux_config.h"
+#include "gpio_define.h"
+#include "ccm_pll_reg_define.h"
+#include "imx_i2c.h"
+#include "imx_spi.h"
+#include "imx_sata.h"
+#include "pmic.h"
+#include "regsgpmi.h"
+#include "regsapbh.h"
+
+#define ESDCTL_ESDSCR_OFFSET  0x1C
+// PLL definitions
+#define HW_ANADIG_USB1_PLL_480_CTRL_RW  (ANATOP_IPS_BASE_ADDR+0x10)
+#define HW_ANADIG_PLL_528_RW    (ANATOP_IPS_BASE_ADDR+0x30) 
+#define HW_ANADIG_PLL_528_NUM   (ANATOP_IPS_BASE_ADDR+0x50)
+#define HW_ANADIG_PLL_528_DENOM     (ANATOP_IPS_BASE_ADDR+0x60)
+#define HW_ANADIG_PFD_528_RW        (ANATOP_IPS_BASE_ADDR+0x100)
+#define HW_ANADIG_PLL_SYS_RW        (ANATOP_IPS_BASE_ADDR+0x000)
+
+#define HW_ANADIG_REG_CORE	(ANATOP_IPS_BASE_ADDR + 0x140)
+#define HW_ANADIG_REG_CORE_V_CORE_VALUE_mv(x)	((((x)-700)/25) << 0)
+#define HW_ANADIG_REG_CORE_V_SOC_VALUE_mv(x)	((((x)-700)/25) << 18)
+#define HW_ANADIG_REG_CORE_V_CORE_MSK		0x1F
+#define HW_ANADIG_REG_CORE_V_SOC_MSK		(0x1F << 18)
+
+// audio defines
+#define WM8960_I2C_DEV_ADDR 		(0x34>>1)
+#define WM8960_I2C_BASE_ADDR		I2C2_BASE_ADDR
+
+#define WM8958_I2C_DEV_ADDR 		(0x34>>1)
+#define WM8958_I2C_BASE_ADDR		I2C1_BASE_ADDR
+
+#define WM8962_I2C_DEV_ADDR 		(0x34>>1)
+#define WM8962_I2C_BASE_ADDR		I2C4_BASE_ADDR
+
+#define SGTL5000_I2C_BASE   I2C1_BASE_ADDR  // audio codec on i2c1
+#define SGTL5000_I2C_ID     0x0A
+
+// SGTL5000 specific register values
+#define CHIP_REF_CTRL_REG_VALUE 0x01FF  // VDDA/2
+#define CHIP_LINE_OUT_CTRL_REG_VALUE 0x0322 // VDDIO/2
+#define CHIP_LINE_OUT_VOL_REG_VALUE 0x0F0F  // based on VDDA and VDDIO values
+#define CHIP_CLK_TOP_CTRL_REG_VALUE 0   // pass through, Input OSC 13.5MHz, default configuration for sample rate, 48KHz
+#define CHIP_PLL_CTRL_REG_VALUE ((14 << 11) | (1154))
+#define CHIP_CLK_CTRL_REG_VALUE ((0x2 << 2) | (0x3))
+#define CHIP_CLK_CTRL_REG_MCLK_FREQ_VALUE 0x3   /*12MHz =256*Fs */
+#define CHIP_PLL_CTRL_REG_VALUE2     ((16 << 11) | (786))   // for CodecInit2
+
+#define SI476x_I2C_BASE    I2C2_BASE_ADDR
+#define SI476x_I2C_ID      (0xC6 >> 1)
+
+#define OS81050_I2C_BASE    I2C3_BASE_ADDR
+#define OS81050_I2C_ID      (0x40 >> 1)
+
+#define ADV7180_I2C_BASE    I2C3_BASE_ADDR
+#define ADV7180_I2C_ID      (0x42 >> 1)
+
+#if defined(SABRE_LITE)
+#define P1003_TSC_I2C_BASE  I2C3_BASE_ADDR
+#else //default SABRE_AI
+#define P1003_TSC_I2C_BASE  I2C2_BASE_ADDR
+#endif
+#define P1003_TSC_I2C_ID    4
+
+// MAX7310 I2C settings
+/* For the SABRE AI board which has 3 MAX7310 */
+#ifdef SABRE_AI
+#define MAX7310_NBR 3
+#define MAX7310_I2C_BASE_ID0  I2C3_BASE_ADDR
+#define MAX7310_I2C_ID0          0x30
+#define MAX7310_ID0_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID0_DEF_VAL      0xFF   // init value for the output
+    /* Number 1 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116,
+       PORT2_P81, PORT3_P101
+     */
+#define MAX7310_I2C_BASE_ID1  I2C3_BASE_ADDR
+#define MAX7310_I2C_ID1          0x32
+#define MAX7310_ID1_DEF_DIR      0x00   // init direction for the I/O
+    /*Set the max7310_id1 's default value for ctrl_x */
+#define MAX7310_ID1_DEF_VAL      0xE7   // init value for the output
+
+#define MAX7310_I2C_BASE_ID2  I2C3_BASE_ADDR
+#define MAX7310_I2C_ID2          0x34
+#define MAX7310_ID2_DEF_DIR      0x00   // init direction for the I/O
+    /*Set the max7310_id1 's default value for ctrl_x */
+#define MAX7310_ID2_DEF_VAL      0x57   // init value for the output
+/* For the EVB board which has 2 MAX7310 */
+#endif
+#ifdef EVB
+#define MAX7310_NBR 2
+    /* Number 1 controls: BACKLIGHT_ON, PORT3_P114, CPU_PER_RST_B, PORT3_P110,
+       PORT3_P105, PORT3_P112, PORT3_P107, PORT3_P109.
+     */
+#define MAX7310_I2C_BASE_ID0  I2C3_BASE_ADDR
+#define MAX7310_I2C_ID0     (0x36 >> 1)
+#define MAX7310_ID0_DEF_DIR      0x00   // init direction for the I/O
+#define MAX7310_ID0_DEF_VAL      0xFF   // init value for the output
+    /* Number 1 controls: CTRL_0, CTRL_1, CTRL_2, CTRL_3, CTRL_4, PORT3_P116,
+       PORT2_P81, PORT3_P101
+     */
+#define MAX7310_I2C_BASE_ID1  I2C3_BASE_ADDR
+#define MAX7310_I2C_ID1     (0x3E >> 1)
+#define MAX7310_ID1_DEF_DIR      0x00   // init direction for the I/O
+    /*Set the max7310_id1 's default value for ctrl_x */
+#define MAX7310_ID1_DEF_VAL      0x09   // init value for the output
+#endif
+/* use that defined for boards that doesn't have any MAX7310 */
+#if defined(SMART_DEVICE) || defined(SABRE_LITE)
+    /* dummy value for build */
+#define MAX7310_NBR 0
+#endif
+
+/* create an array of I2C requests for all used expanders on the board */
+struct imx_i2c_request max7310_i2c_req_array[MAX7310_NBR];
+
+#define MMA8450_I2C_ID      0x1C
+#define MMA8451_I2C_ID      0x1C
+#define MAG3112_I2C_ID      0x1D
+#define MAG3110_I2C_ID      0x0E
+#define ISL29023_I2C_ID	    0x44
+#define FXLS8471Q_I2C_ID    0x1E
+
+#define MAX11801_I2C_BASE	I2C3_BASE_ADDR
+#define MAX11801_I2C_ID     (0x90 >> 1)
+
+#ifdef SABRE_AI
+#define CS42888_I2C_BASE	I2C2_BASE_ADDR
+#endif
+#ifdef EVB
+#define CS42888_I2C_BASE	I2C1_BASE_ADDR
+#endif
+/* use that defined for boards that doesn't have any CS42888 */
+#if defined(SMART_DEVICE) || defined(SABRE_LITE)
+#define CS42888_I2C_BASE	DUMMY_VALUE_NOT_USED
+#endif
+#define CS42888_I2C_ID      (0x90 >> 1)
+
+#define AT24Cx_I2C_BASE		I2C3_BASE_ADDR
+#define AT24Cx_I2C_ID		0x50
+
+// USB test defines
+#define USBH1_BASE_ADDR     (USBOH2_USB_BASE_ADDR + 0x200)
+#define USBH2_BASE_ADDR     (USBOH2_USB_BASE_ADDR + 0x400)
+#define USBH3_BASE_ADDR     (USBOH2_USB_BASE_ADDR + 0x600)
+#define USB_OTG_MIRROR_REG  (USBOH2_USB_BASE_ADDR+0x804)
+#define USB_CLKONOFF_CTRL   (USBOH2_USB_BASE_ADDR+0x824)
+#define USBH2_VIEWPORT      (USBH2_BASE_ADDR + 0x170)
+#define USB_CTRL_1          (USBOH2_USB_BASE_ADDR + 0x810)
+#define UH2_PORTSC1         (USBH2_BASE_ADDR + 0x184)
+
+#define IIM_BASE_ADDR       0x0
+#define M4IF_REGISTERS_BASE_ADDR 0x0
+#define ESDHC1_BASE_ADDR 0x0
+#define ESDHC2_BASE_ADDR 0x1
+#define ESDHC3_BASE_ADDR 0x2
+#define DPLLIP1_BASE_ADDR 0x0
+#define DPLLIP2_BASE_ADDR 0x1
+#define DPLLIP3_BASE_ADDR 0x2
+#define DPLLIP4_BASE_ADDR 0x3
+
+#define USDHC_ADMA_BUFFER 0x00910000
+
+/*qh and td pointers defintion*/
+#define QH_BUFFER               0x00908000  // internal RAM
+#define TD_BUFFER               0x00908100  // internal RAM
+
+// input CKIL clock
+#define __CLK_TCK   32768
+#define FREQ_24MHZ               24000000
+#define CKIH                            22579200
+
+// I2C specific defines
+// For LTC Board ID
+#define BOARD_ID_I2C_BASE I2C2_BASE_ADDR
+
+// register defines for the SRTC function of the SNVS
+#define SRTC_LPSCMR         (SNVS_BASE_ADDR + 0x50)
+#define SRTC_LPSCLR         (SNVS_BASE_ADDR + 0x54)
+#define SRTC_LPCR           (SNVS_BASE_ADDR + 0x38)
+#define SRTC_HPCMR          (SNVS_BASE_ADDR + 0x24)
+#define SRTC_HPCLR          (SNVS_BASE_ADDR + 0x28)
+#define SRTC_HPCR           (SNVS_BASE_ADDR + 0x08)
+
+//provide macros for test enter and exit outputs
+#define TEST_ENTER(name) printf ("Running test: %s\n", name)
+
+#define TEST_EXIT(name)  do {printf (" ..Test: %s\n", name); \
+                                                } while (0)
+enum main_clocks {
+    CPU_CLK,
+    AHB_CLK,
+    IPG_CLK,
+    IPG_PER_CLK,
+    DDR_CLK,
+    NFC_CLK,
+    USB_CLK,
+    VPU_CLK,
+};
+
+enum peri_clocks {
+    UART1_BAUD,
+    UART2_BAUD,
+    UART3_BAUD,
+    UART4_BAUD,
+    SSI1_BAUD,
+    SSI2_BAUD,
+    CSI_BAUD,
+    MSTICK1_CLK,
+    MSTICK2_CLK,
+    SPI1_CLK = ECSPI1_BASE_ADDR,
+    SPI2_CLK = ECSPI2_BASE_ADDR,
+};
+
+enum plls {
+    PLL1,
+    PLL2,
+    PLL3,
+    PLL4,
+};
+
+enum display_type {
+    DISP_DEV_NULL = 0,
+    DISP_DEV_TFTLCD,
+    DISP_DEV_LVDS,
+    DISP_DEV_VGA,
+    DISP_DEV_HDMI,
+    DISP_DEV_TV,
+    DISP_DEV_MIPI,
+};
+
+enum lvds_panel_bit_mode {
+    LVDS_PANEL_18BITS_MODE = 0x0,
+    LVDS_PANEL_24BITS_MODE = 0x1,
+};
+
+enum shift_reg_bit{
+	HDMI_nRST = 1,
+	ENET1_nRST = 2,
+	ENET2_nRST = 4,
+	CAN1_2_STBY = 8,
+	BT_nPWD = 16,
+	CSI_RST = 32,
+	CSI_PWDN = 64,
+	LCD_nPWREN = 128,
+	ALL_BITS = 0xFF,
+};
+
+void set_shift_reg(enum shift_reg_bit b, bool state);
+void peri_pwr_en(bool enable);
+void pf0100_enable_vgen5_3v3(void);
+void pf0100_disable_vgen5_3v3(void);
+void pf0100_enable_vgen2_1v5(void);
+void pf0100_disable_vgen2_1v5(void);
+void sd3_reset(void);
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+void clock_setup(u32 core_clk, u32 ahb_div);
+void io_cfg_i2c(u32 module_base);
+void usdhc_iomux_config(u32 module_base);
+bool usdhc_card_detected(unsigned int base_address);
+bool usdhc_write_protected(unsigned int base_address);
+void freq_populate(void);
+void show_freq(void);
+void show_ddr_config(void);
+void board_init(void);
+void reset_usb_hub(void);
+void usb_clock_enable(void);
+void usb_init_phy(void);
+void imx_enet_setup(void);
+void esai_iomux(void);
+void gpmi_nand_pinmux_config(void);
+void gpmi_nand_clk_setup(void);
+void imx_enet_iomux(int id);
+void imx_enet_power_on_reset(void);
+void imx_enet_hw_init(int id);
+void usb_iomux_config(void);
+void usb_vbus_power_on(void);
+void usb_vbus_power_off(void);
+void imx_ar8031_reset(void);
+void imx_KSZ9021RN_reset(void);
+int read_mac(u8 * mac_data);
+int program_mac(u8 * fuse_data);
+void mlb_io_config(void);
+int esai_codec_power_on(void);
+void hdmi_pgm_iomux(void);
+void hdmi_clock_set(unsigned int pclk);
+void lvds_power_on(char *panel_name);
+void sata_clock_disable(void);
+void sata_power_off(void);
+void weim_nor_flash_cs_setup(void);
+void show_boot_switch_info(void);
+void hdmi_power_on(void);
+void camera_power_on(void);
+void camera_power_off(void);
+void camera_reset(void);
+void camera_clock_setting(void);
+void audio_codec_power_on(void);
+
+extern void gpio_backlight_lvds_en(void);
+extern void init_clock(u32 rate);
+extern void hal_delay_us(unsigned int);
+extern int max7310_init(unsigned int, unsigned int, unsigned int);
+extern void max7310_set_gpio_output(unsigned int, unsigned int, unsigned int);
+
+extern void AUDMUXRoute(int intPort, int extPort, int Master);  // defined in ssi.c driver
+
+extern int mx6ul_evk_show_headphone(void);
+
+extern imx_spi_init_func_t spi_init_flash;
+extern imx_spi_xfer_func_t spi_xfer_flash;
+extern struct imx_spi_dev imx_spi_nor;
+
+extern u32 usbh_EHCI_test_mode_base;
+extern u32 usbh_dev_enum_test_base;
+extern u32 usbo_dev_enum_test_base;
+extern u32 usbh_hub251x_test_base;
+extern int ipu_display_panel[];
+extern u32 ddr_density, ddr_num_of_cs;
+extern u32 mmcsd_bus_width, mmc_sd_base_address;
+
+/* list of tests */
+extern int spi_nor_test_enable;
+extern int pmic_mc13892_test_enable;
+extern int pf0100_i2c_device_id_test_enable;
+extern int fec_test_enable;
+extern int lan9220_test_enable;
+extern int enet_test_enable;
+extern int ksz8081rnb_test_enable;
+extern int KSZ9021RN_test_enable;
+extern int ds90ur124_test_enable;
+extern int adv7180_test_enable;
+extern int ard_mb_reset_test_enable;
+extern int ard_mb_expander_reset_test_enable;
+extern int si476x_test_enable;
+extern int esai_test_enable;
+extern int weim_nor_flash_test_enable;
+extern int max7310_i2c_device_id_test_enable;
+extern int nand_test_enable;
+extern int usbh_EHCI_test_mode_test_enable;
+extern int usbh_dev_enum_test_enable;
+extern int usbo_dev_enum_test_enable;
+extern int usbh_hub251x_test_enable;
+extern int i2s_audio_test_enable;
+extern int gps_test_enable;
+extern int gpio_keyboard_test_enable;
+extern int smbus_test_enable;
+extern int touch_screen_test_enable;
+extern int ipu_display_test_enable;
+extern int ddr_test_enable;
+extern int mlb_os81050_test_enable;
+extern int i2c_id_check_test_enable;
+extern int i2c_device_id_check_mag3112_test_enable;
+extern int i2c_device_id_check_mag3110_test_enable;
+extern int i2c_device_id_check_isl29023_test_enable;
+extern int i2c_device_id_check_mma8451_test_enable;
+extern int i2c_device_id_check_cs42888_test_enable;
+extern int i2c_device_id_check_p1003_test_enable;
+extern int mmcsd_test_enable;
+extern int eeprom_test_enable;
+extern int mipi_test_enable;
+extern int touch_button_test_enable;
+extern int android_buttons_test_enable;
+extern int can_test_enable;
+extern int camera_flashtest_enable;
+extern int camera_test_enable;
+extern int epd_test_enable;
+extern int lcd_test_enable;
+extern int lvds_test_enable;
+
+#define PMIC_MC13892_I2C_BASE       I2C2_BASE_ADDR
+#define PMIC_LTC3589_I2C_BASE       I2C2_BASE_ADDR
+#define PMIC_DA9053_I2C_BASE        I2C1_BASE_ADDR
+#define PMIC_PF0100_I2C_BASE      I2C1_BASE_ADDR
+
+#endif /*HARDWARE_H_ */

bsp/imx6ul/platform/include/mx6ul/hdmi_regs.h

@@ -0,0 +1,555 @@
+/*
+ * Copyright (C) 2010-2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+ */
+
+/*!
+ * @file hdmi_regs.h
+ * @brief registers defination of hdmi tx module.
+ * @ingroup diag_hdmi
+ */
+
+#ifndef __HDMI_REGS_H__
+#define __HDMI_REGS_H__
+
+#include "soc_memory_map.h"
+
+// ANALOG registers
+#define HW_ANADIG_PLL_VIDEO         ANATOP_BASE_ADDR + 0x0a0
+#define HW_ANADIG_PLL_VIDEO_NUM     ANATOP_BASE_ADDR + 0x0b0
+#define HW_ANADIG_PLL_VIDEO_DENUM   ANATOP_BASE_ADDR + 0x0c0
+
+// HDMI PHY REGISTERS
+#define CREGS_PLL_DIV_ADDR              0x06
+#define CREGS_PLL_GMP_CNTRL_ADDR        0x15
+#define CREGS_PLL_PROP_INT_CNTRL_ADDR   0x10
+#define CREGS_PATTERNGEN                0x1B
+#define CREGS_PGMODE                    0x1C
+#define CREGS_DIGTXMODE                 0x1E
+
+//
+// Hdmi controller registers 
+//
+
+// Identification Registers
+#define HDMI_DESIGN_ID              HDMI_ARB_BASE_ADDR+0x0000
+#define HDMI_REVISION_ID            HDMI_ARB_BASE_ADDR+0x0001
+#define HDMI_PRODUCT_ID0            HDMI_ARB_BASE_ADDR+0x0002
+#define HDMI_PRODUCT_ID1            HDMI_ARB_BASE_ADDR+0x0003
+#define HDMI_CONFIG0_ID             HDMI_ARB_BASE_ADDR+0x0004
+#define HDMI_CONFIG1_ID             HDMI_ARB_BASE_ADDR+0x0005
+#define HDMI_CONFIG2_ID             HDMI_ARB_BASE_ADDR+0x0006
+#define HDMI_CONFIG3_ID             HDMI_ARB_BASE_ADDR+0x0007
+
+// Interrupt Registers
+#define HDMI_IH_FC_STAT0            HDMI_ARB_BASE_ADDR+0x0100
+#define HDMI_IH_FC_STAT1            HDMI_ARB_BASE_ADDR+0x0101
+#define HDMI_IH_FC_STAT2            HDMI_ARB_BASE_ADDR+0x0102
+#define HDMI_IH_AS_STAT0            HDMI_ARB_BASE_ADDR+0x0103
+#define HDMI_IH_PHY_STAT0           HDMI_ARB_BASE_ADDR+0x0104
+#define HDMI_IH_I2CM_STAT0          HDMI_ARB_BASE_ADDR+0x0105
+#define HDMI_IH_CEC_STAT0           HDMI_ARB_BASE_ADDR+0x0106
+#define HDMI_IH_VP_STAT0            HDMI_ARB_BASE_ADDR+0x0107
+#define HDMI_IH_I2CMPHY_STAT0       HDMI_ARB_BASE_ADDR+0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0     HDMI_ARB_BASE_ADDR+0x0180
+#define HDMI_IH_MUTE_FC_STAT1       HDMI_ARB_BASE_ADDR+0x0181
+#define HDMI_IH_MUTE_FC_STAT2       HDMI_ARB_BASE_ADDR+0x0182
+#define HDMI_IH_MUTE_AS_STAT0       HDMI_ARB_BASE_ADDR+0x0183
+#define HDMI_IH_MUTE_PHY_STAT0      HDMI_ARB_BASE_ADDR+0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0     HDMI_ARB_BASE_ADDR+0x0185
+#define HDMI_IH_MUTE_CEC_STAT0      HDMI_ARB_BASE_ADDR+0x0186
+#define HDMI_IH_MUTE_VP_STAT0       HDMI_ARB_BASE_ADDR+0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0  HDMI_ARB_BASE_ADDR+0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0  HDMI_ARB_BASE_ADDR+0x0189
+#define HDMI_IH_MUTE                HDMI_ARB_BASE_ADDR+0x01FF
+
+// Video Sample Registers
+#define HDMI_TX_INVID0              HDMI_ARB_BASE_ADDR+0x0200
+#define HDMI_TX_INSTUFFING          HDMI_ARB_BASE_ADDR+0x0201
+#define HDMI_TX_GYDATA0             HDMI_ARB_BASE_ADDR+0x0202
+#define HDMI_TX_GYDATA1             HDMI_ARB_BASE_ADDR+0x0203
+#define HDMI_TX_RCRDATA0            HDMI_ARB_BASE_ADDR+0x0204
+#define HDMI_TX_RCRDATA1            HDMI_ARB_BASE_ADDR+0x0205
+#define HDMI_TX_BCBDATA0            HDMI_ARB_BASE_ADDR+0x0206
+#define HDMI_TX_BCBDATA1            HDMI_ARB_BASE_ADDR+0x0207
+
+// Video Packetizer Registers
+#define HDMI_VP_STATUS              HDMI_ARB_BASE_ADDR+0x0800
+#define HDMI_VP_PR_CD               HDMI_ARB_BASE_ADDR+0x0801
+#define HDMI_VP_STUFF               HDMI_ARB_BASE_ADDR+0x0802
+#define HDMI_VP_REMAP               HDMI_ARB_BASE_ADDR+0x0803
+#define HDMI_VP_CONF                HDMI_ARB_BASE_ADDR+0x0804
+#define HDMI_VP_STAT                HDMI_ARB_BASE_ADDR+0x0805
+#define HDMI_VP_INT                 HDMI_ARB_BASE_ADDR+0x0806
+#define HDMI_VP_MASK                HDMI_ARB_BASE_ADDR+0x0807
+#define HDMI_VP_POL                 HDMI_ARB_BASE_ADDR+0x0808
+
+// Frame Composer Registers
+#define HDMI_FC_INVIDCONF           HDMI_ARB_BASE_ADDR+0x1000
+#define HDMI_FC_INHACTV0            HDMI_ARB_BASE_ADDR+0x1001
+#define HDMI_FC_INHACTV1            HDMI_ARB_BASE_ADDR+0x1002
+#define HDMI_FC_INHBLANK0           HDMI_ARB_BASE_ADDR+0x1003
+#define HDMI_FC_INHBLANK1           HDMI_ARB_BASE_ADDR+0x1004
+#define HDMI_FC_INVACTV0            HDMI_ARB_BASE_ADDR+0x1005
+#define HDMI_FC_INVACTV1            HDMI_ARB_BASE_ADDR+0x1006
+#define HDMI_FC_INVBLANK            HDMI_ARB_BASE_ADDR+0x1007
+#define HDMI_FC_HSYNCINDELAY0       HDMI_ARB_BASE_ADDR+0x1008
+#define HDMI_FC_HSYNCINDELAY1       HDMI_ARB_BASE_ADDR+0x1009
+#define HDMI_FC_HSYNCINWIDTH0       HDMI_ARB_BASE_ADDR+0x100A
+#define HDMI_FC_HSYNCINWIDTH1       HDMI_ARB_BASE_ADDR+0x100B
+#define HDMI_FC_VSYNCINDELAY        HDMI_ARB_BASE_ADDR+0x100C
+#define HDMI_FC_VSYNCINWIDTH        HDMI_ARB_BASE_ADDR+0x100D
+#define HDMI_FC_INFREQ0             HDMI_ARB_BASE_ADDR+0x100E
+#define HDMI_FC_INFREQ1             HDMI_ARB_BASE_ADDR+0x100F
+#define HDMI_FC_INFREQ2             HDMI_ARB_BASE_ADDR+0x1010
+#define HDMI_FC_CTRLDUR             HDMI_ARB_BASE_ADDR+0x1011
+#define HDMI_FC_EXCTRLDUR           HDMI_ARB_BASE_ADDR+0x1012
+#define HDMI_FC_EXCTRLSPAC          HDMI_ARB_BASE_ADDR+0x1013
+#define HDMI_FC_CH0PREAM            HDMI_ARB_BASE_ADDR+0x1014
+#define HDMI_FC_CH1PREAM            HDMI_ARB_BASE_ADDR+0x1015
+#define HDMI_FC_CH2PREAM            HDMI_ARB_BASE_ADDR+0x1016
+#define HDMI_FC_AVICONF3            HDMI_ARB_BASE_ADDR+0x1017
+#define HDMI_FC_GCP                 HDMI_ARB_BASE_ADDR+0x1018
+#define HDMI_FC_AVICONF0            HDMI_ARB_BASE_ADDR+0x1019
+#define HDMI_FC_AVICONF1            HDMI_ARB_BASE_ADDR+0x101A
+#define HDMI_FC_AVICONF2            HDMI_ARB_BASE_ADDR+0x101B
+#define HDMI_FC_AVIVID              HDMI_ARB_BASE_ADDR+0x101C
+#define HDMI_FC_AVIETB0             HDMI_ARB_BASE_ADDR+0x101D
+#define HDMI_FC_AVIETB1             HDMI_ARB_BASE_ADDR+0x101E
+#define HDMI_FC_AVISBB0             HDMI_ARB_BASE_ADDR+0x101F
+#define HDMI_FC_AVISBB1             HDMI_ARB_BASE_ADDR+0x1020
+#define HDMI_FC_AVIELB0             HDMI_ARB_BASE_ADDR+0x1021
+#define HDMI_FC_AVIELB1             HDMI_ARB_BASE_ADDR+0x1022
+#define HDMI_FC_AVISRB0             HDMI_ARB_BASE_ADDR+0x1023
+#define HDMI_FC_AVISRB1             HDMI_ARB_BASE_ADDR+0x1024
+#define HDMI_FC_AUDICONF0           HDMI_ARB_BASE_ADDR+0x1025
+#define HDMI_FC_AUDICONF1           HDMI_ARB_BASE_ADDR+0x1026
+#define HDMI_FC_AUDICONF2           HDMI_ARB_BASE_ADDR+0x1027
+#define HDMI_FC_AUDICONF3           HDMI_ARB_BASE_ADDR+0x1028
+#define HDMI_FC_VSDIEEEID0          HDMI_ARB_BASE_ADDR+0x1029
+#define HDMI_FC_VSDSIZE             HDMI_ARB_BASE_ADDR+0x102A
+#define HDMI_FC_VSDIEEEID1          HDMI_ARB_BASE_ADDR+0x1030
+#define HDMI_FC_VSDIEEEID2          HDMI_ARB_BASE_ADDR+0x1031
+#define HDMI_FC_VSDPAYLOAD0         HDMI_ARB_BASE_ADDR+0x1032
+#define HDMI_FC_VSDPAYLOAD1         HDMI_ARB_BASE_ADDR+0x1033
+#define HDMI_FC_VSDPAYLOAD2         HDMI_ARB_BASE_ADDR+0x1034
+#define HDMI_FC_VSDPAYLOAD3         HDMI_ARB_BASE_ADDR+0x1035
+#define HDMI_FC_VSDPAYLOAD4         HDMI_ARB_BASE_ADDR+0x1036
+#define HDMI_FC_VSDPAYLOAD5         HDMI_ARB_BASE_ADDR+0x1037
+#define HDMI_FC_VSDPAYLOAD6         HDMI_ARB_BASE_ADDR+0x1038
+#define HDMI_FC_VSDPAYLOAD7         HDMI_ARB_BASE_ADDR+0x1039
+#define HDMI_FC_VSDPAYLOAD8         HDMI_ARB_BASE_ADDR+0x103A
+#define HDMI_FC_VSDPAYLOAD9         HDMI_ARB_BASE_ADDR+0x103B
+#define HDMI_FC_VSDPAYLOAD10        HDMI_ARB_BASE_ADDR+0x103C
+#define HDMI_FC_VSDPAYLOAD11        HDMI_ARB_BASE_ADDR+0x103D
+#define HDMI_FC_VSDPAYLOAD12        HDMI_ARB_BASE_ADDR+0x103E
+#define HDMI_FC_VSDPAYLOAD13        HDMI_ARB_BASE_ADDR+0x103F
+#define HDMI_FC_VSDPAYLOAD14        HDMI_ARB_BASE_ADDR+0x1040
+#define HDMI_FC_VSDPAYLOAD15        HDMI_ARB_BASE_ADDR+0x1041
+#define HDMI_FC_VSDPAYLOAD16        HDMI_ARB_BASE_ADDR+0x1042
+#define HDMI_FC_VSDPAYLOAD17        HDMI_ARB_BASE_ADDR+0x1043
+#define HDMI_FC_VSDPAYLOAD18        HDMI_ARB_BASE_ADDR+0x1044
+#define HDMI_FC_VSDPAYLOAD19        HDMI_ARB_BASE_ADDR+0x1045
+#define HDMI_FC_VSDPAYLOAD20        HDMI_ARB_BASE_ADDR+0x1046
+#define HDMI_FC_VSDPAYLOAD21        HDMI_ARB_BASE_ADDR+0x1047
+#define HDMI_FC_VSDPAYLOAD22        HDMI_ARB_BASE_ADDR+0x1048
+#define HDMI_FC_VSDPAYLOAD23        HDMI_ARB_BASE_ADDR+0x1049
+#define HDMI_FC_SPDVENDORNAME0      HDMI_ARB_BASE_ADDR+0x104A
+#define HDMI_FC_SPDVENDORNAME1      HDMI_ARB_BASE_ADDR+0x104B
+#define HDMI_FC_SPDVENDORNAME2      HDMI_ARB_BASE_ADDR+0x104C
+#define HDMI_FC_SPDVENDORNAME3      HDMI_ARB_BASE_ADDR+0x104D
+#define HDMI_FC_SPDVENDORNAME4      HDMI_ARB_BASE_ADDR+0x104E
+#define HDMI_FC_SPDVENDORNAME5      HDMI_ARB_BASE_ADDR+0x104F
+#define HDMI_FC_SPDVENDORNAME6      HDMI_ARB_BASE_ADDR+0x1050
+#define HDMI_FC_SPDVENDORNAME7      HDMI_ARB_BASE_ADDR+0x1051
+#define HDMI_FC_SDPPRODUCTNAME0     HDMI_ARB_BASE_ADDR+0x1052
+#define HDMI_FC_SDPPRODUCTNAME1     HDMI_ARB_BASE_ADDR+0x1053
+#define HDMI_FC_SDPPRODUCTNAME2     HDMI_ARB_BASE_ADDR+0x1054
+#define HDMI_FC_SDPPRODUCTNAME3     HDMI_ARB_BASE_ADDR+0x1055
+#define HDMI_FC_SDPPRODUCTNAME4     HDMI_ARB_BASE_ADDR+0x1056
+#define HDMI_FC_SDPPRODUCTNAME5     HDMI_ARB_BASE_ADDR+0x1057
+#define HDMI_FC_SDPPRODUCTNAME6     HDMI_ARB_BASE_ADDR+0x1058
+#define HDMI_FC_SDPPRODUCTNAME7     HDMI_ARB_BASE_ADDR+0x1059
+#define HDMI_FC_SDPPRODUCTNAME8     HDMI_ARB_BASE_ADDR+0x105A
+#define HDMI_FC_SDPPRODUCTNAME9     HDMI_ARB_BASE_ADDR+0x105B
+#define HDMI_FC_SDPPRODUCTNAME10    HDMI_ARB_BASE_ADDR+0x105C
+#define HDMI_FC_SDPPRODUCTNAME11    HDMI_ARB_BASE_ADDR+0x105D
+#define HDMI_FC_SDPPRODUCTNAME12    HDMI_ARB_BASE_ADDR+0x105E
+#define HDMI_FC_SDPPRODUCTNAME13    HDMI_ARB_BASE_ADDR+0x105F
+#define HDMI_FC_SDPPRODUCTNAME14    HDMI_ARB_BASE_ADDR+0x1060
+#define HDMI_FC_SPDPRODUCTNAME15    HDMI_ARB_BASE_ADDR+0x1061
+#define HDMI_FC_SPDDEVICEINF        HDMI_ARB_BASE_ADDR+0x1062
+#define HDMI_FC_AUDSCONF            HDMI_ARB_BASE_ADDR+0x1063
+#define HDMI_FC_AUDSSTAT            HDMI_ARB_BASE_ADDR+0x1064
+#define HDMI_FC_AUDSV               HDMI_ARB_BASE_ADDR+0x1065
+#define HDMI_FC_AUDSU               HDMI_ARB_BASE_ADDR+0x1066
+#define HDMI_FC_AUDSCHNLS0          HDMI_ARB_BASE_ADDR+0x1067
+#define HDMI_FC_AUDSCHNLS1          HDMI_ARB_BASE_ADDR+0x1068
+#define HDMI_FC_AUDSCHNLS2          HDMI_ARB_BASE_ADDR+0x1069
+#define HDMI_FC_AUDSCHNLS3          HDMI_ARB_BASE_ADDR+0x106A
+#define HDMI_FC_AUDSCHNLS4          HDMI_ARB_BASE_ADDR+0x106B
+#define HDMI_FC_AUDSCHNLS5          HDMI_ARB_BASE_ADDR+0x106C
+#define HDMI_FC_AUDSCHNLS6          HDMI_ARB_BASE_ADDR+0x106D
+#define HDMI_FC_AUDSCHNLS7          HDMI_ARB_BASE_ADDR+0x106E
+#define HDMI_FC_AUDSCHNLS8          HDMI_ARB_BASE_ADDR+0x106F
+#define HDMI_FC_DATACH0FILL         HDMI_ARB_BASE_ADDR+0x1070
+#define HDMI_FC_DATACH1FILL         HDMI_ARB_BASE_ADDR+0x1071
+#define HDMI_FC_DATACH2FILL         HDMI_ARB_BASE_ADDR+0x1072
+#define HDMI_FC_CTRLQHIGH           HDMI_ARB_BASE_ADDR+0x1073
+#define HDMI_FC_CTRLQLOW            HDMI_ARB_BASE_ADDR+0x1074
+#define HDMI_FC_ACP0                HDMI_ARB_BASE_ADDR+0x1075
+#define HDMI_FC_ACP28               HDMI_ARB_BASE_ADDR+0x1076
+#define HDMI_FC_ACP27               HDMI_ARB_BASE_ADDR+0x1077
+#define HDMI_FC_ACP26               HDMI_ARB_BASE_ADDR+0x1078
+#define HDMI_FC_ACP25               HDMI_ARB_BASE_ADDR+0x1079
+#define HDMI_FC_ACP24               HDMI_ARB_BASE_ADDR+0x107A
+#define HDMI_FC_ACP23               HDMI_ARB_BASE_ADDR+0x107B
+#define HDMI_FC_ACP22               HDMI_ARB_BASE_ADDR+0x107C
+#define HDMI_FC_ACP21               HDMI_ARB_BASE_ADDR+0x107D
+#define HDMI_FC_ACP20               HDMI_ARB_BASE_ADDR+0x107E
+#define HDMI_FC_ACP19               HDMI_ARB_BASE_ADDR+0x107F
+#define HDMI_FC_ACP18               HDMI_ARB_BASE_ADDR+0x1080
+#define HDMI_FC_ACP17               HDMI_ARB_BASE_ADDR+0x1081
+#define HDMI_FC_ACP16               HDMI_ARB_BASE_ADDR+0x1082
+#define HDMI_FC_ACP15               HDMI_ARB_BASE_ADDR+0x1083
+#define HDMI_FC_ACP14               HDMI_ARB_BASE_ADDR+0x1084
+#define HDMI_FC_ACP13               HDMI_ARB_BASE_ADDR+0x1085
+#define HDMI_FC_ACP12               HDMI_ARB_BASE_ADDR+0x1086
+#define HDMI_FC_ACP11               HDMI_ARB_BASE_ADDR+0x1087
+#define HDMI_FC_ACP10               HDMI_ARB_BASE_ADDR+0x1088
+#define HDMI_FC_ACP9                HDMI_ARB_BASE_ADDR+0x1089
+#define HDMI_FC_ACP8                HDMI_ARB_BASE_ADDR+0x108A
+#define HDMI_FC_ACP7                HDMI_ARB_BASE_ADDR+0x108B
+#define HDMI_FC_ACP6                HDMI_ARB_BASE_ADDR+0x108C
+#define HDMI_FC_ACP5                HDMI_ARB_BASE_ADDR+0x108D
+#define HDMI_FC_ACP4                HDMI_ARB_BASE_ADDR+0x108E
+#define HDMI_FC_ACP3                HDMI_ARB_BASE_ADDR+0x108F
+#define HDMI_FC_ACP2                HDMI_ARB_BASE_ADDR+0x1090
+#define HDMI_FC_ACP1                HDMI_ARB_BASE_ADDR+0x1091
+#define HDMI_FC_ISCR1_0             HDMI_ARB_BASE_ADDR+0x1092
+#define HDMI_FC_ISCR1_16            HDMI_ARB_BASE_ADDR+0x1093
+#define HDMI_FC_ISCR1_15            HDMI_ARB_BASE_ADDR+0x1094
+#define HDMI_FC_ISCR1_14            HDMI_ARB_BASE_ADDR+0x1095
+#define HDMI_FC_ISCR1_13            HDMI_ARB_BASE_ADDR+0x1096
+#define HDMI_FC_ISCR1_12            HDMI_ARB_BASE_ADDR+0x1097
+#define HDMI_FC_ISCR1_11            HDMI_ARB_BASE_ADDR+0x1098
+#define HDMI_FC_ISCR1_10            HDMI_ARB_BASE_ADDR+0x1099
+#define HDMI_FC_ISCR1_9             HDMI_ARB_BASE_ADDR+0x109A
+#define HDMI_FC_ISCR1_8             HDMI_ARB_BASE_ADDR+0x109B
+#define HDMI_FC_ISCR1_7             HDMI_ARB_BASE_ADDR+0x109C
+#define HDMI_FC_ISCR1_6             HDMI_ARB_BASE_ADDR+0x109D
+#define HDMI_FC_ISCR1_5             HDMI_ARB_BASE_ADDR+0x109E
+#define HDMI_FC_ISCR1_4             HDMI_ARB_BASE_ADDR+0x109F
+#define HDMI_FC_ISCR1_3             HDMI_ARB_BASE_ADDR+0x10A0
+#define HDMI_FC_ISCR1_2             HDMI_ARB_BASE_ADDR+0x10A1
+#define HDMI_FC_ISCR1_1             HDMI_ARB_BASE_ADDR+0x10A2
+#define HDMI_FC_ISCR2_15            HDMI_ARB_BASE_ADDR+0x10A3
+#define HDMI_FC_ISCR2_14            HDMI_ARB_BASE_ADDR+0x10A4
+#define HDMI_FC_ISCR2_13            HDMI_ARB_BASE_ADDR+0x10A5
+#define HDMI_FC_ISCR2_12            HDMI_ARB_BASE_ADDR+0x10A6
+#define HDMI_FC_ISCR2_11            HDMI_ARB_BASE_ADDR+0x10A7
+#define HDMI_FC_ISCR2_10            HDMI_ARB_BASE_ADDR+0x10A8
+#define HDMI_FC_ISCR2_9             HDMI_ARB_BASE_ADDR+0x10A9
+#define HDMI_FC_ISCR2_8             HDMI_ARB_BASE_ADDR+0x10AA
+#define HDMI_FC_ISCR2_7             HDMI_ARB_BASE_ADDR+0x10AB
+#define HDMI_FC_ISCR2_6             HDMI_ARB_BASE_ADDR+0x10AC
+#define HDMI_FC_ISCR2_5             HDMI_ARB_BASE_ADDR+0x10AD
+#define HDMI_FC_ISCR2_4             HDMI_ARB_BASE_ADDR+0x10AE
+#define HDMI_FC_ISCR2_3             HDMI_ARB_BASE_ADDR+0x10AF
+#define HDMI_FC_ISCR2_2             HDMI_ARB_BASE_ADDR+0x10B0
+#define HDMI_FC_ISCR2_1             HDMI_ARB_BASE_ADDR+0x10B1
+#define HDMI_FC_ISCR2_0             HDMI_ARB_BASE_ADDR+0x10B2
+#define HDMI_FC_DATAUTO0            HDMI_ARB_BASE_ADDR+0x10B3
+#define HDMI_FC_DATAUTO1            HDMI_ARB_BASE_ADDR+0x10B4
+#define HDMI_FC_DATAUTO2            HDMI_ARB_BASE_ADDR+0x10B5
+#define HDMI_FC_DATMAN              HDMI_ARB_BASE_ADDR+0x10B6
+#define HDMI_FC_DATAUTO3            HDMI_ARB_BASE_ADDR+0x10B7
+#define HDMI_FC_RDRB0               HDMI_ARB_BASE_ADDR+0x10B8
+#define HDMI_FC_RDRB1               HDMI_ARB_BASE_ADDR+0x10B9
+#define HDMI_FC_RDRB2               HDMI_ARB_BASE_ADDR+0x10BA
+#define HDMI_FC_RDRB3               HDMI_ARB_BASE_ADDR+0x10BB
+#define HDMI_FC_RDRB4               HDMI_ARB_BASE_ADDR+0x10BC
+#define HDMI_FC_RDRB5               HDMI_ARB_BASE_ADDR+0x10BD
+#define HDMI_FC_RDRB6               HDMI_ARB_BASE_ADDR+0x10BE
+#define HDMI_FC_RDRB7               HDMI_ARB_BASE_ADDR+0x10BF
+#define HDMI_FC_STAT0               HDMI_ARB_BASE_ADDR+0x10D0
+#define HDMI_FC_INT0                HDMI_ARB_BASE_ADDR+0x10D1
+#define HDMI_FC_MASK0               HDMI_ARB_BASE_ADDR+0x10D2
+#define HDMI_FC_POL0                HDMI_ARB_BASE_ADDR+0x10D3
+#define HDMI_FC_STAT1               HDMI_ARB_BASE_ADDR+0x10D4
+#define HDMI_FC_INT1                HDMI_ARB_BASE_ADDR+0x10D5
+#define HDMI_FC_MASK1               HDMI_ARB_BASE_ADDR+0x10D6
+#define HDMI_FC_POL1                HDMI_ARB_BASE_ADDR+0x10D7
+#define HDMI_FC_STAT2               HDMI_ARB_BASE_ADDR+0x10D8
+#define HDMI_FC_INT2                HDMI_ARB_BASE_ADDR+0x10D9
+#define HDMI_FC_MASK2               HDMI_ARB_BASE_ADDR+0x10DA
+#define HDMI_FC_POL2                HDMI_ARB_BASE_ADDR+0x10DB
+#define HDMI_FC_PRCONF              HDMI_ARB_BASE_ADDR+0x10E0
+
+#define HDMI_FC_GMD_STAT            HDMI_ARB_BASE_ADDR+0x1100
+#define HDMI_FC_GMD_EN              HDMI_ARB_BASE_ADDR+0x1101
+#define HDMI_FC_GMD_UP              HDMI_ARB_BASE_ADDR+0x1102
+#define HDMI_FC_GMD_CONF            HDMI_ARB_BASE_ADDR+0x1103
+#define HDMI_FC_GMD_HB              HDMI_ARB_BASE_ADDR+0x1104
+#define HDMI_FC_GMD_PB0             HDMI_ARB_BASE_ADDR+0x1105
+#define HDMI_FC_GMD_PB1             HDMI_ARB_BASE_ADDR+0x1106
+#define HDMI_FC_GMD_PB2             HDMI_ARB_BASE_ADDR+0x1107
+#define HDMI_FC_GMD_PB3             HDMI_ARB_BASE_ADDR+0x1108
+#define HDMI_FC_GMD_PB4             HDMI_ARB_BASE_ADDR+0x1109
+#define HDMI_FC_GMD_PB5             HDMI_ARB_BASE_ADDR+0x110A
+#define HDMI_FC_GMD_PB6             HDMI_ARB_BASE_ADDR+0x110B
+#define HDMI_FC_GMD_PB7             HDMI_ARB_BASE_ADDR+0x110C
+#define HDMI_FC_GMD_PB8             HDMI_ARB_BASE_ADDR+0x110D
+#define HDMI_FC_GMD_PB9             HDMI_ARB_BASE_ADDR+0x110E
+#define HDMI_FC_GMD_PB10            HDMI_ARB_BASE_ADDR+0x110F
+#define HDMI_FC_GMD_PB11            HDMI_ARB_BASE_ADDR+0x1110
+#define HDMI_FC_GMD_PB12            HDMI_ARB_BASE_ADDR+0x1111
+#define HDMI_FC_GMD_PB13            HDMI_ARB_BASE_ADDR+0x1112
+#define HDMI_FC_GMD_PB14            HDMI_ARB_BASE_ADDR+0x1113
+#define HDMI_FC_GMD_PB15            HDMI_ARB_BASE_ADDR+0x1114
+#define HDMI_FC_GMD_PB16            HDMI_ARB_BASE_ADDR+0x1115
+#define HDMI_FC_GMD_PB17            HDMI_ARB_BASE_ADDR+0x1116
+#define HDMI_FC_GMD_PB18            HDMI_ARB_BASE_ADDR+0x1117
+#define HDMI_FC_GMD_PB19            HDMI_ARB_BASE_ADDR+0x1118
+#define HDMI_FC_GMD_PB20            HDMI_ARB_BASE_ADDR+0x1119
+#define HDMI_FC_GMD_PB21            HDMI_ARB_BASE_ADDR+0x111A
+#define HDMI_FC_GMD_PB22            HDMI_ARB_BASE_ADDR+0x111B
+#define HDMI_FC_GMD_PB23            HDMI_ARB_BASE_ADDR+0x111C
+#define HDMI_FC_GMD_PB24            HDMI_ARB_BASE_ADDR+0x111D
+#define HDMI_FC_GMD_PB25            HDMI_ARB_BASE_ADDR+0x111E
+#define HDMI_FC_GMD_PB26            HDMI_ARB_BASE_ADDR+0x111F
+#define HDMI_FC_GMD_PB27            HDMI_ARB_BASE_ADDR+0x1120
+
+#define HDMI_FC_DBGFORCE            HDMI_ARB_BASE_ADDR+0x1200
+#define HDMI_FC_DBGAUD0CH0          HDMI_ARB_BASE_ADDR+0x1201
+#define HDMI_FC_DBGAUD1CH0          HDMI_ARB_BASE_ADDR+0x1202
+#define HDMI_FC_DBGAUD2CH0          HDMI_ARB_BASE_ADDR+0x1203
+#define HDMI_FC_DBGAUD0CH1          HDMI_ARB_BASE_ADDR+0x1204
+#define HDMI_FC_DBGAUD1CH1          HDMI_ARB_BASE_ADDR+0x1205
+#define HDMI_FC_DBGAUD2CH1          HDMI_ARB_BASE_ADDR+0x1206
+#define HDMI_FC_DBGAUD0CH2          HDMI_ARB_BASE_ADDR+0x1207
+#define HDMI_FC_DBGAUD1CH2          HDMI_ARB_BASE_ADDR+0x1208
+#define HDMI_FC_DBGAUD2CH2          HDMI_ARB_BASE_ADDR+0x1209
+#define HDMI_FC_DBGAUD0CH3          HDMI_ARB_BASE_ADDR+0x120A
+#define HDMI_FC_DBGAUD1CH3          HDMI_ARB_BASE_ADDR+0x120B
+#define HDMI_FC_DBGAUD2CH3          HDMI_ARB_BASE_ADDR+0x120C
+#define HDMI_FC_DBGAUD0CH4          HDMI_ARB_BASE_ADDR+0x120D
+#define HDMI_FC_DBGAUD1CH4          HDMI_ARB_BASE_ADDR+0x120E
+#define HDMI_FC_DBGAUD2CH4          HDMI_ARB_BASE_ADDR+0x120F
+#define HDMI_FC_DBGAUD0CH5          HDMI_ARB_BASE_ADDR+0x1210
+#define HDMI_FC_DBGAUD1CH5          HDMI_ARB_BASE_ADDR+0x1211
+#define HDMI_FC_DBGAUD2CH5          HDMI_ARB_BASE_ADDR+0x1212
+#define HDMI_FC_DBGAUD0CH6          HDMI_ARB_BASE_ADDR+0x1213
+#define HDMI_FC_DBGAUD1CH6          HDMI_ARB_BASE_ADDR+0x1214
+#define HDMI_FC_DBGAUD2CH6          HDMI_ARB_BASE_ADDR+0x1215
+#define HDMI_FC_DBGAUD0CH7          HDMI_ARB_BASE_ADDR+0x1216
+#define HDMI_FC_DBGAUD1CH7          HDMI_ARB_BASE_ADDR+0x1217
+#define HDMI_FC_DBGAUD2CH7          HDMI_ARB_BASE_ADDR+0x1218
+#define HDMI_FC_DBGTMDS0            HDMI_ARB_BASE_ADDR+0x1219
+#define HDMI_FC_DBGTMDS1            HDMI_ARB_BASE_ADDR+0x121A
+#define HDMI_FC_DBGTMDS2            HDMI_ARB_BASE_ADDR+0x121B
+
+// HDMI Source PHY Registers
+#define HDMI_PHY_CONF0                  HDMI_ARB_BASE_ADDR+0x3000
+#define HDMI_PHY_TST0                   HDMI_ARB_BASE_ADDR+0x3001
+#define HDMI_PHY_TST1                   HDMI_ARB_BASE_ADDR+0x3002
+#define HDMI_PHY_TST2                   HDMI_ARB_BASE_ADDR+0x3003
+#define HDMI_PHY_STAT0                  HDMI_ARB_BASE_ADDR+0x3004
+#define HDMI_PHY_INT0                   HDMI_ARB_BASE_ADDR+0x3005
+#define HDMI_PHY_MASK0                  HDMI_ARB_BASE_ADDR+0x3006
+#define HDMI_PHY_POL0                   HDMI_ARB_BASE_ADDR+0x3007
+
+// HDMI Master PHY Registers
+#define HDMI_PHY_I2CM_SLAVE_ADDR             HDMI_ARB_BASE_ADDR+0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR           HDMI_ARB_BASE_ADDR+0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR           HDMI_ARB_BASE_ADDR+0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR           HDMI_ARB_BASE_ADDR+0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR           HDMI_ARB_BASE_ADDR+0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR           HDMI_ARB_BASE_ADDR+0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR         HDMI_ARB_BASE_ADDR+0x3026
+#define HDMI_PHY_I2CM_INT_ADDR               HDMI_ARB_BASE_ADDR+0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR            HDMI_ARB_BASE_ADDR+0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR               HDMI_ARB_BASE_ADDR+0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR          HDMI_ARB_BASE_ADDR+0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x3032
+
+// Generic Parallel Audio Interface Registers
+#define HDMI_GP_CONF0               HDMI_ARB_BASE_ADDR+0x3500
+#define HDMI_GP_CONF1               HDMI_ARB_BASE_ADDR+0x3501
+#define HDMI_GP_CONF2               HDMI_ARB_BASE_ADDR+0x3502
+#define HDMI_GP_STAT                HDMI_ARB_BASE_ADDR+0x3503
+#define HDMI_GP_INT                 HDMI_ARB_BASE_ADDR+0x3504
+#define HDMI_GP_MASK                HDMI_ARB_BASE_ADDR+0x3505
+#define HDMI_GP_POL                 HDMI_ARB_BASE_ADDR+0x3506
+
+// Audio DMA Registers (TBD)
+#define HDMI_AHB_DMA_CONF0          HDMI_ARB_BASE_ADDR+0x3600
+#define HDMI_AHB_DMA_START          HDMI_ARB_BASE_ADDR+0x3601
+#define HDMI_AHB_DMA_STOP           HDMI_ARB_BASE_ADDR+0x3602
+#define HDMI_AHB_DMA_THRSLD         HDMI_ARB_BASE_ADDR+0x3603
+#define HDMI_AHB_DMA_STRADDR0       HDMI_ARB_BASE_ADDR+0x3604
+#define HDMI_AHB_DMA_STRADDR1       HDMI_ARB_BASE_ADDR+0x3605
+#define HDMI_AHB_DMA_STRADDR2       HDMI_ARB_BASE_ADDR+0x3606
+#define HDMI_AHB_DMA_STRADDR3       HDMI_ARB_BASE_ADDR+0x3607
+#define HDMI_AHB_DMA_STPADDR0       HDMI_ARB_BASE_ADDR+0x3608
+#define HDMI_AHB_DMA_STPADDR1       HDMI_ARB_BASE_ADDR+0x3609
+#define HDMI_AHB_DMA_STPADDR2       HDMI_ARB_BASE_ADDR+0x360a
+#define HDMI_AHB_DMA_STPADDR3       HDMI_ARB_BASE_ADDR+0x360b
+#define HDMI_AHB_DMA_BSTADDR0       HDMI_ARB_BASE_ADDR+0x360c
+#define HDMI_AHB_DMA_BSTADDR1       HDMI_ARB_BASE_ADDR+0x360d
+#define HDMI_AHB_DMA_BSTADDR2       HDMI_ARB_BASE_ADDR+0x360e
+#define HDMI_AHB_DMA_BSTADDR3       HDMI_ARB_BASE_ADDR+0x360f
+#define HDMI_AHB_DMA_MBLENGTH0      HDMI_ARB_BASE_ADDR+0x3610
+#define HDMI_AHB_DMA_MBLENGTH1      HDMI_ARB_BASE_ADDR+0x3611
+#define HDMI_AHB_DMA_STAT           HDMI_ARB_BASE_ADDR+0x3612
+#define HDMI_AHB_DMA_INT            HDMI_ARB_BASE_ADDR+0x3613
+#define HDMI_AHB_DMA_MASK           HDMI_ARB_BASE_ADDR+0x3614
+#define HDMI_AHB_DMA_POL            HDMI_ARB_BASE_ADDR+0x3615
+
+// Main Controller Registers
+#define HDMI_MC_SFRDIV              HDMI_ARB_BASE_ADDR+0x4000
+#define HDMI_MC_CLKDIS              HDMI_ARB_BASE_ADDR+0x4001
+#define HDMI_MC_SWRSTZ              HDMI_ARB_BASE_ADDR+0x4002
+#define HDMI_MC_OPCTRL              HDMI_ARB_BASE_ADDR+0x4003
+#define HDMI_MC_FLOWCTRL            HDMI_ARB_BASE_ADDR+0x4004
+#define HDMI_MC_PHYRSTZ             HDMI_ARB_BASE_ADDR+0x4005
+#define HDMI_MC_LOCKONCLOCK         HDMI_ARB_BASE_ADDR+0x4006
+#define HDMI_MC_HEACPHY_RST         HDMI_ARB_BASE_ADDR+0x4007
+
+// Color Space  Converter Registers
+#define HDMI_CSC_CFG                HDMI_ARB_BASE_ADDR+0x4100
+#define HDMI_CSC_SCALE              HDMI_ARB_BASE_ADDR+0x4101
+#define HDMI_CSC_COEF_A1_MSB        HDMI_ARB_BASE_ADDR+0x4102
+#define HDMI_CSC_COEF_A1_LSB        HDMI_ARB_BASE_ADDR+0x4103
+#define HDMI_CSC_COEF_A2_MSB        HDMI_ARB_BASE_ADDR+0x4104
+#define HDMI_CSC_COEF_A2_LSB        HDMI_ARB_BASE_ADDR+0x4105
+#define HDMI_CSC_COEF_A3_MSB        HDMI_ARB_BASE_ADDR+0x4106
+#define HDMI_CSC_COEF_A3_LSB        HDMI_ARB_BASE_ADDR+0x4107
+#define HDMI_CSC_COEF_A4_MSB        HDMI_ARB_BASE_ADDR+0x4108
+#define HDMI_CSC_COEF_A4_LSB        HDMI_ARB_BASE_ADDR+0x4109
+#define HDMI_CSC_COEF_B1_MSB        HDMI_ARB_BASE_ADDR+0x410A
+#define HDMI_CSC_COEF_B1_LSB        HDMI_ARB_BASE_ADDR+0x410B
+#define HDMI_CSC_COEF_B2_MSB        HDMI_ARB_BASE_ADDR+0x410C
+#define HDMI_CSC_COEF_B2_LSB        HDMI_ARB_BASE_ADDR+0x410D
+#define HDMI_CSC_COEF_B3_MSB        HDMI_ARB_BASE_ADDR+0x410E
+#define HDMI_CSC_COEF_B3_LSB        HDMI_ARB_BASE_ADDR+0x410F
+#define HDMI_CSC_COEF_B4_MSB        HDMI_ARB_BASE_ADDR+0x4110
+#define HDMI_CSC_COEF_B4_LSB        HDMI_ARB_BASE_ADDR+0x4111
+#define HDMI_CSC_COEF_C1_MSB        HDMI_ARB_BASE_ADDR+0x4112
+#define HDMI_CSC_COEF_C1_LSB        HDMI_ARB_BASE_ADDR+0x4113
+#define HDMI_CSC_COEF_C2_MSB        HDMI_ARB_BASE_ADDR+0x4114
+#define HDMI_CSC_COEF_C2_LSB        HDMI_ARB_BASE_ADDR+0x4115
+#define HDMI_CSC_COEF_C3_MSB        HDMI_ARB_BASE_ADDR+0x4116
+#define HDMI_CSC_COEF_C3_LSB        HDMI_ARB_BASE_ADDR+0x4117
+#define HDMI_CSC_COEF_C4_MSB        HDMI_ARB_BASE_ADDR+0x4118
+#define HDMI_CSC_COEF_C4_LSB        HDMI_ARB_BASE_ADDR+0x4119
+
+// HDCP Encryption Engine Registers
+#define HDMI_A_HDCPCFG0             HDMI_ARB_BASE_ADDR+0x5000
+#define HDMI_A_HDCPCFG1             HDMI_ARB_BASE_ADDR+0x5001
+#define HDMI_A_HDCPOBS0             HDMI_ARB_BASE_ADDR+0x5002
+#define HDMI_A_HDCPOBS1             HDMI_ARB_BASE_ADDR+0x5003
+#define HDMI_A_HDCPOBS2             HDMI_ARB_BASE_ADDR+0x5004
+#define HDMI_A_HDCPOBS3             HDMI_ARB_BASE_ADDR+0x5005
+#define HDMI_A_APIINTCLR            HDMI_ARB_BASE_ADDR+0x5006
+#define HDMI_A_APIINTSTAT           HDMI_ARB_BASE_ADDR+0x5007
+#define HDMI_A_APIINTMSK            HDMI_ARB_BASE_ADDR+0x5008
+#define HDMI_A_VIDPOLCFG            HDMI_ARB_BASE_ADDR+0x5009
+#define HDMI_A_OESSWCFG             HDMI_ARB_BASE_ADDR+0x500A
+#define HDMI_A_TIMER1SETUP0         HDMI_ARB_BASE_ADDR+0x500B
+#define HDMI_A_TIMER1SETUP1         HDMI_ARB_BASE_ADDR+0x500C
+#define HDMI_A_TIMER2SETUP0         HDMI_ARB_BASE_ADDR+0x500D
+#define HDMI_A_TIMER2SETUP1         HDMI_ARB_BASE_ADDR+0x500E
+#define HDMI_A_100MSCFG             HDMI_ARB_BASE_ADDR+0x500F
+#define HDMI_A_2SCFG0               HDMI_ARB_BASE_ADDR+0x5010
+#define HDMI_A_2SCFG1               HDMI_ARB_BASE_ADDR+0x5011
+#define HDMI_A_5SCFG0               HDMI_ARB_BASE_ADDR+0x5012
+#define HDMI_A_5SCFG1               HDMI_ARB_BASE_ADDR+0x5013
+#define HDMI_A_SRMVERLSB            HDMI_ARB_BASE_ADDR+0x5014
+#define HDMI_A_SRMVERMSB            HDMI_ARB_BASE_ADDR+0x5015
+#define HDMI_A_SRMCTRL              HDMI_ARB_BASE_ADDR+0x5016
+#define HDMI_A_SFRSETUP             HDMI_ARB_BASE_ADDR+0x5017
+#define HDMI_A_I2CHSETUP            HDMI_ARB_BASE_ADDR+0x5018
+#define HDMI_A_INTSETUP             HDMI_ARB_BASE_ADDR+0x5019
+#define HDMI_A_PRESETUP             HDMI_ARB_BASE_ADDR+0x501A
+#define HDMI_A_SRM_BASE             HDMI_ARB_BASE_ADDR+0x5020
+
+// CEC Engine Registers
+#define HDMI_CEC_CTRL               HDMI_ARB_BASE_ADDR+0x7D00
+#define HDMI_CEC_STAT               HDMI_ARB_BASE_ADDR+0x7D01
+#define HDMI_CEC_MASK               HDMI_ARB_BASE_ADDR+0x7D02
+#define HDMI_CEC_POLARITY           HDMI_ARB_BASE_ADDR+0x7D03
+#define HDMI_CEC_INT                HDMI_ARB_BASE_ADDR+0x7D04
+#define HDMI_CEC_ADDR_L             HDMI_ARB_BASE_ADDR+0x7D05
+#define HDMI_CEC_ADDR_H             HDMI_ARB_BASE_ADDR+0x7D06
+#define HDMI_CEC_TX_CNT             HDMI_ARB_BASE_ADDR+0x7D07
+#define HDMI_CEC_RX_CNT             HDMI_ARB_BASE_ADDR+0x7D08
+#define HDMI_CEC_TX_DATA0           HDMI_ARB_BASE_ADDR+0x7D10
+#define HDMI_CEC_TX_DATA1           HDMI_ARB_BASE_ADDR+0x7D11
+#define HDMI_CEC_TX_DATA2           HDMI_ARB_BASE_ADDR+0x7D12
+#define HDMI_CEC_TX_DATA3           HDMI_ARB_BASE_ADDR+0x7D13
+#define HDMI_CEC_TX_DATA4           HDMI_ARB_BASE_ADDR+0x7D14
+#define HDMI_CEC_TX_DATA5           HDMI_ARB_BASE_ADDR+0x7D15
+#define HDMI_CEC_TX_DATA6           HDMI_ARB_BASE_ADDR+0x7D16
+#define HDMI_CEC_TX_DATA7           HDMI_ARB_BASE_ADDR+0x7D17
+#define HDMI_CEC_TX_DATA8           HDMI_ARB_BASE_ADDR+0x7D18
+#define HDMI_CEC_TX_DATA9           HDMI_ARB_BASE_ADDR+0x7D19
+#define HDMI_CEC_TX_DATA10          HDMI_ARB_BASE_ADDR+0x7D1a
+#define HDMI_CEC_TX_DATA11          HDMI_ARB_BASE_ADDR+0x7D1b
+#define HDMI_CEC_TX_DATA12          HDMI_ARB_BASE_ADDR+0x7D1c
+#define HDMI_CEC_TX_DATA13          HDMI_ARB_BASE_ADDR+0x7D1d
+#define HDMI_CEC_TX_DATA14          HDMI_ARB_BASE_ADDR+0x7D1e
+#define HDMI_CEC_TX_DATA15          HDMI_ARB_BASE_ADDR+0x7D1f
+#define HDMI_CEC_RX_DATA0           HDMI_ARB_BASE_ADDR+0x7D20
+#define HDMI_CEC_RX_DATA1           HDMI_ARB_BASE_ADDR+0x7D21
+#define HDMI_CEC_RX_DATA2           HDMI_ARB_BASE_ADDR+0x7D22
+#define HDMI_CEC_RX_DATA3           HDMI_ARB_BASE_ADDR+0x7D23
+#define HDMI_CEC_RX_DATA4           HDMI_ARB_BASE_ADDR+0x7D24
+#define HDMI_CEC_RX_DATA5           HDMI_ARB_BASE_ADDR+0x7D25
+#define HDMI_CEC_RX_DATA6           HDMI_ARB_BASE_ADDR+0x7D26
+#define HDMI_CEC_RX_DATA7           HDMI_ARB_BASE_ADDR+0x7D27
+#define HDMI_CEC_RX_DATA8           HDMI_ARB_BASE_ADDR+0x7D28
+#define HDMI_CEC_RX_DATA9           HDMI_ARB_BASE_ADDR+0x7D29
+#define HDMI_CEC_RX_DATA10          HDMI_ARB_BASE_ADDR+0x7D2a
+#define HDMI_CEC_RX_DATA11          HDMI_ARB_BASE_ADDR+0x7D2b
+#define HDMI_CEC_RX_DATA12          HDMI_ARB_BASE_ADDR+0x7D2c
+#define HDMI_CEC_RX_DATA13          HDMI_ARB_BASE_ADDR+0x7D2d
+#define HDMI_CEC_RX_DATA14          HDMI_ARB_BASE_ADDR+0x7D2e
+#define HDMI_CEC_RX_DATA15          HDMI_ARB_BASE_ADDR+0x7D2f
+#define HDMI_CEC_LOCK               HDMI_ARB_BASE_ADDR+0x7D30
+#define HDMI_CEC_WKUPCTRL           HDMI_ARB_BASE_ADDR+0x7D31
+
+// I2C Master Registers (E-DDC)
+#define HDMI_I2CM_SLAVE             HDMI_ARB_BASE_ADDR+0x7E00
+#define HDMI_I2CMESS                HDMI_ARB_BASE_ADDR+0x7E01
+#define HDMI_I2CM_DATAO             HDMI_ARB_BASE_ADDR+0x7E02
+#define HDMI_I2CM_DATAI             HDMI_ARB_BASE_ADDR+0x7E03
+#define HDMI_I2CM_OPERATION         HDMI_ARB_BASE_ADDR+0x7E04
+#define HDMI_I2CM_INT               HDMI_ARB_BASE_ADDR+0x7E05
+#define HDMI_I2CM_CTLINT            HDMI_ARB_BASE_ADDR+0x7E06
+#define HDMI_I2CM_DIV               HDMI_ARB_BASE_ADDR+0x7E07
+#define HDMI_I2CM_SEGADDR           HDMI_ARB_BASE_ADDR+0x7E08
+#define HDMI_I2CM_SOFTRSTZ          HDMI_ARB_BASE_ADDR+0x7E09
+#define HDMI_I2CM_SEGPTR            HDMI_ARB_BASE_ADDR+0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR     HDMI_ARB_BASE_ADDR+0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR     HDMI_ARB_BASE_ADDR+0x7E12
+
+// Random Number Generator Registers (RNG)
+#define HDMI_RNG_BASE         HDMI_ARB_BASE_ADDR+0x8000
+
+#endif //HDMI_COMMON_H

bsp/imx6ul/platform/include/mx6ul/iim_fuse.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2011-2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+#ifndef __IIM_FUSE_H__
+#define __IIM_FUSE_H__
+
+#define IIM_STAT_OFF            0x00
+#define IIM_STAT_BUSY           (1 << 7)
+#define IIM_STAT_PRGD           (1 << 1)
+#define IIM_STAT_SNSD           (1 << 0)
+#define IIM_STATM_OFF           0x04
+#define IIM_ERR_OFF             0x08
+#define IIM_ERR_PRGE            (1 << 7)
+#define IIM_ERR_WPE         (1 << 6)
+#define IIM_ERR_OPE         (1 << 5)
+#define IIM_ERR_RPE         (1 << 4)
+#define IIM_ERR_WLRE        (1 << 3)
+#define IIM_ERR_SNSE        (1 << 2)
+#define IIM_ERR_PARITYE     (1 << 1)
+#define IIM_EMASK_OFF           0x0C
+#define IIM_FCTL_OFF            0x10
+#define IIM_UA_OFF              0x14
+#define IIM_LA_OFF              0x18
+#define IIM_SDAT_OFF            0x1C
+#define IIM_PREV_OFF            0x20
+#define IIM_SREV_OFF            0x24
+#define IIM_PREG_P_OFF          0x28
+#define IIM_SCS0_OFF            0x2C
+#define IIM_SCS1_P_OFF          0x30
+#define IIM_SCS2_OFF            0x34
+#define IIM_SCS3_P_OFF          0x38
+
+//unsigned int sense_fuse(int bank, int row);
+//int fuse_blow(int bank, int row, int bit);
+
+#endif // __IIM_FUSE_H__

bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h

@@ -0,0 +1,915 @@
+/*
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6UL_PINFUNC_H
+#define __DTS_IMX6UL_PINFUNC_H
+
+#define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \
+	do {\
+		writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\
+		if (select_input_offset != 0)\
+			writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\
+		writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\
+	} while(0);
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6UL_PAD_JTAG_MOD__SJC_MOD(p)                               PIN_CFG(0x0044, 0x02D0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__GPT2_CLK(p)                              PIN_CFG(0x0044, 0x02D0, 0x05A0, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT(p)                             PIN_CFG(0x0044, 0x02D0, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M(p)                     PIN_CFG(0x0044, 0x02D0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY(p)                          PIN_CFG(0x0044, 0x02D0, 0x04C0, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10(p)                            PIN_CFG(0x0044, 0x02D0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00(p)                      PIN_CFG(0x0044, 0x02D0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__SJC_TMS(p)                               PIN_CFG(0x0048, 0x02D4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1(p)                         PIN_CFG(0x0048, 0x02D4, 0x0598, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__CCM_WAIT(p)                              PIN_CFG(0x0048, 0x02D4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11(p)                            PIN_CFG(0x0048, 0x02D4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01(p)                      PIN_CFG(0x0048, 0x02D4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT(p)                             PIN_CFG(0x0048, 0x02D4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__SJC_TDO(p)                               PIN_CFG(0x004C, 0x02D8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2(p)                         PIN_CFG(0x004C, 0x02D8, 0x059C, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC(p)                          PIN_CFG(0x004C, 0x02D8, 0x05FC, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__CCM_STOP(p)                              PIN_CFG(0x004C, 0x02D8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12(p)                            PIN_CFG(0x004C, 0x02D8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT(p)                             PIN_CFG(0x004C, 0x02D8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__SJC_TDI(p)                               PIN_CFG(0x0050, 0x02DC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1(p)                         PIN_CFG(0x0050, 0x02DC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK(p)                          PIN_CFG(0x0050, 0x02DC, 0x05F8, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__PWM6_OUT(p)                              PIN_CFG(0x0050, 0x02DC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13(p)                            PIN_CFG(0x0050, 0x02DC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__MQS_LEFT(p)                              PIN_CFG(0x0050, 0x02DC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL(p)                       PIN_CFG(0x0050, 0x02DC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__SJC_TCK(p)                               PIN_CFG(0x0054, 0x02E0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2(p)                         PIN_CFG(0x0054, 0x02E0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA(p)                          PIN_CFG(0x0054, 0x02E0, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__PWM7_OUT(p)                              PIN_CFG(0x0054, 0x02E0, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14(p)                            PIN_CFG(0x0054, 0x02E0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL(p)                       PIN_CFG(0x0054, 0x02E0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB(p)                          PIN_CFG(0x0058, 0x02E4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3(p)                      PIN_CFG(0x0058, 0x02E4, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA(p)                       PIN_CFG(0x0058, 0x02E4, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT(p)                           PIN_CFG(0x0058, 0x02E4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15(p)                         PIN_CFG(0x0058, 0x02E4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS(p)                   PIN_CFG(0x0058, 0x02E4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL(p)                            PIN_CFG(0x005C, 0x02E8, 0x05AC, 0x0, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1(p)                       PIN_CFG(0x005C, 0x02E8, 0x058C, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID(p)                      PIN_CFG(0x005C, 0x02E8, 0x04B8, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1(p)                      PIN_CFG(0x005C, 0x02E8, 0x0574, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT(p)                           PIN_CFG(0x005C, 0x02E8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00(p)                          PIN_CFG(0x005C, 0x02E8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN(p)                PIN_CFG(0x005C, 0x02E8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET(p)                    PIN_CFG(0x005C, 0x02E8, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B(p)                        PIN_CFG(0x005C, 0x02E8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA(p)                            PIN_CFG(0x0060, 0x02EC, 0x05B0, 0x0, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1(p)                       PIN_CFG(0x0060, 0x02EC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC(p)                         PIN_CFG(0x0060, 0x02EC, 0x0664, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2(p)                      PIN_CFG(0x0060, 0x02EC, 0x057C, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT(p)                            PIN_CFG(0x0060, 0x02EC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01(p)                          PIN_CFG(0x0060, 0x02EC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT(p)               PIN_CFG(0x0060, 0x02EC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET(p)                     PIN_CFG(0x0060, 0x02EC, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B(p)                        PIN_CFG(0x0060, 0x02EC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL(p)                            PIN_CFG(0x0064, 0x02F0, 0x05A4, 0x0, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2(p)                       PIN_CFG(0x0064, 0x02F0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR(p)                        PIN_CFG(0x0064, 0x02F0, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M(p)                   PIN_CFG(0x0064, 0x02F0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP(p)                           PIN_CFG(0x0064, 0x02F0, 0x066C, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02(p)                          PIN_CFG(0x0064, 0x02F0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00(p)                    PIN_CFG(0x0064, 0x02F0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET(p)                    PIN_CFG(0x0064, 0x02F0, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO02__UART1_TX(p)                            PIN_CFG(0x0064, 0x02F0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA(p)                            PIN_CFG(0x0068, 0x02F4, 0x05A8, 0x0, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3(p)                       PIN_CFG(0x0068, 0x02F4, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC(p)                         PIN_CFG(0x0068, 0x02F4, 0x0660, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B(p)                         PIN_CFG(0x0068, 0x02F4, 0x0668, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03(p)                          PIN_CFG(0x0068, 0x02F4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK(p)                     PIN_CFG(0x0068, 0x02F4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK(p)                      PIN_CFG(0x0068, 0x02F4, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO03__UART1_RX(p)                            PIN_CFG(0x0068, 0x02F4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1(p)                      PIN_CFG(0x006C, 0x02F8, 0x0574, 0x0, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT(p)                            PIN_CFG(0x006C, 0x02F8, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR(p)                        PIN_CFG(0x006C, 0x02F8, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B(p)                      PIN_CFG(0x006C, 0x02F8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04(p)                          PIN_CFG(0x006C, 0x02F8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN(p)                PIN_CFG(0x006C, 0x02F8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO04__UART5_TX(p)                            PIN_CFG(0x006C, 0x02F8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2(p)                      PIN_CFG(0x0070, 0x02FC, 0x057C, 0x0, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT(p)                            PIN_CFG(0x0070, 0x02FC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID(p)                      PIN_CFG(0x0070, 0x02FC, 0x04BC, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD(p)                           PIN_CFG(0x0070, 0x02FC, 0x0530, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT(p)                      PIN_CFG(0x0070, 0x02FC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05(p)                          PIN_CFG(0x0070, 0x02FC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT(p)               PIN_CFG(0x0070, 0x02FC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO05__UART5_RX(p)                            PIN_CFG(0x0070, 0x02FC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO(p)                          PIN_CFG(0x0074, 0x0300, 0x0578, 0x0, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO(p)                          PIN_CFG(0x0074, 0x0300, 0x0580, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE(p)                    PIN_CFG(0x0074, 0x0300, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK(p)                            PIN_CFG(0x0074, 0x0300, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP(p)                           PIN_CFG(0x0074, 0x0300, 0x069C, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06(p)                          PIN_CFG(0x0074, 0x0300, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT(p)                            PIN_CFG(0x0074, 0x0300, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B(p)                        PIN_CFG(0x0074, 0x0300, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS(p)                       PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS(p)                       PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC(p)                           PIN_CFG(0x0078, 0x0304, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC(p)                           PIN_CFG(0x0078, 0x0304, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE(p)                   PIN_CFG(0x0078, 0x0304, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK(p)                          PIN_CFG(0x0078, 0x0304, 0x0528, 0x3, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B(p)                         PIN_CFG(0x0078, 0x0304, 0x0674, 0x4, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07(p)                          PIN_CFG(0x0078, 0x0304, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__CCM_STOP(p)                            PIN_CFG(0x0078, 0x0304, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS(p)                       PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS(p)                       PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT(p)                            PIN_CFG(0x007C, 0x0308, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B(p)                        PIN_CFG(0x007C, 0x0308, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT(p)                           PIN_CFG(0x007C, 0x0308, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC(p)                           PIN_CFG(0x007C, 0x0308, 0x052C, 0x3, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT(p)                      PIN_CFG(0x007C, 0x0308, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08(p)                          PIN_CFG(0x007C, 0x0308, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY(p)                        PIN_CFG(0x007C, 0x0308, 0x04C0, 0x6, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS(p)                       PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS(p)                       PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT(p)                            PIN_CFG(0x0080, 0x030C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN(p)                            PIN_CFG(0x0080, 0x030C, 0x0618, 0x2, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC(p)                           PIN_CFG(0x0080, 0x030C, 0x0524, 0x3, 0x1, p)
+#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09(p)                          PIN_CFG(0x0080, 0x030C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B(p)                      PIN_CFG(0x0080, 0x030C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS(p)                       PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS(p)                       PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p)                         PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p)
+#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02(p)                    PIN_CFG(0x0084, 0x0310, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL(p)                         PIN_CFG(0x0084, 0x0310, 0x05B4, 0x2, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02(p)                       PIN_CFG(0x0084, 0x0310, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1(p)                    PIN_CFG(0x0084, 0x0310, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16(p)                       PIN_CFG(0x0084, 0x0310, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT(p)                        PIN_CFG(0x0084, 0x0310, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p)                         PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p)
+#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03(p)                    PIN_CFG(0x0088, 0x0314, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA(p)                         PIN_CFG(0x0088, 0x0314, 0x05B8, 0x2, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03(p)                       PIN_CFG(0x0088, 0x0314, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK(p)                         PIN_CFG(0x0088, 0x0314, 0x0594, 0x4, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17(p)                       PIN_CFG(0x0088, 0x0314, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN(p)                         PIN_CFG(0x0088, 0x0314, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS(p)                      PIN_CFG(0x008C, 0x0318, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS(p)                      PIN_CFG(0x008C, 0x0318, 0x0620, 0x0, 0x2, p)
+#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK(p)                       PIN_CFG(0x008C, 0x0318, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP(p)                          PIN_CFG(0x008C, 0x0318, 0x066C, 0x2, 0x1, p)
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04(p)                         PIN_CFG(0x008C, 0x0318, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN(p)               PIN_CFG(0x008C, 0x0318, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18(p)                         PIN_CFG(0x008C, 0x0318, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP(p)                          PIN_CFG(0x008C, 0x0318, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS(p)                      PIN_CFG(0x0090, 0x031C, 0x0620, 0x0, 0x3, p)
+#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS(p)                      PIN_CFG(0x0090, 0x031C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER(p)                        PIN_CFG(0x0090, 0x031C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B(p)                        PIN_CFG(0x0090, 0x031C, 0x0668, 0x2, 0x1, p)
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05(p)                         PIN_CFG(0x0090, 0x031C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT(p)              PIN_CFG(0x0090, 0x031C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19(p)                         PIN_CFG(0x0090, 0x031C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B(p)                        PIN_CFG(0x0090, 0x031C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__UART2_TX(p)                         PIN_CFG(0x0094, 0x0320, 0x062C, 0x0, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02(p)                    PIN_CFG(0x0094, 0x0320, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL(p)                         PIN_CFG(0x0094, 0x0320, 0x05BC, 0x2, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1(p)                    PIN_CFG(0x0094, 0x0320, 0x058C, 0x4, 0x1, p)
+#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0(p)                       PIN_CFG(0x0094, 0x0320, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__UART2_RX(p)                         PIN_CFG(0x0098, 0x0324, 0x062C, 0x0, 0x1, p)
+#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03(p)                    PIN_CFG(0x0098, 0x0324, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA(p)                         PIN_CFG(0x0098, 0x0324, 0x05C0, 0x2, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07(p)                       PIN_CFG(0x0098, 0x0324, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2(p)                    PIN_CFG(0x0098, 0x0324, 0x0590, 0x4, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21(p)                       PIN_CFG(0x0098, 0x0324, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE(p)                         PIN_CFG(0x0098, 0x0324, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK(p)                      PIN_CFG(0x0098, 0x0324, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS(p)                      PIN_CFG(0x009C, 0x0328, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS(p)                      PIN_CFG(0x009C, 0x0328, 0x0628, 0x0, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS(p)                          PIN_CFG(0x009C, 0x0328, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX(p)                        PIN_CFG(0x009C, 0x0328, 0x0000, 0x12, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08(p)                         PIN_CFG(0x009C, 0x0328, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2(p)                      PIN_CFG(0x009C, 0x0328, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22(p)                         PIN_CFG(0x009C, 0x0328, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B(p)                           PIN_CFG(0x009C, 0x0328, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI(p)                        PIN_CFG(0x009C, 0x0328, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS(p)                      PIN_CFG(0x00A0, 0x032C, 0x0628, 0x0, 0x1, p)
+#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS(p)                      PIN_CFG(0x00A0, 0x032C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__ENET1_COL(p)                          PIN_CFG(0x00A0, 0x032C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX(p)                        PIN_CFG(0x00A0, 0x032C, 0x0588, 0x12, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09(p)                         PIN_CFG(0x00A0, 0x032C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3(p)                      PIN_CFG(0x00A0, 0x032C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23(p)                         PIN_CFG(0x00A0, 0x032C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL(p)                           PIN_CFG(0x00A0, 0x032C, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO(p)                        PIN_CFG(0x00A0, 0x032C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__UART3_TX(p)                         PIN_CFG(0x00A4, 0x0330, 0x0634, 0x0, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01(p)                       PIN_CFG(0x00A4, 0x0330, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS(p)                    PIN_CFG(0x00A4, 0x0330, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS(p)                    PIN_CFG(0x00A4, 0x0330, 0x0628, 0x4, 0x2, p)
+#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24(p)                       PIN_CFG(0x00A4, 0x0330, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT(p)                     PIN_CFG(0x00A4, 0x0330, 0x0000, 0x7, 0x0, p)
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID(p)                   PIN_CFG(0x00A4, 0x0330, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__UART3_RX(p)                         PIN_CFG(0x00A8, 0x0334, 0x0634, 0x0, 0x1, p)
+#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00(p)                       PIN_CFG(0x00A8, 0x0334, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS(p)                    PIN_CFG(0x00A8, 0x0334, 0x0628, 0x4, 0x3, p)
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS(p)                    PIN_CFG(0x00A8, 0x0334, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25(p)                       PIN_CFG(0x00A8, 0x0334, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT(p)                        PIN_CFG(0x00A8, 0x0334, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS(p)                      PIN_CFG(0x00AC, 0x0338, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS(p)                      PIN_CFG(0x00AC, 0x0338, 0x0630, 0x0, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK(p)                       PIN_CFG(0x00AC, 0x0338, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX(p)                        PIN_CFG(0x00AC, 0x0338, 0x0000, 0x12, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10(p)                         PIN_CFG(0x00AC, 0x0338, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN(p)               PIN_CFG(0x00AC, 0x0338, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26(p)                         PIN_CFG(0x00AC, 0x0338, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT(p)                          PIN_CFG(0x00AC, 0x0338, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS(p)                      PIN_CFG(0x00B0, 0x033C, 0x0630, 0x0, 0x1, p)
+#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS(p)                      PIN_CFG(0x00B0, 0x033C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER(p)                        PIN_CFG(0x00B0, 0x033C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX(p)                        PIN_CFG(0x00B0, 0x033C, 0x0584, 0x12, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11(p)                         PIN_CFG(0x00B0, 0x033C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT(p)              PIN_CFG(0x00B0, 0x033C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27(p)                         PIN_CFG(0x00B0, 0x033C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B(p)                       PIN_CFG(0x00B0, 0x033C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__UART4_TX(p)                         PIN_CFG(0x00B4, 0x0340, 0x063C, 0x0, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02(p)                    PIN_CFG(0x00B4, 0x0340, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL(p)                         PIN_CFG(0x00B4, 0x0340, 0x05A4, 0x12, 0x1, p)
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12(p)                       PIN_CFG(0x00B4, 0x0340, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02(p)              PIN_CFG(0x00B4, 0x0340, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28(p)                       PIN_CFG(0x00B4, 0x0340, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK(p)                      PIN_CFG(0x00B4, 0x0340, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART4_RX_DATA__UART4_RX(p)                         PIN_CFG(0x00B8, 0x0344, 0x063C, 0x0, 0x1, p)
+#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03(p)                    PIN_CFG(0x00B8, 0x0344, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA(p)                         PIN_CFG(0x00B8, 0x0344, 0x05A8, 0x12, 0x2, p)
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01(p)              PIN_CFG(0x00B8, 0x0344, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0(p)                       PIN_CFG(0x00B8, 0x0344, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30(p)                       PIN_CFG(0x00BC, 0x0348, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI(p)                      PIN_CFG(0x00BC, 0x0348, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_UART5_TX_DATA__UART5_TX(p)                         PIN_CFG(0x00BC, 0x0348, 0x0644, 0x0, 0x4, p)
+#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS(p)                        PIN_CFG(0x00BC, 0x0348, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL(p)                         PIN_CFG(0x00BC, 0x0348, 0x05AC, 0x12, 0x2, p)
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14(p)                       PIN_CFG(0x00BC, 0x0348, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00(p)              PIN_CFG(0x00BC, 0x0348, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART5_RX_DATA__UART5_RX(p)                         PIN_CFG(0x00C0, 0x034C, 0x0644, 0x0, 0x5, p)
+#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL(p)                        PIN_CFG(0x00C0, 0x034C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA(p)                         PIN_CFG(0x00C0, 0x034C, 0x05B0, 0x12, 0x2, p)
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15(p)                       PIN_CFG(0x00C0, 0x034C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB(p)                  PIN_CFG(0x00C0, 0x034C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31(p)                       PIN_CFG(0x00C0, 0x034C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO(p)                      PIN_CFG(0x00C0, 0x034C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00(p)                   PIN_CFG(0x00C4, 0x0350, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS(p)                   PIN_CFG(0x00C4, 0x0350, 0x0638, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS(p)                   PIN_CFG(0x00C4, 0x0350, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT(p)                        PIN_CFG(0x00C4, 0x0350, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16(p)                      PIN_CFG(0x00C4, 0x0350, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX(p)                     PIN_CFG(0x00C4, 0x0350, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00(p)                      PIN_CFG(0x00C4, 0x0350, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00(p)                       PIN_CFG(0x00C4, 0x0350, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL(p)                     PIN_CFG(0x00C4, 0x0350, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01(p)                   PIN_CFG(0x00C8, 0x0354, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS(p)                   PIN_CFG(0x00C8, 0x0354, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS(p)                   PIN_CFG(0x00C8, 0x0354, 0x0638, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT(p)                        PIN_CFG(0x00C8, 0x0354, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17(p)                      PIN_CFG(0x00C8, 0x0354, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX(p)                     PIN_CFG(0x00C8, 0x0354, 0x0584, 0x4, 0x1, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01(p)                      PIN_CFG(0x00C8, 0x0354, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00(p)                       PIN_CFG(0x00C8, 0x0354, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL(p)                     PIN_CFG(0x00C8, 0x0354, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN(p)                        PIN_CFG(0x00CC, 0x0358, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS(p)                      PIN_CFG(0x00CC, 0x0358, 0x0640, 0x1, 0x3, p)
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS(p)                      PIN_CFG(0x00CC, 0x0358, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18(p)                         PIN_CFG(0x00CC, 0x0358, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX(p)                        PIN_CFG(0x00CC, 0x0358, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02(p)                         PIN_CFG(0x00CC, 0x0358, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01(p)                          PIN_CFG(0x00CC, 0x0358, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT(p)                     PIN_CFG(0x00CC, 0x0358, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00(p)                   PIN_CFG(0x00D0, 0x035C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS(p)                   PIN_CFG(0x00D0, 0x035C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS(p)                   PIN_CFG(0x00D0, 0x035C, 0x0640, 0x1, 0x4, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19(p)                      PIN_CFG(0x00D0, 0x035C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX(p)                     PIN_CFG(0x00D0, 0x035C, 0x0588, 0x4, 0x1, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03(p)                      PIN_CFG(0x00D0, 0x035C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01(p)                       PIN_CFG(0x00D0, 0x035C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT(p)                  PIN_CFG(0x00D0, 0x035C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01(p)                   PIN_CFG(0x00D4, 0x0360, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS(p)                   PIN_CFG(0x00D4, 0x0360, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS(p)                   PIN_CFG(0x00D4, 0x0360, 0x0648, 0x1, 0x2, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT(p)                        PIN_CFG(0x00D4, 0x0360, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20(p)                      PIN_CFG(0x00D4, 0x0360, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO(p)                      PIN_CFG(0x00D4, 0x0360, 0x0580, 0x4, 0x1, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04(p)                      PIN_CFG(0x00D4, 0x0360, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02(p)                       PIN_CFG(0x00D4, 0x0360, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB(p)            PIN_CFG(0x00D4, 0x0360, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN(p)                        PIN_CFG(0x00D8, 0x0364, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS(p)                      PIN_CFG(0x00D8, 0x0364, 0x0648, 0x1, 0x3, p)
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS(p)                      PIN_CFG(0x00D8, 0x0364, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT(p)                           PIN_CFG(0x00D8, 0x0364, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21(p)                         PIN_CFG(0x00D8, 0x0364, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC(p)                          PIN_CFG(0x00D8, 0x0364, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05(p)                         PIN_CFG(0x00D8, 0x0364, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02(p)                          PIN_CFG(0x00D8, 0x0364, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB(p)               PIN_CFG(0x00D8, 0x0364, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK(p)                      PIN_CFG(0x00DC, 0x0368, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS(p)                     PIN_CFG(0x00DC, 0x0368, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS(p)                     PIN_CFG(0x00DC, 0x0368, 0x0650, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT(p)                          PIN_CFG(0x00DC, 0x0368, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22(p)                        PIN_CFG(0x00DC, 0x0368, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1(p)                    PIN_CFG(0x00DC, 0x0368, 0x0574, 0x14, 0x2, p)
+#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06(p)                        PIN_CFG(0x00DC, 0x0368, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03(p)                         PIN_CFG(0x00DC, 0x0368, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK(p)                          PIN_CFG(0x00DC, 0x0368, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER(p)                        PIN_CFG(0x00E0, 0x036C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS(p)                      PIN_CFG(0x00E0, 0x036C, 0x0650, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS(p)                      PIN_CFG(0x00E0, 0x036C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT(p)                           PIN_CFG(0x00E0, 0x036C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23(p)                         PIN_CFG(0x00E0, 0x036C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE(p)                            PIN_CFG(0x00E0, 0x036C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07(p)                         PIN_CFG(0x00E0, 0x036C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03(p)                          PIN_CFG(0x00E0, 0x036C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2(p)                      PIN_CFG(0x00E0, 0x036C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00(p)                   PIN_CFG(0x00E4, 0x0370, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_TX(p)                        PIN_CFG(0x00E4, 0x0370, 0x064C, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD(p)                 PIN_CFG(0x00E4, 0x0370, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL(p)                        PIN_CFG(0x00E4, 0x0370, 0x05B4, 0x3, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO(p)                      PIN_CFG(0x00E4, 0x0370, 0x0578, 0x4, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08(p)                      PIN_CFG(0x00E4, 0x0370, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04(p)                       PIN_CFG(0x00E4, 0x0370, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR(p)                    PIN_CFG(0x00E4, 0x0370, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01(p)                   PIN_CFG(0x00E8, 0x0374, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_RX(p)                        PIN_CFG(0x00E8, 0x0374, 0x064C, 0x1, 0x2, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK(p)                  PIN_CFG(0x00E8, 0x0374, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA(p)                        PIN_CFG(0x00E8, 0x0374, 0x05B8, 0x3, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC(p)                       PIN_CFG(0x00E8, 0x0374, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09(p)                      PIN_CFG(0x00E8, 0x0374, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04(p)                       PIN_CFG(0x00E8, 0x0374, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC(p)                     PIN_CFG(0x00E8, 0x0374, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN(p)                        PIN_CFG(0x00EC, 0x0378, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__UART7_TX(p)                           PIN_CFG(0x00EC, 0x0378, 0x0654, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B(p)                   PIN_CFG(0x00EC, 0x0378, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL(p)                           PIN_CFG(0x00EC, 0x0378, 0x05BC, 0x3, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26(p)                         PIN_CFG(0x00EC, 0x0378, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10(p)                         PIN_CFG(0x00EC, 0x0378, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05(p)                          PIN_CFG(0x00EC, 0x0378, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M(p)                  PIN_CFG(0x00EC, 0x0378, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00(p)                   PIN_CFG(0x00F0, 0x037C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_RX(p)                        PIN_CFG(0x00F0, 0x037C, 0x0654, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN(p)                 PIN_CFG(0x00F0, 0x037C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA(p)                        PIN_CFG(0x00F0, 0x037C, 0x05C0, 0x3, 0x1, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02(p)                      PIN_CFG(0x00F0, 0x037C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11(p)                      PIN_CFG(0x00F0, 0x037C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05(p)                       PIN_CFG(0x00F0, 0x037C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01(p)                   PIN_CFG(0x00F4, 0x0380, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_TX(p)                        PIN_CFG(0x00F4, 0x0380, 0x065C, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD(p)                 PIN_CFG(0x00F4, 0x0380, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK(p)                     PIN_CFG(0x00F4, 0x0380, 0x0564, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03(p)                      PIN_CFG(0x00F4, 0x0380, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12(p)                      PIN_CFG(0x00F4, 0x0380, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06(p)                       PIN_CFG(0x00F4, 0x0380, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR(p)                    PIN_CFG(0x00F4, 0x0380, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN(p)                        PIN_CFG(0x00F8, 0x0384, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__UART8_RX(p)                           PIN_CFG(0x00F8, 0x0384, 0x065C, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK(p)                     PIN_CFG(0x00F8, 0x0384, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI(p)                        PIN_CFG(0x00F8, 0x0384, 0x056C, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN(p)                   PIN_CFG(0x00F8, 0x0384, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13(p)                         PIN_CFG(0x00F8, 0x0384, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06(p)                          PIN_CFG(0x00F8, 0x0384, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC(p)                        PIN_CFG(0x00F8, 0x0384, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK(p)                      PIN_CFG(0x00FC, 0x0388, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS(p)                     PIN_CFG(0x00FC, 0x0388, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS(p)                     PIN_CFG(0x00FC, 0x0388, 0x0658, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B(p)                  PIN_CFG(0x00FC, 0x0388, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO(p)                       PIN_CFG(0x00FC, 0x0388, 0x0568, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2(p)                    PIN_CFG(0x00FC, 0x0388, 0x057C, 0x14, 0x2, p)
+#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14(p)                        PIN_CFG(0x00FC, 0x0388, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07(p)                         PIN_CFG(0x00FC, 0x0388, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID(p)                    PIN_CFG(0x00FC, 0x0388, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER(p)                        PIN_CFG(0x0100, 0x038C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS(p)                      PIN_CFG(0x0100, 0x038C, 0x0658, 0x1, 0x1, p)
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS(p)                      PIN_CFG(0x0100, 0x038C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN(p)                    PIN_CFG(0x0100, 0x038C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15(p)                         PIN_CFG(0x0100, 0x038C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07(p)                          PIN_CFG(0x0100, 0x038C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY(p)                     PIN_CFG(0x0100, 0x038C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__LCDIF_CLK(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN(p)                           PIN_CFG(0x0104, 0x0390, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__UART4_TX(p)                               PIN_CFG(0x0104, 0x0390, 0x063C, 0x2, 0x2, p)
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__EIM_CS2_B(p)                              PIN_CFG(0x0104, 0x0390, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__GPIO3_IO00(p)                             PIN_CFG(0x0104, 0x0390, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB(p)                   PIN_CFG(0x0104, 0x0390, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE(p)                        PIN_CFG(0x0108, 0x0394, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__UART4_RX(p)                            PIN_CFG(0x0108, 0x0394, 0x063C, 0x2, 0x3, p)
+#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC(p)                        PIN_CFG(0x0108, 0x0394, 0x060C, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B(p)                           PIN_CFG(0x0108, 0x0394, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY(p)                          PIN_CFG(0x0108, 0x0394, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC(p)                          PIN_CFG(0x010C, 0x0398, 0x05DC, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS(p)                             PIN_CFG(0x010C, 0x0398, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS(p)                        PIN_CFG(0x010C, 0x0398, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS(p)                        PIN_CFG(0x010C, 0x0398, 0x0638, 0x2, 0x2, p)
+#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK(p)                         PIN_CFG(0x010C, 0x0398, 0x0608, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB(p)                 PIN_CFG(0x010C, 0x0398, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02(p)                           PIN_CFG(0x010C, 0x0398, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1(p)                           PIN_CFG(0x010C, 0x0398, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC(p)                          PIN_CFG(0x0110, 0x039C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY(p)                           PIN_CFG(0x0110, 0x039C, 0x05DC, 0x1, 0x1, p)
+#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS(p)                        PIN_CFG(0x0110, 0x039C, 0x0638, 0x2, 0x3, p)
+#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS(p)                        PIN_CFG(0x0110, 0x039C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA(p)                         PIN_CFG(0x0110, 0x039C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B(p)                         PIN_CFG(0x0110, 0x039C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03(p)                           PIN_CFG(0x0110, 0x039C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2(p)                           PIN_CFG(0x0110, 0x039C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__LCDIF_RESET(p)                          PIN_CFG(0x0114, 0x03A0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__LCDIF_CS(p)                             PIN_CFG(0x0114, 0x03A0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI(p)                     PIN_CFG(0x0114, 0x03A0, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA(p)                         PIN_CFG(0x0114, 0x03A0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY(p)                       PIN_CFG(0x0114, 0x03A0, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__GPIO3_IO04(p)                           PIN_CFG(0x0114, 0x03A0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3(p)                           PIN_CFG(0x0114, 0x03A0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00(p)                        PIN_CFG(0x0118, 0x03A4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__PWM1_OUT(p)                            PIN_CFG(0x0118, 0x03A4, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN(p)                PIN_CFG(0x0118, 0x03A4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__I2C3_SDA(p)                            PIN_CFG(0x0118, 0x03A4, 0x05B8, 0x4, 0x2, p)
+#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05(p)                          PIN_CFG(0x0118, 0x03A4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00(p)                        PIN_CFG(0x0118, 0x03A4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK(p)                           PIN_CFG(0x0118, 0x03A4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__PWM2_OUT(p)                            PIN_CFG(0x011C, 0x03A8, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT(p)               PIN_CFG(0x011C, 0x03A8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__I2C3_SCL(p)                            PIN_CFG(0x011C, 0x03A8, 0x05B4, 0x4, 0x2, p)
+#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06(p)                          PIN_CFG(0x011C, 0x03A8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC(p)                        PIN_CFG(0x011C, 0x03A8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__PWM3_OUT(p)                            PIN_CFG(0x0120, 0x03AC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN(p)                PIN_CFG(0x0120, 0x03AC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__I2C4_SDA(p)                            PIN_CFG(0x0120, 0x03AC, 0x05C0, 0x4, 0x2, p)
+#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07(p)                          PIN_CFG(0x0120, 0x03AC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK(p)                        PIN_CFG(0x0120, 0x03AC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__PWM4_OUT(p)                            PIN_CFG(0x0124, 0x03B0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT(p)               PIN_CFG(0x0124, 0x03B0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__I2C4_SCL(p)                            PIN_CFG(0x0124, 0x03B0, 0x05BC, 0x4, 0x2, p)
+#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08(p)                          PIN_CFG(0x0124, 0x03B0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA(p)                        PIN_CFG(0x0124, 0x03B0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS(p)                       PIN_CFG(0x0128, 0x03B4, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS(p)                       PIN_CFG(0x0128, 0x03B4, 0x0658, 0x1, 0x2, p)
+#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN(p)                PIN_CFG(0x0128, 0x03B4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09(p)                          PIN_CFG(0x0128, 0x03B4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA(p)                        PIN_CFG(0x0128, 0x03B4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05(p)                        PIN_CFG(0x012C, 0x03B8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS(p)                       PIN_CFG(0x012C, 0x03B8, 0x0658, 0x1, 0x3, p)
+#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS(p)                       PIN_CFG(0x012C, 0x03B8, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT(p)               PIN_CFG(0x012C, 0x03B8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT(p)                           PIN_CFG(0x012C, 0x03B8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10(p)                          PIN_CFG(0x012C, 0x03B8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05(p)                        PIN_CFG(0x012C, 0x03B8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1(p)                          PIN_CFG(0x012C, 0x03B8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06(p)                        PIN_CFG(0x0130, 0x03BC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS(p)                       PIN_CFG(0x0130, 0x03BC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS(p)                       PIN_CFG(0x0130, 0x03BC, 0x0650, 0x1, 0x2, p)
+#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN(p)                PIN_CFG(0x0130, 0x03BC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06(p)                        PIN_CFG(0x0130, 0x03BC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2(p)                          PIN_CFG(0x0130, 0x03BC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07(p)                        PIN_CFG(0x0134, 0x03C0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS(p)                       PIN_CFG(0x0134, 0x03C0, 0x0650, 0x1, 0x3, p)
+#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS(p)                       PIN_CFG(0x0134, 0x03C0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT(p)               PIN_CFG(0x0134, 0x03C0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK(p)                       PIN_CFG(0x0134, 0x03C0, 0x061C, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12(p)                          PIN_CFG(0x0134, 0x03C0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07(p)                        PIN_CFG(0x0134, 0x03C0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3(p)                          PIN_CFG(0x0134, 0x03C0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08(p)                        PIN_CFG(0x0138, 0x03C4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__SPDIF_IN(p)                            PIN_CFG(0x0138, 0x03C4, 0x0618, 0x1, 0x2, p)
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__EIM_DATA00(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13(p)                          PIN_CFG(0x0138, 0x03C4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08(p)                        PIN_CFG(0x0138, 0x03C4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX(p)                         PIN_CFG(0x0138, 0x03C4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09(p)                        PIN_CFG(0x013C, 0x03C8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK(p)                           PIN_CFG(0x013C, 0x03C8, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__EIM_DATA01(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14(p)                          PIN_CFG(0x013C, 0x03C8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09(p)                        PIN_CFG(0x013C, 0x03C8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX(p)                         PIN_CFG(0x013C, 0x03C8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__EIM_DATA02(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15(p)                          PIN_CFG(0x0140, 0x03CC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10(p)                        PIN_CFG(0x0140, 0x03CC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX(p)                         PIN_CFG(0x0140, 0x03CC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__EIM_DATA03(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16(p)                          PIN_CFG(0x0144, 0x03D0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11(p)                        PIN_CFG(0x0144, 0x03D0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX(p)                         PIN_CFG(0x0144, 0x03D0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12(p)                        PIN_CFG(0x0148, 0x03D4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC(p)                        PIN_CFG(0x0148, 0x03D4, 0x060C, 0x1, 0x1, p)
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__EIM_DATA04(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12(p)                        PIN_CFG(0x0148, 0x03D4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY(p)                          PIN_CFG(0x0148, 0x03D4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13(p)                        PIN_CFG(0x014C, 0x03D8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK(p)                        PIN_CFG(0x014C, 0x03D8, 0x0608, 0x1, 0x1, p)
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__EIM_DATA05(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18(p)                          PIN_CFG(0x014C, 0x03D8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13(p)                        PIN_CFG(0x014C, 0x03D8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B(p)                      PIN_CFG(0x014C, 0x03D8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__EIM_DATA06(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19(p)                          PIN_CFG(0x0150, 0x03DC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4(p)                        PIN_CFG(0x0150, 0x03DC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__EIM_DATA07(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20(p)                          PIN_CFG(0x0154, 0x03E0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5(p)                        PIN_CFG(0x0154, 0x03E0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__UART7_TX(p)                            PIN_CFG(0x0158, 0x03E4, 0x0654, 0x1, 0x2, p)
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__EIM_DATA08(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21(p)                          PIN_CFG(0x0158, 0x03E4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6(p)                        PIN_CFG(0x0158, 0x03E4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__UART7_RX(p)                            PIN_CFG(0x015C, 0x03E8, 0x0654, 0x1, 0x3, p)
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__EIM_DATA09(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22(p)                          PIN_CFG(0x015C, 0x03E8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7(p)                        PIN_CFG(0x015C, 0x03E8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18(p)                        PIN_CFG(0x0160, 0x03EC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__PWM5_OUT(p)                            PIN_CFG(0x0160, 0x03EC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO(p)                    PIN_CFG(0x0160, 0x03EC, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__EIM_DATA10(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26(p)                        PIN_CFG(0x0160, 0x03EC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD(p)                          PIN_CFG(0x0160, 0x03EC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__EIM_DATA11(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27(p)                        PIN_CFG(0x0164, 0x03F0, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19(p)                        PIN_CFG(0x0164, 0x03F0, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__PWM6_OUT(p)                            PIN_CFG(0x0164, 0x03F0, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY(p)                      PIN_CFG(0x0164, 0x03F0, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11(p)                          PIN_CFG(0x0164, 0x03F0, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__EIM_DATA12(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20(p)                        PIN_CFG(0x0168, 0x03F4, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__UART8_TX(p)                            PIN_CFG(0x0168, 0x03F4, 0x065C, 0x1, 0x2, p)
+#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK(p)                         PIN_CFG(0x0168, 0x03F4, 0x0534, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12(p)                          PIN_CFG(0x0168, 0x03F4, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__UART8_RX(p)                            PIN_CFG(0x016C, 0x03F8, 0x065C, 0x1, 0x3, p)
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__EIM_DATA13(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26(p)                          PIN_CFG(0x016C, 0x03F8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1(p)                        PIN_CFG(0x016C, 0x03F8, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT(p)                           PIN_CFG(0x0170, 0x03FC, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI(p)                         PIN_CFG(0x0170, 0x03FC, 0x053C, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__EIM_DATA14(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27(p)                          PIN_CFG(0x0170, 0x03FC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2(p)                        PIN_CFG(0x0170, 0x03FC, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__MQS_LEFT(p)                            PIN_CFG(0x0174, 0x0400, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO(p)                         PIN_CFG(0x0174, 0x0400, 0x0538, 0x2, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__EIM_DATA15(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28(p)                          PIN_CFG(0x0174, 0x0400, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3(p)                        PIN_CFG(0x0174, 0x0400, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B(p)                         PIN_CFG(0x0178, 0x0404, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK(p)                           PIN_CFG(0x0178, 0x0404, 0x0670, 0x1, 0x2, p)
+#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK(p)                          PIN_CFG(0x0178, 0x0404, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00(p)                            PIN_CFG(0x0178, 0x0404, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2(p)                           PIN_CFG(0x0178, 0x0404, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B(p)                         PIN_CFG(0x017C, 0x0408, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD(p)                           PIN_CFG(0x017C, 0x0408, 0x0678, 0x1, 0x2, p)
+#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B(p)                         PIN_CFG(0x017C, 0x0408, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00(p)                            PIN_CFG(0x017C, 0x0408, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3(p)                           PIN_CFG(0x017C, 0x0408, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00(p)                     PIN_CFG(0x0180, 0x040C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0(p)                       PIN_CFG(0x0180, 0x040C, 0x067C, 0x1, 0x2, p)
+#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B(p)                       PIN_CFG(0x0180, 0x040C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01(p)                          PIN_CFG(0x0180, 0x040C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__EIM_AD08(p)                           PIN_CFG(0x0180, 0x040C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02(p)                         PIN_CFG(0x0180, 0x040C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY(p)                         PIN_CFG(0x0180, 0x040C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01(p)                     PIN_CFG(0x0184, 0x0410, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1(p)                       PIN_CFG(0x0184, 0x0410, 0x0680, 0x1, 0x2, p)
+#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01(p)                          PIN_CFG(0x0184, 0x0410, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__EIM_AD09(p)                           PIN_CFG(0x0184, 0x0410, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1(p)                         PIN_CFG(0x0184, 0x0410, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02(p)                     PIN_CFG(0x0188, 0x0414, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2(p)                       PIN_CFG(0x0188, 0x0414, 0x0684, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00(p)                      PIN_CFG(0x0188, 0x0414, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02(p)                          PIN_CFG(0x0188, 0x0414, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__EIM_AD10(p)                           PIN_CFG(0x0188, 0x0414, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04(p)                         PIN_CFG(0x0188, 0x0414, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2(p)                         PIN_CFG(0x0188, 0x0414, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03(p)                     PIN_CFG(0x018C, 0x0418, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3(p)                       PIN_CFG(0x018C, 0x0418, 0x0688, 0x1, 0x2, p)
+#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01(p)                      PIN_CFG(0x018C, 0x0418, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02(p)                          PIN_CFG(0x018C, 0x0418, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__EIM_AD11(p)                           PIN_CFG(0x018C, 0x0418, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05(p)                         PIN_CFG(0x018C, 0x0418, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3(p)                         PIN_CFG(0x018C, 0x0418, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04(p)                     PIN_CFG(0x0190, 0x041C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4(p)                       PIN_CFG(0x0190, 0x041C, 0x068C, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02(p)                      PIN_CFG(0x0190, 0x041C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK(p)                        PIN_CFG(0x0190, 0x041C, 0x0564, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_DATA04__EIM_AD12(p)                           PIN_CFG(0x0190, 0x041C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06(p)                         PIN_CFG(0x0190, 0x041C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA04__UART2_TX(p)                           PIN_CFG(0x0190, 0x041C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05(p)                     PIN_CFG(0x0194, 0x0420, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5(p)                       PIN_CFG(0x0194, 0x0420, 0x0690, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03(p)                      PIN_CFG(0x0194, 0x0420, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI(p)                        PIN_CFG(0x0194, 0x0420, 0x056C, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_DATA05__EIM_AD13(p)                           PIN_CFG(0x0194, 0x0420, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07(p)                         PIN_CFG(0x0194, 0x0420, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA05__UART2_RX(p)                           PIN_CFG(0x0194, 0x0420, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06(p)                     PIN_CFG(0x0198, 0x0424, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6(p)                       PIN_CFG(0x0198, 0x0424, 0x0694, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK(p)                       PIN_CFG(0x0198, 0x0424, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO(p)                        PIN_CFG(0x0198, 0x0424, 0x0568, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_DATA06__EIM_AD14(p)                           PIN_CFG(0x0198, 0x0424, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08(p)                         PIN_CFG(0x0198, 0x0424, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS(p)                      PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS(p)                      PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07(p)                     PIN_CFG(0x019C, 0x0428, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7(p)                       PIN_CFG(0x019C, 0x0428, 0x0698, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B(p)                       PIN_CFG(0x019C, 0x0428, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0(p)                         PIN_CFG(0x019C, 0x0428, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__EIM_AD15(p)                           PIN_CFG(0x019C, 0x0428, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09(p)                         PIN_CFG(0x019C, 0x0428, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS(p)                      PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS(p)                      PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE(p)                           PIN_CFG(0x01A0, 0x042C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B(p)                        PIN_CFG(0x01A0, 0x042C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__PWM3_OUT(p)                              PIN_CFG(0x01A0, 0x042C, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__EIM_ADDR17(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__GPIO4_IO10(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1(p)                            PIN_CFG(0x01A0, 0x042C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B(p)                         PIN_CFG(0x01A4, 0x0430, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B(p)                       PIN_CFG(0x01A4, 0x0430, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK(p)                          PIN_CFG(0x01A4, 0x0430, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__PWM4_OUT(p)                             PIN_CFG(0x01A4, 0x0430, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__EIM_BCLK(p)                             PIN_CFG(0x01A4, 0x0430, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11(p)                           PIN_CFG(0x01A4, 0x0430, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY(p)                           PIN_CFG(0x01A4, 0x0430, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B(p)                   PIN_CFG(0x01A8, 0x0434, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4(p)                      PIN_CFG(0x01A8, 0x0434, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00(p)                     PIN_CFG(0x01A8, 0x0434, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0(p)                        PIN_CFG(0x01A8, 0x0434, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B(p)                         PIN_CFG(0x01A8, 0x0434, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12(p)                        PIN_CFG(0x01A8, 0x0434, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_READY_B__UART3_TX(p)                          PIN_CFG(0x01A8, 0x0434, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B(p)                       PIN_CFG(0x01AC, 0x0438, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5(p)                        PIN_CFG(0x01AC, 0x0438, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01(p)                       PIN_CFG(0x01AC, 0x0438, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK(p)                         PIN_CFG(0x01AC, 0x0438, 0x0554, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B(p)                         PIN_CFG(0x01AC, 0x0438, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13(p)                          PIN_CFG(0x01AC, 0x0438, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_CE0_B__UART3_RX(p)                            PIN_CFG(0x01AC, 0x0438, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6(p)                        PIN_CFG(0x01B0, 0x043C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI(p)                         PIN_CFG(0x01B0, 0x043C, 0x055C, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18(p)                          PIN_CFG(0x01B0, 0x043C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14(p)                          PIN_CFG(0x01B0, 0x043C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS(p)                       PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE(p)                           PIN_CFG(0x01B4, 0x0440, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7(p)                          PIN_CFG(0x01B4, 0x0440, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO(p)                           PIN_CFG(0x01B4, 0x0440, 0x0558, 0x3, 0x1, p)
+#define MX6UL_PAD_NAND_CLE__EIM_ADDR16(p)                            PIN_CFG(0x01B4, 0x0440, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__GPIO4_IO15(p)                            PIN_CFG(0x01B4, 0x0440, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS(p)                         PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS(p)                           PIN_CFG(0x01B8, 0x0444, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__CSI_FIELD(p)                             PIN_CFG(0x01B8, 0x0444, 0x0530, 0x1, 0x1, p)
+#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B(p)                          PIN_CFG(0x01B8, 0x0444, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__PWM5_OUT(p)                              PIN_CFG(0x01B8, 0x0444, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__EIM_WAIT(p)                              PIN_CFG(0x01B8, 0x0444, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__GPIO4_IO16(p)                            PIN_CFG(0x01B8, 0x0444, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01(p)                      PIN_CFG(0x01B8, 0x0444, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK(p)                         PIN_CFG(0x01B8, 0x0444, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__USDHC1_CMD(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1(p)                          PIN_CFG(0x01BC, 0x0448, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC(p)                           PIN_CFG(0x01BC, 0x0448, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__SPDIF_OUT(p)                              PIN_CFG(0x01BC, 0x0448, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__EIM_ADDR19(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__GPIO2_IO16(p)                             PIN_CFG(0x01BC, 0x0448, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00(p)                       PIN_CFG(0x01BC, 0x0448, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR(p)                           PIN_CFG(0x01BC, 0x0448, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__USDHC1_CLK(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2(p)                          PIN_CFG(0x01C0, 0x044C, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK(p)                              PIN_CFG(0x01C0, 0x044C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__SPDIF_IN(p)                               PIN_CFG(0x01C0, 0x044C, 0x0618, 0x3, 0x3, p)
+#define MX6UL_PAD_SD1_CLK__EIM_ADDR20(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__GPIO2_IO17(p)                             PIN_CFG(0x01C0, 0x044C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC(p)                            PIN_CFG(0x01C0, 0x044C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0(p)                         PIN_CFG(0x01C4, 0x0450, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3(p)                        PIN_CFG(0x01C4, 0x0450, 0x0000, 0x1, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC(p)                         PIN_CFG(0x01C4, 0x0450, 0x05FC, 0x2, 0x1, p)
+#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX(p)                          PIN_CFG(0x01C4, 0x0450, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21(p)                           PIN_CFG(0x01C4, 0x0450, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18(p)                           PIN_CFG(0x01C4, 0x0450, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID(p)                       PIN_CFG(0x01C4, 0x0450, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1(p)                         PIN_CFG(0x01C8, 0x0454, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_DATA1__GPT2_CLK(p)                             PIN_CFG(0x01C8, 0x0454, 0x05A0, 0x1, 0x1, p)
+#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK(p)                         PIN_CFG(0x01C8, 0x0454, 0x05F8, 0x2, 0x1, p)
+#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX(p)                          PIN_CFG(0x01C8, 0x0454, 0x0584, 0x3, 0x3, p)
+#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22(p)                           PIN_CFG(0x01C8, 0x0454, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19(p)                           PIN_CFG(0x01C8, 0x0454, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR(p)                         PIN_CFG(0x01C8, 0x0454, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2(p)                         PIN_CFG(0x01CC, 0x0458, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1(p)                        PIN_CFG(0x01CC, 0x0458, 0x0598, 0x1, 0x1, p)
+#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA(p)                         PIN_CFG(0x01CC, 0x0458, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX(p)                          PIN_CFG(0x01CC, 0x0458, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23(p)                           PIN_CFG(0x01CC, 0x0458, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20(p)                           PIN_CFG(0x01CC, 0x0458, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1(p)                            PIN_CFG(0x01CC, 0x0458, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC(p)                          PIN_CFG(0x01CC, 0x0458, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3(p)                         PIN_CFG(0x01D0, 0x045C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2(p)                        PIN_CFG(0x01D0, 0x045C, 0x059C, 0x1, 0x1, p)
+#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA(p)                         PIN_CFG(0x01D0, 0x045C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX(p)                          PIN_CFG(0x01D0, 0x045C, 0x0588, 0x3, 0x3, p)
+#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24(p)                           PIN_CFG(0x01D0, 0x045C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21(p)                           PIN_CFG(0x01D0, 0x045C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2(p)                            PIN_CFG(0x01D0, 0x045C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID(p)                       PIN_CFG(0x01D0, 0x045C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__CSI_MCLK(p)                              PIN_CFG(0x01D4, 0x0460, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B(p)                           PIN_CFG(0x01D4, 0x0460, 0x0674, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B(p)                         PIN_CFG(0x01D4, 0x0460, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__I2C1_SDA(p)                              PIN_CFG(0x01D4, 0x0460, 0x05A8, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B(p)                             PIN_CFG(0x01D4, 0x0460, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17(p)                            PIN_CFG(0x01D4, 0x0460, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL(p)                     PIN_CFG(0x01D4, 0x0460, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_MCLK__UART6_TX(p)                              PIN_CFG(0x01D4, 0x0460, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK(p)                          PIN_CFG(0x01D8, 0x0464, 0x0528, 0x0, 0x1, p)
+#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP(p)                           PIN_CFG(0x01D8, 0x0464, 0x069C, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B(p)                       PIN_CFG(0x01D8, 0x0464, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL(p)                            PIN_CFG(0x01D8, 0x0464, 0x05A4, 0x3, 0x2, p)
+#define MX6UL_PAD_CSI_PIXCLK__EIM_OE(p)                              PIN_CFG(0x01D8, 0x0464, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18(p)                          PIN_CFG(0x01D8, 0x0464, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5(p)                       PIN_CFG(0x01D8, 0x0464, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_PIXCLK__UART6_RX(p)                            PIN_CFG(0x01D8, 0x0464, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC(p)                            PIN_CFG(0x01DC, 0x0468, 0x052C, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK(p)                           PIN_CFG(0x01DC, 0x0468, 0x0670, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK(p)                       PIN_CFG(0x01DC, 0x0468, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA(p)                             PIN_CFG(0x01DC, 0x0468, 0x05B0, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__EIM_RW(p)                               PIN_CFG(0x01DC, 0x0468, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19(p)                           PIN_CFG(0x01DC, 0x0468, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT(p)                             PIN_CFG(0x01DC, 0x0468, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS(p)                        PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS(p)                        PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC(p)                            PIN_CFG(0x01E0, 0x046C, 0x0524, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD(p)                           PIN_CFG(0x01E0, 0x046C, 0x0678, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL(p)                             PIN_CFG(0x01E0, 0x046C, 0x05AC, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B(p)                            PIN_CFG(0x01E0, 0x046C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20(p)                           PIN_CFG(0x01E0, 0x046C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT(p)                             PIN_CFG(0x01E0, 0x046C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS(p)                        PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__CSI_DATA02(p)                          PIN_CFG(0x01E4, 0x0470, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0(p)                        PIN_CFG(0x01E4, 0x0470, 0x067C, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B(p)                    PIN_CFG(0x01E4, 0x0470, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK(p)                         PIN_CFG(0x01E4, 0x0470, 0x0544, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__EIM_AD00(p)                            PIN_CFG(0x01E4, 0x0470, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21(p)                          PIN_CFG(0x01E4, 0x0470, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT(p)                        PIN_CFG(0x01E4, 0x0470, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA00__UART5_TX(p)                            PIN_CFG(0x01E4, 0x0470, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__CSI_DATA03(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1(p)                        PIN_CFG(0x01E8, 0x0474, 0x0680, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN(p)                     PIN_CFG(0x01E8, 0x0474, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__EIM_AD01(p)                            PIN_CFG(0x01E8, 0x0474, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22(p)                          PIN_CFG(0x01E8, 0x0474, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK(p)                           PIN_CFG(0x01E8, 0x0474, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA01__UART5_RX(p)                            PIN_CFG(0x01E8, 0x0474, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__CSI_DATA04(p)                          PIN_CFG(0x01EC, 0x0478, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2(p)                        PIN_CFG(0x01EC, 0x0478, 0x0684, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD(p)                     PIN_CFG(0x01EC, 0x0478, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI(p)                         PIN_CFG(0x01EC, 0x0478, 0x054C, 0x3, 0x1, p)
+#define MX6UL_PAD_CSI_DATA02__EIM_AD02(p)                            PIN_CFG(0x01EC, 0x0478, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23(p)                          PIN_CFG(0x01EC, 0x0478, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC(p)                        PIN_CFG(0x01EC, 0x0478, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS(p)                       PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS(p)                       PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__CSI_DATA05(p)                          PIN_CFG(0x01F0, 0x047C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3(p)                        PIN_CFG(0x01F0, 0x047C, 0x0688, 0x1, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO(p)                         PIN_CFG(0x01F0, 0x047C, 0x0548, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__EIM_AD03(p)                            PIN_CFG(0x01F0, 0x047C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24(p)                          PIN_CFG(0x01F0, 0x047C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK(p)                        PIN_CFG(0x01F0, 0x047C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS(p)                       PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA04__CSI_DATA06(p)                          PIN_CFG(0x01F4, 0x0480, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4(p)                        PIN_CFG(0x01F4, 0x0480, 0x068C, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK(p)                      PIN_CFG(0x01F4, 0x0480, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK(p)                         PIN_CFG(0x01F4, 0x0480, 0x0534, 0x3, 0x1, p)
+#define MX6UL_PAD_CSI_DATA04__EIM_AD04(p)                            PIN_CFG(0x01F4, 0x0480, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25(p)                          PIN_CFG(0x01F4, 0x0480, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC(p)                        PIN_CFG(0x01F4, 0x0480, 0x05EC, 0x6, 0x1, p)
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP(p)                           PIN_CFG(0x01F4, 0x0480, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__CSI_DATA07(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5(p)                        PIN_CFG(0x01F8, 0x0484, 0x0690, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B(p)                    PIN_CFG(0x01F8, 0x0484, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x3, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__EIM_AD05(p)                            PIN_CFG(0x01F8, 0x0484, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26(p)                          PIN_CFG(0x01F8, 0x0484, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK(p)                        PIN_CFG(0x01F8, 0x0484, 0x05E8, 0x6, 0x1, p)
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B(p)                         PIN_CFG(0x01F8, 0x0484, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__CSI_DATA08(p)                          PIN_CFG(0x01FC, 0x0488, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6(p)                        PIN_CFG(0x01FC, 0x0488, 0x0694, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN(p)                     PIN_CFG(0x01FC, 0x0488, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI(p)                         PIN_CFG(0x01FC, 0x0488, 0x053C, 0x3, 0x1, p)
+#define MX6UL_PAD_CSI_DATA06__EIM_AD06(p)                            PIN_CFG(0x01FC, 0x0488, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27(p)                          PIN_CFG(0x01FC, 0x0488, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA(p)                        PIN_CFG(0x01FC, 0x0488, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B(p)                      PIN_CFG(0x01FC, 0x0488, 0x0000, 0x8, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__CSI_DATA09(p)                          PIN_CFG(0x0200, 0x048C, 0x0000, 0x0, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7(p)                        PIN_CFG(0x0200, 0x048C, 0x0698, 0x1, 0x2, p)
+#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD(p)                     PIN_CFG(0x0200, 0x048C, 0x0000, 0x2, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO(p)                         PIN_CFG(0x0200, 0x048C, 0x0538, 0x3, 0x1, p)
+#define MX6UL_PAD_CSI_DATA07__EIM_AD07(p)                            PIN_CFG(0x0200, 0x048C, 0x0000, 0x4, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28(p)                          PIN_CFG(0x0200, 0x048C, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA(p)                        PIN_CFG(0x0200, 0x048C, 0x0000, 0x6, 0x0, p)
+#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT(p)                      PIN_CFG(0x0200, 0x048C, 0x0000, 0x8, 0x0, p)
+
+/*
+ * The TAMPER Pin can be used for GPIO, which depends on
+ * TAMPER_PIN_DISABLE[1:0] settings.
+ */
+#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00(p)                        PIN_CFG(0x001C, 0x02A8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01(p)                        PIN_CFG(0x0020, 0x02AC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02(p)                        PIN_CFG(0x0024, 0x02B0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03(p)                        PIN_CFG(0x0028, 0x02B4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04(p)                        PIN_CFG(0x002C, 0x02B8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05(p)                        PIN_CFG(0x0030, 0x02BC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06(p)                        PIN_CFG(0x0034, 0x02C0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07(p)                        PIN_CFG(0x0038, 0x02C4, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08(p)                        PIN_CFG(0x003C, 0x02C8, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09(p)                        PIN_CFG(0x0040, 0x02CC, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10(p)                          PIN_CFG(0x0014, 0x02A0, 0x0000, 0x5, 0x0, p)
+#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11(p)                          PIN_CFG(0x0018, 0x02A4, 0x0000, 0x5, 0x0, p)
+
+#endif /* __DTS_IMX6UL_PINFUNC_H */

bsp/imx6ul/platform/include/mx6ul/iomux_define.h

@@ -0,0 +1,107 @@
+#ifndef _IOMUX_DEFINE_H_
+#define _IOMUX_DEFINE_H_
+
+#include "soc_memory_map.h"
+
+// IOMUXC_SW_MUX_CTL_PAD_*
+// SION
+#define SION_DISABLED 0x0
+#define SION_ENABLED  0x1
+// MUX_MODE
+#define ALT0 0x0
+#define ALT1 0x1
+#define ALT2 0x2
+#define ALT3 0x3
+#define ALT4 0x4
+#define ALT5 0x5
+#define ALT6 0x6
+#define ALT7 0x7
+
+// IOMUXC_SW_PAD_CTL_PAD_*
+// IOMUXC_SW_PAD_CTL_GRP_*
+// LVE
+#define LVE_DISABLED 0x0
+#define LVE_ENABLED  0x1
+// HYS
+#define HYS_DISABLED 0x0
+#define HYS_ENABLED  0x1
+// PUS
+#define PUS_100KOHM_PD 0x0
+#define PUS_47KOHM_PU  0x1
+#define PUS_100KOHM_PU 0x2
+#define PUS_22KOHM_PU  0x3
+// PUE
+#define PUE_KEEP 0x0
+#define PUE_PULL 0x1
+// PKE
+#define PKE_DISABLED 0x0
+#define PKE_ENABLED  0x1
+// ODE
+#define ODE_DISABLED 0x0
+#define ODE_ENABLED  0x1
+// SPEED
+#define SPD_TBD    0x0
+#define SPD_50MHZ  0x1
+#define SPD_100MHZ 0x2
+#define SPD_200MHZ 0x3
+// DSE
+#define DSE_DISABLED 0x0
+#define DSE_240OHM   0x1
+#define DSE_120OHM   0x2
+#define DSE_80OHM    0x3
+#define DSE_60OHM    0x4
+#define DSE_48OHM    0x5
+#define DSE_40OHM    0x6
+#define DSE_34OHM    0x7
+// SRE
+#define SRE_SLOW 0x0
+#define SRE_FAST 0x1
+// ODT
+#define ODT_OFF    0x0
+#define ODT_120OHM 0x1
+#define ODT_60OHM  0x2
+#define ODT_40OHM  0x3
+#define ODT_30OHM  0x4
+#define ODT_RES5   0x5
+#define ODT_20OHM  0x6
+#define ODT_RES7   0x7
+// DDR_INPUT
+#define DDR_INPUT_CMOS 0x0
+#define DDR_INPUT_DIFF 0x1
+// DDR_SEL
+#define DDR_SEL_LPDDR1_DDR3_DDR2_ODT 0x0
+#define DDR_SEL_DDR2                 0x1
+#define DDR_SEL_LPDDR2               0x2
+#define DDR_SEL_RES0                 0x3
+// DO_TRIM
+#define DO_TRIM_RES0 0x0
+#define DO_TRIM_RES1 0x1
+
+#define MK_PAD(HYS, PUS, PUE, PKE, ODE, SPEED, DSE, SRE) ( \
+		((HYS & 0x1) << 16) | \
+		((PUS & 0x3) << 14) | \
+		((PUE & 0x1) << 13) | \
+		((PKE & 0x1) << 12) | \
+		((ODE & 0x1) << 11) | \
+		((SPEED & 0x3) << 6 ) | \
+		((DSE & 0x7) << 3 ) | \
+		((SRE & 0x1) << 0 ) )
+
+#define PAD_ENET_INPUT	MK_PAD(1, 0, 0, 0, 0, 3, 5, 1)
+#define PAD_ENET_OUTPUT	MK_PAD(0, 0, 0, 0, 0, 3, 5, 1)
+#define PAD_ENET_CTRL	MK_PAD(0, 0, 0, 0, 0, 0, 3, 1)
+#define PAD_GPIO_OUTPUT	MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
+#define PAD_GPIO_INPUT	MK_PAD(0, 1, 1, 1, 0, 0, 2, 0)
+#define PAD_UART_OUTPUT	MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
+#define PAD_UART_INPUT	MK_PAD(0, 2, 0, 0, 0, 0, 2, 0)
+#define PAD_I2C			MK_PAD(0, 2, 0, 0, 1, 0, 2, 0)
+#define PAD_I2C4		MK_PAD(0, 2, 0, 0, 1, 0, 4, 0)
+#define PAD_LCD_DATA	MK_PAD(0, 0, 0, 0, 0, 2, 3, 1)
+#define PAD_AUDMUX		MK_PAD(0, 0, 0, 0, 0, 0, 5, 1)
+#define PAD_CAN			MK_PAD(0, 0, 0, 0, 0, 0, 2, 0)
+#define PAD_SDHC_DATA	MK_PAD(0, 1, 1, 1, 0, 2, 3, 1)
+#define PAD_QSPI		MK_PAD(0, 0, 0, 0, 0, 3, 3, 1)
+#define PAD_QSPI_PU		MK_PAD(0, 1, 1, 1, 0, 3, 3, 1)
+
+#endif
+

bsp/imx6ul/platform/include/mx6ul/iomux_register.h

@@ -0,0 +1,5 @@
+#ifndef _IOMUX_REGISTER_H_
+#define _IOMUX_REGISTER_H_
+#include "imx6ul-pinfunc.h"
+#endif
+

bsp/imx6ul/platform/include/mx6ul/irq_numbers.h

@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#if !defined(__IRQ_NUMBERS_H__)
+#define __IRQ_NUMBERS_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief i.MX6 interrupt numbers.
+//!
+//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
+//! Use these numbers when specifying an interrupt to the GIC.
+//!
+//! The first 16 interrupts are special in that they are reserved for software interrupts generated
+//! by the SWI instruction.
+enum _imx_interrupts
+{
+    SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
+    SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
+    SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
+    SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
+    SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
+    SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
+    SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
+    SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
+    SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
+    SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
+    SW_INTERRUPT_10 = 10,   //!< Software interrupt 10.
+    SW_INTERRUPT_11 = 11,   //!< Software interrupt 11.
+    SW_INTERRUPT_12 = 12,   //!< Software interrupt 12.
+    SW_INTERRUPT_13 = 13,   //!< Software interrupt 13.
+    SW_INTERRUPT_14 = 14,   //!< Software interrupt 14.
+    SW_INTERRUPT_15 = 15,   //!< Software interrupt 15.
+    RSVD_INTERRUPT_16 = 16, //!< Reserved.
+    RSVD_INTERRUPT_17 = 17, //!< Reserved.
+    RSVD_INTERRUPT_18 = 18, //!< Reserved.
+    RSVD_INTERRUPT_19 = 19, //!< Reserved.
+    RSVD_INTERRUPT_20 = 20, //!< Reserved.
+    RSVD_INTERRUPT_21 = 21, //!< Reserved.
+    RSVD_INTERRUPT_22 = 22, //!< Reserved.
+    RSVD_INTERRUPT_23 = 23, //!< Reserved.
+    RSVD_INTERRUPT_24 = 24, //!< Reserved.
+    RSVD_INTERRUPT_25 = 25, //!< Reserved.
+    RSVD_INTERRUPT_26 = 26, //!< Reserved.
+    RSVD_INTERRUPT_27 = 27, //!< Reserved.
+    RSVD_INTERRUPT_28 = 28, //!< Reserved.
+    RSVD_INTERRUPT_29 = 29, //!< Reserved.
+    RSVD_INTERRUPT_30 = 30, //!< Reserved.
+    RSVD_INTERRUPT_31 = 31, //!< Reserved.
+    IMX_INT_IOMUXC_GPR = 32,   //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot.
+    IMX_INT_CHEETAH_CSYSPWRUPREQ = 33,  //!< @todo Listed as DAP in RM
+    IMX_INT_SDMA = 34,  //!< Logical OR of all 48 SDMA interrupt requests/events from all channels.
+    IMX_INT_TSC = 35,   //!< TSC
+    IMX_INT_SNVS_LP_SET_PWR_OFF = 36,   //!< PMIC power off request.
+    IMX_INT_LCDIF = 37,  //!< LCDIF interrupt request.
+    IMX_INT_BEE = 38, //!< BEE interrupt request.
+    IMX_INT_CSI = 39,  //!< CMOS Sensor Interface interrupt request.
+    IMX_INT_PXP = 40,    //!< PXP interrupt request.
+    IMX_INT_SCTR1 = 41, //!< SCTR1
+    IMX_INT_SCTR2 = 42, //!< SCTR2
+    IMX_INT_WDOG3 = 43,    //!< WDOG3 timer reset interrupt request.
+    IMX_INT_INTERRUPT_44 = 44,   //!< Reserved.
+    IMX_INT_APBH_DMA = 45,   //!< APBH DMA
+    IMX_INT_EIM = 46,   //!< EIM interrupt request.
+    IMX_INT_NAND_BCH = 47,   //!< Reserved.
+    IMX_INT_NAND_GPMI = 48,  //!< Reserved.
+    IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests.
+    IMX_INT_INTERRUPT_50 = 50,  //!< Reserved.
+    IMX_INT_SNVS = 51,  //!< SNVS consolidated interrupt.
+    IMX_INT_SNVS_SEC = 52,  //!< SNVS security interrupt.
+    IMX_INT_CSU = 53,   //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted.
+    IMX_INT_USDHC1 = 54,    //!< uSDHC1 (Enhanced SDHC) interrupt request.
+    IMX_INT_USDHC2 = 55,    //!< uSDHC2 (Enhanced SDHC) interrupt request.
+    IMX_INT_SAI3 = 56,    //!< uSDHC3 (Enhanced SDHC) interrupt request.
+    IMX_INT_SAI4 = 57,    //!< uSDHC4 (Enhanced SDHC) interrupt request.
+    IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests.
+    IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests.
+    IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests.
+    IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests.
+    IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests.
+    IMX_INT_ECSPI1 = 63,    //!< eCSPI1 interrupt request.
+    IMX_INT_ECSPI2 = 64,    //!< eCSPI2 interrupt request.
+    IMX_INT_ECSPI3 = 65,    //!< eCSPI3 interrupt request.
+    IMX_INT_ECSPI4 = 66,    //!< eCSPI4 interrupt request.
+    IMX_INT_I2C4 = 67,    //!< Reserved.
+    IMX_INT_I2C1 = 68,  //!< I2C1 interrupt request.
+    IMX_INT_I2C2 = 69,  //!< I2C2 interrupt request.
+    IMX_INT_I2C3 = 70,  //!< I2C3 interrupt request.
+    IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests.
+    IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests.
+    IMX_INT_INTERRUPT_73 = 73,    //!< Reserved.
+    IMX_INT_USB_OTG2 = 74,    //!< USB Host 1 interrupt request.
+    IMX_INT_USB_OTG1 = 75,   //!< USB OTG1 interrupt request.
+    IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request.
+    IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request.
+    IMX_INT_CAAM_JQ2 = 78,  //!< SSI1 interrupt request.
+    IMX_INT_CAAM_ERR = 79,  //!< SSI2 interrupt request.
+    IMX_INT_CAAM_RTIC = 80,  //!< SSI3 interrupt request.
+    IMX_INT_TEMPERATURE = 81,   //!< Temperature Sensor (temp. greater than threshold) interrupt request.
+    IMX_INT_ASRC = 82,  //!< Reserved.
+    IMX_INT_INTERRUPT_83 = 83,  //!< Reserved.
+    IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts.
+    IMX_INT_INTERRUPT_85 = 85,   //!< Reserved.
+    IMX_INT_PMU_ANA_BO = 86,    //!< PMU analog regulator brown-out interrupt request.
+    IMX_INT_GPT1 = 87,   //
+    IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt.
+    IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt.
+    IMX_INT_GPIO1_INT7 = 90,    //!< INT7 interrupt request.
+    IMX_INT_GPIO1_INT6 = 91,    //!< INT6 interrupt request.
+    IMX_INT_GPIO1_INT5 = 92,    //!< INT5 interrupt request.
+    IMX_INT_GPIO1_INT4 = 93,    //!< INT4 interrupt request.
+    IMX_INT_GPIO1_INT3 = 94,    //!< INT3 interrupt request.
+    IMX_INT_GPIO1_INT2 = 95,    //!< INT2 interrupt request.
+    IMX_INT_GPIO1_INT1 = 96,    //!< INT1 interrupt request.
+    IMX_INT_GPIO1_INT0 = 97,    //!< INT0 interrupt request.
+    IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15.
+    IMX_INT_GPIO1_INT31_16 = 99,    //!< Combined interrupt indication for GPIO1 signals 16 - 31.
+    IMX_INT_GPIO2_INT15_0 = 100,    //!< Combined interrupt indication for GPIO2 signals 0 - 15.
+    IMX_INT_GPIO2_INT31_16 = 101,   //!< Combined interrupt indication for GPIO2 signals 16 - 31.
+    IMX_INT_GPIO3_INT15_0 = 102,    //!< Combined interrupt indication for GPIO3 signals 0 - 15.
+    IMX_INT_GPIO3_INT31_16 = 103,   //!< Combined interrupt indication for GPIO3 signals 16 - 31.
+    IMX_INT_GPIO4_INT15_0 = 104,    //!< Combined interrupt indication for GPIO4 signals 0 - 15.
+    IMX_INT_GPIO4_INT31_16 = 105,   //!< Combined interrupt indication for GPIO4 signals 16 - 31.
+    IMX_INT_GPIO5_INT15_0 = 106,    //!< Combined interrupt indication for GPIO5 signals 0 - 15.
+    IMX_INT_GPIO5_INT31_16 = 107,   //!< Combined interrupt indication for GPIO5 signals 16 - 31.
+    IMX_INT_INTERRUPT_108 = 108,    //!< Reserved.
+    IMX_INT_INTERRUPT_109 = 109,   //!< Reserved.
+    IMX_INT_INTERRUPT_110 = 110,    //!< Reserved.
+    IMX_INT_INTERRUPT_111 = 111,   //!< Reserved.
+    IMX_INT_WDOG1 = 112,    //!< WDOG1 timer reset interrupt request.
+    IMX_INT_WDOG2 = 113,    //!< WDOG2 timer reset interrupt request.
+    IMX_INT_KPP = 114,  //!< Key Pad interrupt request.
+    IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
+    IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
+    IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
+    IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
+    IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1.
+    IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2.
+    IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1.
+    IMX_INT_INTERRUPT_122 = 122, //!< Reserved.
+    IMX_INT_SRC = 123,  //!< SRC interrupt request.
+    IMX_INT_INTERRUPT_124 = 124,   //!< Logical OR of all L2 interrupt requests.
+    IMX_INT_INTERRUPT_125 = 125,   //!< Parity Check error interrupt request.
+    IMX_INT_CHEETAH_PERFORM = 126,  //!< Logical OR of Performance Unit interrupts.
+    IMX_INT_CHEETAH_TRIGGER = 127,  //!< Logical OR of CTI trigger outputs.
+    IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC.
+    IMX_INT_SAI1 = 129,    //!< EPDC interrupt request.
+    IMX_INT_SAI2 = 130,    //!< EPDC interrupt request.
+    IMX_INT_INTERRUPT_131 = 131,    //!< DCP general interrupt request.
+    IMX_INT_ADC1 = 132,    //!< DCP channel 0 interrupt request.
+    IMX_INT_ADC2 = 133,    //!< DCP secure interrupt request.
+    IMX_INT_INTERRUPT_134 = 134,  //!< Reserved.
+    IMX_INT_INTERRUPT_135 = 135,  //!< Reserved.
+    IMX_INT_SJC = 136,  //!< SJC interrupt from General Purpose register.
+    IMX_INT_CAAM_0 = 137,    //!< Reserved.
+    IMX_INT_CAAM_1 = 138,    //!< Reserved.
+    IMX_INT_QSPI = 139,    //!< Reserved.
+    IMX_INT_TZASC1 = 140,   //!< ASC1 interrupt request.
+    IMX_INT_GPT2 = 141,   //!< Reserved.
+    IMX_INT_CAN1 = 142, //!< Reserved.
+    IMX_INT_CAN2 = 143, //!< Reserved.
+    IMX_INT_SIM1 = 144,    //!< Reserved.
+    IMX_INT_SIM2 = 145,    //!< Reserved.
+    IMX_INT_PWM5 = 146,    //!< Fast Ethernet Controller interrupt request.
+    IMX_INT_PWM6 = 147,  //!< Reserved.
+    IMX_INT_PWM7 = 148,   //!< Reserved.
+    IMX_INT_PWM8 = 149, //!< Reserved.
+    IMX_INT_ENET1 = 150, //!< Reserved.
+    IMX_INT_ENET1_TIMER = 151,    //!< Reserved.
+    IMX_INT_ENET2 = 152,   //!< Reserved.
+    IMX_INT_ENET2_TIMER = 153,   //!< Reserved.
+    IMX_INT_INTERRUPT_154 = 154,   //!< Reserved.
+    IMX_INT_INTERRUPT_155 = 155,   //!< Reserved.
+    IMX_INT_INTERRUPT_156 = 156,    //!< Reserved.
+    IMX_INT_INTERRUPT_157 = 157,    //!< Reserved.
+    IMX_INT_INTERRUPT_158 = 158, //!< Reserved.
+    IMX_INT_PMU_DIG_BO = 159,    //!< //!< PMU digital regulator brown-out interrupt request.
+    IMX_INTERRUPT_COUNT = 160   //!< Total number of interrupts.
+};
+
+
+#endif // __IRQ_NUMBERS_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/mx6ul/plat_startup.h

@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+*/
+
+/*!
+ * @file plat_startup.inc
+ * @brief This file contains start-up DCD.
+ *
+ * @ingroup diag_init
+ */
+ /* *INDENT-OFF* */
+#ifndef _PLAT_STARTUP_H_
+#define _PLAT_STARTUP_H_
+
+#include "soc_memory_map.h"
+#define IMAGE_ENTRY_ADDR        0x80000000
+#define IMAGE_SIZE              4*1024*1024
+
+#define L2CC_REG1_CTRL          0x00A02100
+#define L2CC_INV_REG            0x00A0277C
+#define L2CC_TAG_RAM_CTRL       0x00A02108
+#define L2CC_DAT_RAM_CTRL       0x00A0210C
+#define L2CC_PREFETCH_CTRL      0x00A02F60
+
+#define ROM_API_TABLE_BASE_ADDR     (0x00000180)
+#define ROM_API_HWCNFG_SETUP_OFFSET   (0x08)
+
+#define PLATFORM_INIT           plat_dcd_startup
+
+#define ASM_REG32_WR(i, addr, val) \
+    ldr r0, =addr;              \
+    ldr r1, =val;               \
+    str r1, [r0];
+
+// image starts at 0x00907000
+//flash header & DCD @ 0x400
+.macro plat_dcd_startup
+    b startup
+    .org 0x400
+/* First IVT to copy the plugin that initializes the system into OCRAM */
+ivt_header:             .long 0x402000D1    //Tag=0xD1, Len=0x0020, Ver=0x40
+app_code_jump_v:        .long 0x00907458    // Plugin entry point, address after the second IVT table
+reserv1:                .long 0x0
+dcd_ptr:                .long 0x0
+boot_data_ptr:          .long 0x00907420
+self_ptr:               .long 0x00907400
+app_code_csf:           .long 0x0 // reserve 4K for csf
+reserv2:                .long 0x0
+boot_data:              .long 0x00907000
+image_len:              .long 16*1024  
+plugin:                 .long 0x1  // Enable plugin flag
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:            .long 0x402000D1    //Tag=0xD1, Len=0x0020, Ver=0x40
+app2_code_jump_v:       .long startup       // Entry point for the bootloader
+reserv3:                .long 0x0
+dcd2_ptr:               .long 0x0
+boot_data2_ptr:         .long boot_data2
+self_ptr2:              .long ivt2_header
+app_code_csf2:          .long 0x0 // reserve 4K for csf
+reserv4:                .long 0x0
+boot_data2:             .long IMAGE_ENTRY_ADDR
+image_len2:             .long IMAGE_SIZE
+plugin2:                .long 0x0
+
+// Here starts the plugin code
+plugin_start:
+// Save the return address and the function arguments
+    push    {r0-r4, lr}
+
+#if defined(EVB) || defined(SABRE_LITE)
+ASM_REG32_WR(0, 0x020bc000, 0x30)
+
+
+ASM_REG32_WR(0, 0x020c4068, 0xffffffff)
+ASM_REG32_WR(0, 0x020c406c, 0xffffffff)
+ASM_REG32_WR(0, 0x020c4070, 0xffffffff)
+ASM_REG32_WR(0, 0x020c4074, 0xffffffff)
+ASM_REG32_WR(0, 0x020c4078, 0xffffffff)
+ASM_REG32_WR(0, 0x020c407c, 0xffffffff)
+ASM_REG32_WR(0, 0x020c4080, 0xffffffff)
+ASM_REG32_WR(0, 0x020c4084, 0xffffffff)
+
+ASM_REG32_WR(0, 0x020E04B4, 0x000C0000)
+ASM_REG32_WR(0, 0x020E04AC, 0x00000000)
+ASM_REG32_WR(0, 0x020E027C, 0x00000030)
+ASM_REG32_WR(0, 0x020E0250, 0x00000030)
+ASM_REG32_WR(0, 0x020E024C, 0x00000030)
+ASM_REG32_WR(0, 0x020E0490, 0x00000030)
+ASM_REG32_WR(0, 0x020E0288, 0x00000030)
+ASM_REG32_WR(0, 0x020E0270, 0x00000000)
+ASM_REG32_WR(0, 0x020E0260, 0x00000030)
+ASM_REG32_WR(0, 0x020E0264, 0x00000030)
+ASM_REG32_WR(0, 0x020E04A0, 0x00000030)
+ASM_REG32_WR(0, 0x020E0494, 0x00020000)
+ASM_REG32_WR(0, 0x020E0280, 0x00000030)
+ASM_REG32_WR(0, 0x020E0284, 0x00000030)
+ASM_REG32_WR(0, 0x020E04B0, 0x00020000)
+ASM_REG32_WR(0, 0x020E0498, 0x00000030)
+ASM_REG32_WR(0, 0x020E04A4, 0x00000030)
+ASM_REG32_WR(0, 0x020E0244, 0x00000030)
+ASM_REG32_WR(0, 0x020E0248, 0x00000030)
+ASM_REG32_WR(0, 0x021B001C, 0x00008000)
+ASM_REG32_WR(0, 0x021B0800, 0xA1390003)
+ASM_REG32_WR(0, 0x021B080C, 0x001b001E)
+ASM_REG32_WR(0, 0x021B083C, 0x42400240)
+ASM_REG32_WR(0, 0x021B0848, 0x00003A3E)
+ASM_REG32_WR(0, 0x021B0850, 0x00003230)
+ASM_REG32_WR(0, 0x021B081C, 0x33333333)
+ASM_REG32_WR(0, 0x021B0820, 0x33333333)
+ASM_REG32_WR(0, 0x021B082C, 0xf3333333)
+ASM_REG32_WR(0, 0x021B0830, 0xf3333333)
+ASM_REG32_WR(0, 0x021B08C0, 0x00922012)
+ASM_REG32_WR(0, 0x021B08b8, 0x00000800)
+ASM_REG32_WR(0, 0x021B0004, 0x0002002D)
+ASM_REG32_WR(0, 0x021B0008, 0x1B333000)
+ASM_REG32_WR(0, 0x021B000C, 0x676B54B3)
+ASM_REG32_WR(0, 0x021B0010, 0xB68E0A83)
+ASM_REG32_WR(0, 0x021B0014, 0x01FF00DB)
+ASM_REG32_WR(0, 0x021B0018, 0x00211740)
+ASM_REG32_WR(0, 0x021B001C, 0x00008000)
+ASM_REG32_WR(0, 0x021B002C, 0x000026D2)
+ASM_REG32_WR(0, 0x021B0030, 0x006C1023)
+ASM_REG32_WR(0, 0x021B0040, 0x0000005F)
+ASM_REG32_WR(0, 0x021B0000, 0x85180000)
+ASM_REG32_WR(0, 0x021B001C, 0x02008032)
+ASM_REG32_WR(0, 0x021B001C, 0x00008033)
+ASM_REG32_WR(0, 0x021B001C, 0x00048031)
+ASM_REG32_WR(0, 0x021B001C, 0x15208030)
+ASM_REG32_WR(0, 0x021B001C, 0x04008040)
+ASM_REG32_WR(0, 0x021B0020, 0x00000800)
+ASM_REG32_WR(0, 0x021B0818, 0x00000227)
+ASM_REG32_WR(0, 0x021B0004, 0x0002552D)
+ASM_REG32_WR(0, 0x021B0404, 0x00011006)
+ASM_REG32_WR(0, 0x021B001C, 0x00000000)
+
+
+#else
+	#error "Please add the DDR initialization code for this board, unless you can make sure the existing code can be shared."
+#endif
+
+read_obds:
+/********************
+    The following is to fill in those arguments for this ROM function
+    pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+
+    This function is used to copy data from the storage media into DDR.
+
+    start - Initial (possibly partial) image load address on entry.  Final image load address on exit.
+    bytes - Initial (possibly partial) image size on entry.  Final image size on exit.
+    boot_data - Initial @ref ivt Boot Data load address.
+*/
+
+    adr r0, DDR_DEST_ADDR
+    adr r1, COPY_SIZE
+    adr r2, BOOT_DATA
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+    //mov r4, #0x2000
+    //add r4, r4, #0xed
+    //blx r4    // This address might change in future ROM versions.
+    ldr r3, =ROM_API_TABLE_BASE_ADDR         /* Address of rom_api_table is 0xc0 */
+    ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] /* hwcnfg setup function address is 3rd entry in the api table address 0xc8 */
+    blx r4  /* call into ROM function */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* SDRAM has been setup, binary image has been copied to SDRAM */
+	b	startup // Jump to our code directly
+
+DDR_DEST_ADDR:    .word   IMAGE_ENTRY_ADDR
+COPY_SIZE:        .word   IMAGE_SIZE
+BOOT_DATA:        .word   IMAGE_ENTRY_ADDR
+                  .word   IMAGE_SIZE  //real data to be copied by the pu_irom_hwcnfg_setup()
+                  .word   0
+
+.endm   //plat_dcd_startup
+
+// #define PLATFORM_ASM_STARTUP           platform_asm_startup
+.macro platform_asm_startup
+
+config_L2_cache:
+    disable_L2_cache
+
+init_aips_start:
+    init_aips
+
+init_reloc_start:
+    /* Check if need to copy image to Redboot ROM space */
+    ldr r0, =0xFFFFF000
+    and r0, r0, pc
+    ldr r1, =IMAGE_ENTRY_ADDR
+    cmp r0, r1
+    beq skip_SDRAM_copy
+
+    add r2, r0, #IMAGE_SIZE
+
+1:  ldmia r0!, {r3-r10}
+    stmia r1!, {r3-r10}
+    cmp r0, r2
+    ble 1b
+    /* Jump to SDRAM */
+    ldr r1, =0xFFFF
+    and r0, pc, r1         /* offset of pc */
+    ldr r1, =(IMAGE_ENTRY_ADDR + 0x8)
+    add pc, r0, r1
+    nop
+    nop
+    nop
+    nop
+
+skip_SDRAM_copy:
+.endm   //platform_asm_startup
+
+/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+.macro init_aips
+    /*
+     * Set all MPROTx to be non-bufferable, trusted for R/W,
+     * not forced to user-mode.
+     */
+    ldr r0, =AIPS_TZ1_BASE_ADDR
+    ldr r1, =0x77777777
+    str r1, [r0, #0x00]
+    str r1, [r0, #0x04]
+
+    ldr r0, =AIPS_TZ2_BASE_ADDR
+    str r1, [r0, #0x00]
+    str r1, [r0, #0x04]
+
+.endm /* init_aips */
+
+.macro clean_L1_DCache
+	mov r0, #0
+	mcr p15, 2, r0, c0, c0, 0 // select DCache
+	mrc p15, 1, r0, c0, c0, 0 // read CCSIDR
+	mov r0, r0, ASR #13
+	ldr	r3, =0x3FFF
+	and r0, r0, r3
+	cmp r0, #0x7F
+	moveq r6, #0x1000 // 4KB * 4way = 16KB
+	beq	clean_and_invalidate_L1_dcache
+	cmp r0, #0xFF
+	moveq r6, #0x2000 // 32KB
+	beq clean_and_invalidate_L1_dcache
+	movne r6, #0x4000 // 64KB
+
+clean_and_invalidate_L1_dcache:
+	mov r2, #0x00000000
+	mov r3, #0x40000000
+	mov r4, #0x80000000
+	mov r5, #0xC0000000
+
+clean_and_invalidate_L1_dcache_byset:
+	mcr p15, 0, r2, c7, c14, 2 //clean and invalidate dcache on way 0
+	mcr p15, 0, r3, c7, c14, 2 //clean and invalidate dcache on way 1
+	mcr p15, 0, r4, c7, c14, 2 //clean and invalidate dcache on way 2
+	mcr p15, 0, r5, c7, c14, 2 //clean and invalidate dcache on way 3
+	add r2, r2, #0x20
+	add r3, r3, #0x20
+	add r4, r4, #0x20
+	add r5, r5, #0x20
+	
+	cmp r2, r6
+	bne clean_and_invalidate_L1_dcache_byset
+	
+.endm
+
+.macro enable_L1_cache
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 6 // invalidate BTAC
+    mcr p15, 0, r0, c7, c5, 0 // invalidate icache
+    
+    mov r0, #0
+    mcr p15, 2, r0, c0, c0, 0 // select DCache
+    mrc p15, 1, r0, c0, c0, 0 // read CCSIDR
+    mov r0, r0, ASR #13
+    ldr r3, =0x3FFF
+    and r0, r0, r3
+    cmp r0, #0x7F
+    moveq r6, #0x1000 // 4KB * 4way = 16KB
+    beq invalidate_dcache
+    cmp r0, #0xFF
+    moveq r6, #0x2000 // 32KB
+    beq invalidate_dcache
+    movne r6, #0x4000 // 64KB
+
+invalidate_dcache:
+    mov r2, #0x00000000
+    mov r3, #0x40000000
+    mov r4, #0x80000000
+    mov r5, #0xC0000000
+
+invalidate_dcache_byset:
+    mcr p15, 0, r2, c7, c6, 2 //invalidate dcache on way 0
+    mcr p15, 0, r3, c7, c6, 2 //invalidate dcache on way 1
+    mcr p15, 0, r4, c7, c6, 2 //invalidate dcache on way 2
+    mcr p15, 0, r5, c7, c6, 2 //invalidate dcache on way 3
+    add r2, r2, #0x20
+    add r3, r3, #0x20
+    add r4, r4, #0x20
+    add r5, r5, #0x20
+    
+    cmp r2, r6
+    bne invalidate_dcache_byset
+    
+    ldr r0, =0x00930000 //where to store the TLB page table
+    mcr p15, 0, r0, c2, c0, 0
+    ldr r0, =0x55555555
+    mcr p15, 0, r0, c3, c0, 0
+    
+    mrc p15, 0, r0, c1, c0, 0 // read CP15 register 1 into r0
+    orr r0, r0, #(0x1<<12)    // enable I Cache
+    orr r0, r0, #(0x1<<11)    // turn on BP
+    orr r0, r0, #(0x1<<2)     // enable D Cache
+    /*Attention: If you want to enable MMU, must set up the TLB tables first!!*/
+    bic r0, r0, #(0x1<<0)     // disable MMU
+    mcr p15, 0, r0, c1, c0, 0 // write CP15 register 1
+.endm
+
+.macro disable_L1_cache
+    mrc p15, 0, r0, c1, c0, 0
+    bic r0, r0, #(0x1<<12) 
+    bic r0, r0, #(0x1<<11) 
+    bic r0, r0, #(0x1<<2) 
+    bic r0, r0, #(0x1<<0) 
+    mcr p15, 0, r0, c1, c0, 0
+.endm
+
+.macro disable_L1_DCache
+	mrc		p15, 0, r0, c1, c0, 0
+	ands	r0, r0, #(0x1<<11)	//check if L1 DCache has been disabled
+	beq		disable_L1_DCache_done
+	bic r0, r0, #(0x1<<11) 
+	bic r0, r0, #(0x1<<0) //disable MMU 
+	mcr p15, 0, r0, c1, c0, 0
+	clean_L1_DCache
+disable_L1_DCache_done:
+.endm
+
+.macro enable_L2_cache
+    /* set latency: 4x cycles read, 2x cycles write, (3x cycles setup)*/
+    ldr     r1,= L2CC_TAG_RAM_CTRL
+    ldr     r0,=0x0132
+    str     r0,[r1]
+    ldr     r1, =L2CC_DAT_RAM_CTRL
+    ldr     r0,=0x0132
+    str     r0,[r1]
+    
+    /* invalidate L2Cache by way */
+    ldr     r1, =L2CC_INV_REG
+    ldr     r0, =0xffff
+    str     r0,[r1]
+l2cc_inv_done:
+    ldr     r2,[r1]
+    mov     r0,#0x0
+    cmp     r2,r0
+    bne     l2cc_inv_done
+    
+    /* turn on l2 cache */
+    ldr     r1, =L2CC_REG1_CTRL
+    mov     r0,#1
+    str     r0,[r1]
+.endm
+
+.macro disable_L2_cache
+    ldr     r1, =L2CC_REG1_CTRL
+    mov     r0,#0
+    str     r0,[r1]
+.endm
+
+#endif //_PLAT_STARTUP_H_

bsp/imx6ul/platform/include/mx6ul/registers/regs.h

@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+
+#ifndef _REGS_H
+#define _REGS_H  1
+
+//
+// define base address of the register block only if it is not already
+// defined, which allows the compiler to override at build time for
+// users who've mapped their registers to locations other than the
+// physical location
+//
+
+#ifndef REGS_BASE
+#define REGS_BASE 0x00000000
+#endif
+
+//
+// common register types
+//
+
+#ifndef __LANGUAGE_ASM__
+typedef unsigned char reg8_t;
+typedef unsigned short reg16_t;
+typedef unsigned int reg32_t;
+#endif
+
+//
+// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
+// used to simplify macro definitions in the module register headers.
+//
+#ifndef __REG_VALUE_TYPE
+    #ifndef __LANGUAGE_ASM__
+        #define __REG_VALUE_TYPE(v, t) ((t)(v))
+    #else
+        #define __REG_VALUE_TYPE(v, t) (v)
+    #endif
+#endif
+
+//
+// macros for single instance registers
+//
+
+#define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
+#define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
+#define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
+
+#define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RD(reg, field)        HW_##reg.B.field
+#define BF_WR(reg, field, v)     BW_##reg##_##field(v)
+
+#define BF_CS1(reg, f1, v1)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for multiple instance registers
+//
+
+#define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
+#define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
+#define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
+
+#define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RDn(reg, n, field)        HW_##reg(n).B.field
+#define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+//
+// macros for single instance MULTI-BLOCK registers
+//
+
+#define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
+#define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
+#define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
+
+#define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
+#define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
+#define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
+
+#define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
+#define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
+
+#define BFn_CS1(reg, blk, f1, v1)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
+
+#define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for MULTI-BLOCK multiple instance registers
+//
+
+#define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
+#define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
+#define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
+
+#define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
+#define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
+#define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
+
+#define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
+#define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BFn_CS1n(reg, blk, n, f1, v1)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
+
+#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+#endif // _REGS_H
+
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/mx6ul/registers/regsarmglobaltimer.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_ARMGLOBALTIMER_REGISTERS_H__
+#define __HW_ARMGLOBALTIMER_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * i.MX6UL ARMGLOBALTIMER
+ *
+ * ARM Cortex-A9 Global Timer
+ *
+ * Registers defined in this header file:
+ * - HW_ARMGLOBALTIMER_COUNTERn - Global Timer Counter Registers
+ * - HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
+ * - HW_ARMGLOBALTIMER_IRQSTATUS - Global Timer Interrupt Status Register
+ * - HW_ARMGLOBALTIMER_COMPARATORn - Global Timer Comparator Value Registers
+ * - HW_ARMGLOBALTIMER_AUTOINCREMENT - Global Timer Auto-increment Register
+ *
+ * - hw_armglobaltimer_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_ARMGLOBALTIMER_BASE
+#define HW_ARMGLOBALTIMER_INSTANCE_COUNT (1) //!< Number of instances of the ARMGLOBALTIMER module.
+#define REGS_ARMGLOBALTIMER_BASE (0x021DC000) //!< Base address for ARMGLOBALTIMER.
+#endif
+//@}
+
+
+//-------------------------------------------------------------------------------------------
+// HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_ARMGLOBALTIMER_CONTROL - Global Timer Control Register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * Configuration and control of the Global Timer.
+ */
+typedef union _hw_armglobaltimer_control
+{
+    reg32_t U;
+    struct _hw_armglobaltimer_control_bitfields
+    {
+        unsigned TIMER_ENABLE : 1; //!< [0] Timer enable.
+        unsigned DBG_ENABLE : 1; //!< [1] This bit is banked per Cortex-A9 processor.
+        unsigned RESERVED0 : 6; //!< [2] This bit is banked per Cortex-A9 processor.
+        unsigned FCR0 : 1; //!< [3] This bit is banked per Cortex-A9 processor.
+        unsigned FCR1 : 1; //!< [7:4] Reserved
+        unsigned RESERVED1 : 22; //!< [31:16] Reserved.
+    } B;
+} hw_armglobaltimer_control_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire ARMGLOBALTIMER_CONTROL register
+ */
+//@{
+#define HW_ARMGLOBALTIMER_CONTROL_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x000)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ARMGLOBALTIMER_CONTROL           (*(volatile hw_armglobaltimer_control_t *) HW_ARMGLOBALTIMER_CONTROL_ADDR)
+#define HW_ARMGLOBALTIMER_CONTROL_RD()      (HW_ARMGLOBALTIMER_CONTROL.U)
+#define HW_ARMGLOBALTIMER_CONTROL_WR(v)     (HW_ARMGLOBALTIMER_CONTROL.U = (v))
+#define HW_ARMGLOBALTIMER_CONTROL_SET(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() |  (v)))
+#define HW_ARMGLOBALTIMER_CONTROL_CLR(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() & ~(v)))
+#define HW_ARMGLOBALTIMER_CONTROL_TOG(v)    (HW_ARMGLOBALTIMER_CONTROL_WR(HW_ARMGLOBALTIMER_CONTROL_RD() ^  (v)))
+#endif
+//@}
+
+
+#define HW_ARMGLOBALTIMER_COUNTER_LO_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x008)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ARMGLOBALTIMER_COUNTER_LO           (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_LO_ADDR)
+#define HW_ARMGLOBALTIMER_COUNTER_LO_RD()      (HW_ARMGLOBALTIMER_COUNTER_LO)
+#define HW_ARMGLOBALTIMER_COUNTER_LO_WR(v)     (HW_ARMGLOBALTIMER_COUNTER_LO = (v))
+#endif
+
+#define HW_ARMGLOBALTIMER_COUNTER_HI_ADDR      (REGS_ARMGLOBALTIMER_BASE + 0x00C)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_ARMGLOBALTIMER_COUNTER_HI           (*(volatile unsigned *) HW_ARMGLOBALTIMER_COUNTER_HI_ADDR)
+#define HW_ARMGLOBALTIMER_COUNTER_HI_RD()      (HW_ARMGLOBALTIMER_COUNTER_HI)
+#define HW_ARMGLOBALTIMER_COUNTER_HI_WR(v)     (HW_ARMGLOBALTIMER_COUNTER_HI = (v))
+#endif
+
+#endif // __HW_ARMGLOBALTIMER_REGISTERS_H__
+

bsp/imx6ul/platform/include/mx6ul/registers/regsepit.h

@@ -0,0 +1,718 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_EPIT_REGISTERS_H__
+#define __HW_EPIT_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * i.MX6UL EPIT
+ *
+ * EPIT
+ *
+ * Registers defined in this header file:
+ * - HW_EPIT_CR - Control register
+ * - HW_EPIT_SR - Status register
+ * - HW_EPIT_LR - Load register
+ * - HW_EPIT_CMPR - Compare register
+ * - HW_EPIT_CNR - Counter register
+ *
+ * - hw_epit_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_EPIT_BASE
+#define HW_EPIT_INSTANCE_COUNT (2) //!< Number of instances of the EPIT module.
+#define HW_EPIT1 (1) //!< Instance number for EPIT1.
+#define HW_EPIT2 (2) //!< Instance number for EPIT2.
+#define REGS_EPIT1_BASE (0x020d0000) //!< Base address for EPIT instance number 1.
+#define REGS_EPIT2_BASE (0x020d4000) //!< Base address for EPIT instance number 2.
+
+//! @brief Get the base address of EPIT by instance number.
+//! @param x EPIT instance number, from 1 through 2.
+#define REGS_EPIT_BASE(x) ( (x) == HW_EPIT1 ? REGS_EPIT1_BASE : (x) == HW_EPIT2 ? REGS_EPIT2_BASE : 0x00d00000)
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of EPIT.
+#define REGS_EPIT_INSTANCE(b) ( (b) == REGS_EPIT1_BASE ? HW_EPIT1 : (b) == REGS_EPIT2_BASE ? HW_EPIT2 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CR - Control register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CR - Control register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT control register (EPIT_CR) is used to configure the operating settings of the EPIT. It
+ * contains the clock division prescaler value and also the interrupt enable bit. Additionally, it
+ * contains other control bits which are described below. Peripheral Bus Write access to EPIT
+ * Control Register (EPIT_CR) results in one cycle of the wait state, while other valid peripheral
+ * bus accesses are with 0 wait state.
+ */
+typedef union _hw_epit_cr
+{
+    reg32_t U;
+    struct _hw_epit_cr_bitfields
+    {
+        unsigned EN : 1; //!< [0] This bit enables the EPIT.
+        unsigned ENMOD : 1; //!< [1] EPIT enable mode.
+        unsigned OCIEN : 1; //!< [2] Output compare interrupt enable.
+        unsigned RLD : 1; //!< [3] Counter reload control.
+        unsigned PRESCALAR : 12; //!< [15:4] Counter clock prescaler value.
+        unsigned SWR : 1; //!< [16] Software reset.
+        unsigned IOVW : 1; //!< [17] EPIT counter overwrite enable.
+        unsigned DBGEN : 1; //!< [18] This bit is used to keep the EPIT functional in debug mode.
+        unsigned WAITEN : 1; //!< [19] This read/write control bit enables the operation of the EPIT during wait mode.
+        unsigned RESERVED0 : 1; //!< [20] Reserved.
+        unsigned STOPEN : 1; //!< [21] EPIT stop mode enable.
+        unsigned OM : 2; //!< [23:22] EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
+        unsigned CLKSRC : 2; //!< [25:24] Select clock source
+        unsigned RESERVED1 : 6; //!< [31:26] Reserved.
+    } B;
+} hw_epit_cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CR register
+ */
+//@{
+#define HW_EPIT_CR_ADDR(x)      (REGS_EPIT_BASE(x) + 0x0)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CR(x)           (*(volatile hw_epit_cr_t *) HW_EPIT_CR_ADDR(x))
+#define HW_EPIT_CR_RD(x)        (HW_EPIT_CR(x).U)
+#define HW_EPIT_CR_WR(x, v)     (HW_EPIT_CR(x).U = (v))
+#define HW_EPIT_CR_SET(x, v)    (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) |  (v)))
+#define HW_EPIT_CR_CLR(x, v)    (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) & ~(v)))
+#define HW_EPIT_CR_TOG(x, v)    (HW_EPIT_CR_WR(x, HW_EPIT_CR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CR bitfields
+ */
+
+/*! @name Register EPIT_CR, field EN[0] (RW)
+ *
+ * This bit enables the EPIT. EPIT counter and prescaler value when EPIT is enabled (EN = 1), is
+ * dependent upon ENMOD and RLD bit as described for ENMOD bit. It is recommended that all registers
+ * be properly programmed before setting this bit. This bit is reset by a hardware reset. A software
+ * reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - EPIT is disabled
+ * - 1 - EPIT is enabled
+ */
+//@{
+#define BP_EPIT_CR_EN      (0)      //!< Bit position for EPIT_CR_EN.
+#define BM_EPIT_CR_EN      (0x00000001)  //!< Bit mask for EPIT_CR_EN.
+
+//! @brief Get value of EPIT_CR_EN from a register value.
+#define BG_EPIT_CR_EN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_EN) >> BP_EPIT_CR_EN)
+
+//! @brief Format value for bitfield EPIT_CR_EN.
+#define BF_EPIT_CR_EN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_EN) & BM_EPIT_CR_EN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the EN field to a new value.
+#define BW_EPIT_CR_EN(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_EN) | BF_EPIT_CR_EN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field ENMOD[1] (RW)
+ *
+ * EPIT enable mode. When EPIT is disabled (EN=0), both main counter and prescaler counter freeze
+ * their count at current count values. ENMOD bit is a r/w bit that determines the counter value
+ * when the EPIT is enabled again by setting EN bit. If ENMOD bit is set, then main counter is
+ * loaded with the load value (If RLD=1)/ 0xFFFF_FFFF (If RLD=0) and prescaler counter is reset,
+ * when EPIT is enabled (EN=1). If ENMOD is programmed to 0 then both main counter and prescaler
+ * counter restart counting from their frozen values when EPIT is enabled (EN=1). If EPIT is
+ * programmed to be disabled in a low-power mode (STOP/WAIT/DEBUG), then both the main counter and
+ * the prescaler counter freeze at their current count values when EPIT enters low-power mode. When
+ * EPIT exits the low-power mode, both main counter and prescaler counter start counting from their
+ * frozen values irrespective of the ENMOD bit. This bit is reset by a hardware reset. A software
+ * reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - Counter starts counting from the value it had when it was disabled.
+ * - 1 - Counter starts count from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0)
+ */
+//@{
+#define BP_EPIT_CR_ENMOD      (1)      //!< Bit position for EPIT_CR_ENMOD.
+#define BM_EPIT_CR_ENMOD      (0x00000002)  //!< Bit mask for EPIT_CR_ENMOD.
+
+//! @brief Get value of EPIT_CR_ENMOD from a register value.
+#define BG_EPIT_CR_ENMOD(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_ENMOD) >> BP_EPIT_CR_ENMOD)
+
+//! @brief Format value for bitfield EPIT_CR_ENMOD.
+#define BF_EPIT_CR_ENMOD(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_ENMOD) & BM_EPIT_CR_ENMOD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ENMOD field to a new value.
+#define BW_EPIT_CR_ENMOD(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_ENMOD) | BF_EPIT_CR_ENMOD(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field OCIEN[2] (RW)
+ *
+ * Output compare interrupt enable. This bit enables the generation of interrupt on occurrence of
+ * compare event.
+ *
+ * Values:
+ * - 0 - Compare interrupt disabled
+ * - 1 - Compare interrupt enabled
+ */
+//@{
+#define BP_EPIT_CR_OCIEN      (2)      //!< Bit position for EPIT_CR_OCIEN.
+#define BM_EPIT_CR_OCIEN      (0x00000004)  //!< Bit mask for EPIT_CR_OCIEN.
+
+//! @brief Get value of EPIT_CR_OCIEN from a register value.
+#define BG_EPIT_CR_OCIEN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OCIEN) >> BP_EPIT_CR_OCIEN)
+
+//! @brief Format value for bitfield EPIT_CR_OCIEN.
+#define BF_EPIT_CR_OCIEN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OCIEN) & BM_EPIT_CR_OCIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OCIEN field to a new value.
+#define BW_EPIT_CR_OCIEN(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OCIEN) | BF_EPIT_CR_OCIEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field RLD[3] (RW)
+ *
+ * Counter reload control. This bit is cleared by hardware reset. It decides the counter
+ * functionality, whether to run in free-running mode or set-and-forget mode.
+ *
+ * Values:
+ * - 0 - When the counter reaches zero it rolls over to 0xFFFF_FFFF (free-running mode)
+ * - 1 - When the counter reaches zero it reloads from the modulus register (set-and-forget mode)
+ */
+//@{
+#define BP_EPIT_CR_RLD      (3)      //!< Bit position for EPIT_CR_RLD.
+#define BM_EPIT_CR_RLD      (0x00000008)  //!< Bit mask for EPIT_CR_RLD.
+
+//! @brief Get value of EPIT_CR_RLD from a register value.
+#define BG_EPIT_CR_RLD(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_RLD) >> BP_EPIT_CR_RLD)
+
+//! @brief Format value for bitfield EPIT_CR_RLD.
+#define BF_EPIT_CR_RLD(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_RLD) & BM_EPIT_CR_RLD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RLD field to a new value.
+#define BW_EPIT_CR_RLD(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_RLD) | BF_EPIT_CR_RLD(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field PRESCALAR[15:4] (RW)
+ *
+ * Counter clock prescaler value. This bit field determines the prescaler value by which the clock
+ * is divided before it goes to the counter
+ *
+ * Values:
+ * - 0x000 - Divide by 1
+ * - 0x001 - Divide by 2...
+ * - 0xFFF - Divide by 4096
+ */
+//@{
+#define BP_EPIT_CR_PRESCALAR      (4)      //!< Bit position for EPIT_CR_PRESCALAR.
+#define BM_EPIT_CR_PRESCALAR      (0x0000fff0)  //!< Bit mask for EPIT_CR_PRESCALAR.
+
+//! @brief Get value of EPIT_CR_PRESCALAR from a register value.
+#define BG_EPIT_CR_PRESCALAR(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_PRESCALAR) >> BP_EPIT_CR_PRESCALAR)
+
+//! @brief Format value for bitfield EPIT_CR_PRESCALAR.
+#define BF_EPIT_CR_PRESCALAR(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_PRESCALAR) & BM_EPIT_CR_PRESCALAR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the PRESCALAR field to a new value.
+#define BW_EPIT_CR_PRESCALAR(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_PRESCALAR) | BF_EPIT_CR_PRESCALAR(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field SWR[16] (RW)
+ *
+ * Software reset. The EPIT is reset when this bit is set to 1. It is a self clearing bit. This bit
+ * is set when the block is in reset state and is cleared when the reset procedure is over. Setting
+ * this bit resets all the registers to their reset values, except for the EN, ENMOD, STOPEN, WAITEN
+ * and DBGEN bits in this control register
+ *
+ * Values:
+ * - 0 - EPIT is out of reset
+ * - 1 - EPIT is undergoing reset
+ */
+//@{
+#define BP_EPIT_CR_SWR      (16)      //!< Bit position for EPIT_CR_SWR.
+#define BM_EPIT_CR_SWR      (0x00010000)  //!< Bit mask for EPIT_CR_SWR.
+
+//! @brief Get value of EPIT_CR_SWR from a register value.
+#define BG_EPIT_CR_SWR(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_SWR) >> BP_EPIT_CR_SWR)
+
+//! @brief Format value for bitfield EPIT_CR_SWR.
+#define BF_EPIT_CR_SWR(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_SWR) & BM_EPIT_CR_SWR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the SWR field to a new value.
+#define BW_EPIT_CR_SWR(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_SWR) | BF_EPIT_CR_SWR(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field IOVW[17] (RW)
+ *
+ * EPIT counter overwrite enable. This bit controls the counter data when the modulus register is
+ * written. When this bit is set, all writes to the load register overwrites the counter contents
+ * and the counter starts subsequently counting down from the programmed value.
+ *
+ * Values:
+ * - 0 - Write to load register does not result in counter value being overwritten.
+ * - 1 - Write to load register results in immediate overwriting of counter value.
+ */
+//@{
+#define BP_EPIT_CR_IOVW      (17)      //!< Bit position for EPIT_CR_IOVW.
+#define BM_EPIT_CR_IOVW      (0x00020000)  //!< Bit mask for EPIT_CR_IOVW.
+
+//! @brief Get value of EPIT_CR_IOVW from a register value.
+#define BG_EPIT_CR_IOVW(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_IOVW) >> BP_EPIT_CR_IOVW)
+
+//! @brief Format value for bitfield EPIT_CR_IOVW.
+#define BF_EPIT_CR_IOVW(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_IOVW) & BM_EPIT_CR_IOVW)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IOVW field to a new value.
+#define BW_EPIT_CR_IOVW(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_IOVW) | BF_EPIT_CR_IOVW(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field DBGEN[18] (RW)
+ *
+ * This bit is used to keep the EPIT functional in debug mode. When this bit is cleared, the input
+ * clock is gated off in debug mode.This bit is reset by hardware reset. A software reset does not
+ * affect this bit.
+ *
+ * Values:
+ * - 0 - Inactive in debug mode
+ * - 1 - Active in debug mode
+ */
+//@{
+#define BP_EPIT_CR_DBGEN      (18)      //!< Bit position for EPIT_CR_DBGEN.
+#define BM_EPIT_CR_DBGEN      (0x00040000)  //!< Bit mask for EPIT_CR_DBGEN.
+
+//! @brief Get value of EPIT_CR_DBGEN from a register value.
+#define BG_EPIT_CR_DBGEN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_DBGEN) >> BP_EPIT_CR_DBGEN)
+
+//! @brief Format value for bitfield EPIT_CR_DBGEN.
+#define BF_EPIT_CR_DBGEN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_DBGEN) & BM_EPIT_CR_DBGEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DBGEN field to a new value.
+#define BW_EPIT_CR_DBGEN(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_DBGEN) | BF_EPIT_CR_DBGEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field WAITEN[19] (RW)
+ *
+ * This read/write control bit enables the operation of the EPIT during wait mode. This bit is reset
+ * by a hardware reset. A software reset does not affect this bit.
+ *
+ * Values:
+ * - 0 - EPIT is disabled in wait mode
+ * - 1 - EPIT is enabled in wait mode
+ */
+//@{
+#define BP_EPIT_CR_WAITEN      (19)      //!< Bit position for EPIT_CR_WAITEN.
+#define BM_EPIT_CR_WAITEN      (0x00080000)  //!< Bit mask for EPIT_CR_WAITEN.
+
+//! @brief Get value of EPIT_CR_WAITEN from a register value.
+#define BG_EPIT_CR_WAITEN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_WAITEN) >> BP_EPIT_CR_WAITEN)
+
+//! @brief Format value for bitfield EPIT_CR_WAITEN.
+#define BF_EPIT_CR_WAITEN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_WAITEN) & BM_EPIT_CR_WAITEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the WAITEN field to a new value.
+#define BW_EPIT_CR_WAITEN(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_WAITEN) | BF_EPIT_CR_WAITEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field STOPEN[21] (RW)
+ *
+ * EPIT stop mode enable. This read/write control bit enables the operation of the EPIT during stop
+ * mode. This bit is reset by a hardware reset and unaffected by software reset.
+ *
+ * Values:
+ * - 0 - EPIT is disabled in stop mode
+ * - 1 - EPIT is enabled in stop mode
+ */
+//@{
+#define BP_EPIT_CR_STOPEN      (21)      //!< Bit position for EPIT_CR_STOPEN.
+#define BM_EPIT_CR_STOPEN      (0x00200000)  //!< Bit mask for EPIT_CR_STOPEN.
+
+//! @brief Get value of EPIT_CR_STOPEN from a register value.
+#define BG_EPIT_CR_STOPEN(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_STOPEN) >> BP_EPIT_CR_STOPEN)
+
+//! @brief Format value for bitfield EPIT_CR_STOPEN.
+#define BF_EPIT_CR_STOPEN(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_STOPEN) & BM_EPIT_CR_STOPEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the STOPEN field to a new value.
+#define BW_EPIT_CR_STOPEN(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_STOPEN) | BF_EPIT_CR_STOPEN(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field OM[23:22] (RW)
+ *
+ * EPIT output mode.This bit field determines the mode of EPIT output on the output pin.
+ *
+ * Values:
+ * - 00 - EPIT output is disconnected from pad
+ * - 01 - Toggle output pin
+ * - 10 - Clear output pin
+ * - 11 - Set output pin
+ */
+//@{
+#define BP_EPIT_CR_OM      (22)      //!< Bit position for EPIT_CR_OM.
+#define BM_EPIT_CR_OM      (0x00c00000)  //!< Bit mask for EPIT_CR_OM.
+
+//! @brief Get value of EPIT_CR_OM from a register value.
+#define BG_EPIT_CR_OM(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_OM) >> BP_EPIT_CR_OM)
+
+//! @brief Format value for bitfield EPIT_CR_OM.
+#define BF_EPIT_CR_OM(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_OM) & BM_EPIT_CR_OM)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OM field to a new value.
+#define BW_EPIT_CR_OM(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_OM) | BF_EPIT_CR_OM(v)))
+#endif
+//@}
+
+/*! @name Register EPIT_CR, field CLKSRC[25:24] (RW)
+ *
+ * Select clock source These bits determine which clock input is to be selected for running the
+ * counter. This field value should only be changed when the EPIT is disabled by clearing the EN bit
+ * in this register. For other programming requirements while changing clock source, refer to .
+ *
+ * Values:
+ * - 00 - Clock is off
+ * - 01 - Peripheral clock
+ * - 10 - High-frequency reference clock
+ * - 11 - Low-frequency reference clock
+ */
+//@{
+#define BP_EPIT_CR_CLKSRC      (24)      //!< Bit position for EPIT_CR_CLKSRC.
+#define BM_EPIT_CR_CLKSRC      (0x03000000)  //!< Bit mask for EPIT_CR_CLKSRC.
+
+//! @brief Get value of EPIT_CR_CLKSRC from a register value.
+#define BG_EPIT_CR_CLKSRC(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CR_CLKSRC) >> BP_EPIT_CR_CLKSRC)
+
+//! @brief Format value for bitfield EPIT_CR_CLKSRC.
+#define BF_EPIT_CR_CLKSRC(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CR_CLKSRC) & BM_EPIT_CR_CLKSRC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the CLKSRC field to a new value.
+#define BW_EPIT_CR_CLKSRC(x, v)   (HW_EPIT_CR_WR(x, (HW_EPIT_CR_RD(x) & ~BM_EPIT_CR_CLKSRC) | BF_EPIT_CR_CLKSRC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_SR - Status register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_SR - Status register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT status register (EPIT_SR) has a single status bit for the output compare event. The bit
+ * is a write 1 to clear bit.
+ */
+typedef union _hw_epit_sr
+{
+    reg32_t U;
+    struct _hw_epit_sr_bitfields
+    {
+        unsigned OCIF : 1; //!< [0] Output compare interrupt flag.
+        unsigned RESERVED0 : 31; //!< [31:1] Reserved.
+    } B;
+} hw_epit_sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_SR register
+ */
+//@{
+#define HW_EPIT_SR_ADDR(x)      (REGS_EPIT_BASE(x) + 0x4)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_SR(x)           (*(volatile hw_epit_sr_t *) HW_EPIT_SR_ADDR(x))
+#define HW_EPIT_SR_RD(x)        (HW_EPIT_SR(x).U)
+#define HW_EPIT_SR_WR(x, v)     (HW_EPIT_SR(x).U = (v))
+#define HW_EPIT_SR_SET(x, v)    (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) |  (v)))
+#define HW_EPIT_SR_CLR(x, v)    (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) & ~(v)))
+#define HW_EPIT_SR_TOG(x, v)    (HW_EPIT_SR_WR(x, HW_EPIT_SR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_SR bitfields
+ */
+
+/*! @name Register EPIT_SR, field OCIF[0] (W1C)
+ *
+ * Output compare interrupt flag. This bit is the interrupt flag that is set when the content of
+ * counter equals the content of the compare register (EPIT_CMPR). The bit is a write 1 to clear
+ * bit.
+ *
+ * Values:
+ * - 0 - Compare event has not occurred
+ * - 1 - Compare event occurred
+ */
+//@{
+#define BP_EPIT_SR_OCIF      (0)      //!< Bit position for EPIT_SR_OCIF.
+#define BM_EPIT_SR_OCIF      (0x00000001)  //!< Bit mask for EPIT_SR_OCIF.
+
+//! @brief Get value of EPIT_SR_OCIF from a register value.
+#define BG_EPIT_SR_OCIF(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_SR_OCIF) >> BP_EPIT_SR_OCIF)
+
+//! @brief Format value for bitfield EPIT_SR_OCIF.
+#define BF_EPIT_SR_OCIF(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_SR_OCIF) & BM_EPIT_SR_OCIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the OCIF field to a new value.
+#define BW_EPIT_SR_OCIF(x, v)   (HW_EPIT_SR_WR(x, (HW_EPIT_SR_RD(x) & ~BM_EPIT_SR_OCIF) | BF_EPIT_SR_OCIF(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_LR - Load register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_LR - Load register (RW)
+ *
+ * Reset value: 0xffffffff
+ *
+ * The EPIT load register (EPIT_LR) contains the value that is to be loaded into the counter when
+ * EPIT counter reaches zero if the RLD bit in EPIT_CR is set. If the IOVW bit in the EPIT_CR is set
+ * then a write to this register overwrites the value of the EPIT counter register in addition to
+ * updating this registers value. This overwrite feature is active even if the RLD bit is not set.
+ */
+typedef union _hw_epit_lr
+{
+    reg32_t U;
+    struct _hw_epit_lr_bitfields
+    {
+        unsigned LOAD : 32; //!< [31:0] Load value.
+    } B;
+} hw_epit_lr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_LR register
+ */
+//@{
+#define HW_EPIT_LR_ADDR(x)      (REGS_EPIT_BASE(x) + 0x8)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_LR(x)           (*(volatile hw_epit_lr_t *) HW_EPIT_LR_ADDR(x))
+#define HW_EPIT_LR_RD(x)        (HW_EPIT_LR(x).U)
+#define HW_EPIT_LR_WR(x, v)     (HW_EPIT_LR(x).U = (v))
+#define HW_EPIT_LR_SET(x, v)    (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) |  (v)))
+#define HW_EPIT_LR_CLR(x, v)    (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) & ~(v)))
+#define HW_EPIT_LR_TOG(x, v)    (HW_EPIT_LR_WR(x, HW_EPIT_LR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_LR bitfields
+ */
+
+/*! @name Register EPIT_LR, field LOAD[31:0] (RW)
+ *
+ * Load value. Value that is loaded into the counter at the start of each count cycle.
+ */
+//@{
+#define BP_EPIT_LR_LOAD      (0)      //!< Bit position for EPIT_LR_LOAD.
+#define BM_EPIT_LR_LOAD      (0xffffffff)  //!< Bit mask for EPIT_LR_LOAD.
+
+//! @brief Get value of EPIT_LR_LOAD from a register value.
+#define BG_EPIT_LR_LOAD(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_LR_LOAD) >> BP_EPIT_LR_LOAD)
+
+//! @brief Format value for bitfield EPIT_LR_LOAD.
+#define BF_EPIT_LR_LOAD(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_LR_LOAD) & BM_EPIT_LR_LOAD)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the LOAD field to a new value.
+#define BW_EPIT_LR_LOAD(x, v)   (HW_EPIT_LR_WR(x, (HW_EPIT_LR_RD(x) & ~BM_EPIT_LR_LOAD) | BF_EPIT_LR_LOAD(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CMPR - Compare register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CMPR - Compare register (RW)
+ *
+ * Reset value: 0x00000000
+ *
+ * The EPIT compare register (EPIT_CMPR) holds the value that determines when a compare event is
+ * generated.
+ */
+typedef union _hw_epit_cmpr
+{
+    reg32_t U;
+    struct _hw_epit_cmpr_bitfields
+    {
+        unsigned COMPARE : 32; //!< [31:0] Compare Value.
+    } B;
+} hw_epit_cmpr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CMPR register
+ */
+//@{
+#define HW_EPIT_CMPR_ADDR(x)      (REGS_EPIT_BASE(x) + 0xc)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CMPR(x)           (*(volatile hw_epit_cmpr_t *) HW_EPIT_CMPR_ADDR(x))
+#define HW_EPIT_CMPR_RD(x)        (HW_EPIT_CMPR(x).U)
+#define HW_EPIT_CMPR_WR(x, v)     (HW_EPIT_CMPR(x).U = (v))
+#define HW_EPIT_CMPR_SET(x, v)    (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) |  (v)))
+#define HW_EPIT_CMPR_CLR(x, v)    (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) & ~(v)))
+#define HW_EPIT_CMPR_TOG(x, v)    (HW_EPIT_CMPR_WR(x, HW_EPIT_CMPR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CMPR bitfields
+ */
+
+/*! @name Register EPIT_CMPR, field COMPARE[31:0] (RW)
+ *
+ * Compare Value. When the counter value equals this bit field value a compare event is generated.
+ */
+//@{
+#define BP_EPIT_CMPR_COMPARE      (0)      //!< Bit position for EPIT_CMPR_COMPARE.
+#define BM_EPIT_CMPR_COMPARE      (0xffffffff)  //!< Bit mask for EPIT_CMPR_COMPARE.
+
+//! @brief Get value of EPIT_CMPR_COMPARE from a register value.
+#define BG_EPIT_CMPR_COMPARE(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CMPR_COMPARE) >> BP_EPIT_CMPR_COMPARE)
+
+//! @brief Format value for bitfield EPIT_CMPR_COMPARE.
+#define BF_EPIT_CMPR_COMPARE(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_EPIT_CMPR_COMPARE) & BM_EPIT_CMPR_COMPARE)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the COMPARE field to a new value.
+#define BW_EPIT_CMPR_COMPARE(x, v)   (HW_EPIT_CMPR_WR(x, (HW_EPIT_CMPR_RD(x) & ~BM_EPIT_CMPR_COMPARE) | BF_EPIT_CMPR_COMPARE(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_EPIT_CNR - Counter register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_EPIT_CNR - Counter register (RO)
+ *
+ * Reset value: 0xffffffff
+ *
+ * The EPIT counter register (EPIT_CNR) contains the current count value and can be read at any time
+ * without disturbing the counter. This is a read-only register and any attempt to write into it
+ * generates a transfer error. But if the IOVW bit in EPIT_CR is set, the value of this register can
+ * be overwritten with a write to EPIT_LR. This change is reflected when this register is
+ * subsequently read.
+ */
+typedef union _hw_epit_cnr
+{
+    reg32_t U;
+    struct _hw_epit_cnr_bitfields
+    {
+        unsigned COUNT : 32; //!< [31:0] Counter value.
+    } B;
+} hw_epit_cnr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire EPIT_CNR register
+ */
+//@{
+#define HW_EPIT_CNR_ADDR(x)      (REGS_EPIT_BASE(x) + 0x10)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_EPIT_CNR(x)           (*(volatile hw_epit_cnr_t *) HW_EPIT_CNR_ADDR(x))
+#define HW_EPIT_CNR_RD(x)        (HW_EPIT_CNR(x).U)
+#endif
+//@}
+
+/*
+ * constants & macros for individual EPIT_CNR bitfields
+ */
+
+/*! @name Register EPIT_CNR, field COUNT[31:0] (RO)
+ *
+ * Counter value. This contains the current value of the counter.
+ */
+//@{
+#define BP_EPIT_CNR_COUNT      (0)      //!< Bit position for EPIT_CNR_COUNT.
+#define BM_EPIT_CNR_COUNT      (0xffffffff)  //!< Bit mask for EPIT_CNR_COUNT.
+
+//! @brief Get value of EPIT_CNR_COUNT from a register value.
+#define BG_EPIT_CNR_COUNT(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_EPIT_CNR_COUNT) >> BP_EPIT_CNR_COUNT)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_epit_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All EPIT module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_epit
+{
+    volatile hw_epit_cr_t CR; //!< Control register
+    volatile hw_epit_sr_t SR; //!< Status register
+    volatile hw_epit_lr_t LR; //!< Load register
+    volatile hw_epit_cmpr_t CMPR; //!< Compare register
+    volatile hw_epit_cnr_t CNR; //!< Counter register
+} hw_epit_t;
+#pragma pack()
+
+//! @brief Macro to access all EPIT registers.
+//! @param x EPIT instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_EPIT(0)</code>.
+#define HW_EPIT(x)     (*(hw_epit_t *) REGS_EPIT_BASE(x))
+#endif
+
+#endif // __HW_EPIT_REGISTERS_H__
+// v18/121106/1.2.2
+// EOF

bsp/imx6ul/platform/include/mx6ul/registers/regsi2c.h

@@ -0,0 +1,707 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_I2C_REGISTERS_H__
+#define __HW_I2C_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * i.MX6SDL I2C
+ *
+ * I2C
+ *
+ * Registers defined in this header file:
+ * - HW_I2C_IADR - I2C Address Register
+ * - HW_I2C_IFDR - I2C Frequency Divider Register
+ * - HW_I2C_I2CR - I2C Control Register
+ * - HW_I2C_I2SR - I2C Status Register
+ * - HW_I2C_I2DR - I2C Data I/O Register
+ *
+ * - hw_i2c_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_I2C_BASE
+#define HW_I2C_INSTANCE_COUNT (4) //!< Number of instances of the I2C module.
+#define HW_I2C1 (1) //!< Instance number for I2C1.
+#define HW_I2C2 (2) //!< Instance number for I2C2.
+#define HW_I2C3 (3) //!< Instance number for I2C3.
+#define HW_I2C4 (4) //!< Instance number for I2C4.
+#define REGS_I2C1_BASE (0x021a0000) //!< Base address for I2C instance number 1.
+#define REGS_I2C2_BASE (0x021a4000) //!< Base address for I2C instance number 2.
+#define REGS_I2C3_BASE (0x021a8000) //!< Base address for I2C instance number 3.
+#define REGS_I2C4_BASE (0x021f8000) //!< Base address for I2C instance number 4.
+
+//! @brief Get the base address of I2C by instance number.
+//! @param x I2C instance number, from 1 through 4.
+#define REGS_I2C_BASE(x) ( (x) == HW_I2C1 ? REGS_I2C1_BASE : (x) == HW_I2C2 ? REGS_I2C2_BASE : (x) == HW_I2C3 ? REGS_I2C3_BASE : (x) == HW_I2C4 ? REGS_I2C4_BASE : 0x00d00000)
+
+//! @brief Get the instance number given a base address.
+//! @param b Base address for an instance of I2C.
+#define REGS_I2C_INSTANCE(b) ( (b) == REGS_I2C1_BASE ? HW_I2C1 : (b) == REGS_I2C2_BASE ? HW_I2C2 : (b) == REGS_I2C3_BASE ? HW_I2C3 : (b) == REGS_I2C4_BASE ? HW_I2C4 : 0)
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_IADR - I2C Address Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_IADR - I2C Address Register (RW)
+ *
+ * Reset value: 0x0000
+ */
+typedef union _hw_i2c_iadr
+{
+    reg16_t U;
+    struct _hw_i2c_iadr_bitfields
+    {
+        unsigned short RESERVED0 : 1; //!< [0] Reserved
+        unsigned short ADR : 7; //!< [7:1] Slave address.
+        unsigned short RESERVED1 : 8; //!< [15:8] Reserved
+    } B;
+} hw_i2c_iadr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_IADR register
+ */
+//@{
+#define HW_I2C_IADR_ADDR(x)      (REGS_I2C_BASE(x) + 0x0)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_IADR(x)           (*(volatile hw_i2c_iadr_t *) HW_I2C_IADR_ADDR(x))
+#define HW_I2C_IADR_RD(x)        (HW_I2C_IADR(x).U)
+#define HW_I2C_IADR_WR(x, v)     (HW_I2C_IADR(x).U = (v))
+#define HW_I2C_IADR_SET(x, v)    (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) |  (v)))
+#define HW_I2C_IADR_CLR(x, v)    (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) & ~(v)))
+#define HW_I2C_IADR_TOG(x, v)    (HW_I2C_IADR_WR(x, HW_I2C_IADR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual I2C_IADR bitfields
+ */
+
+/*! @name Register I2C_IADR, field ADR[7:1] (RW)
+ *
+ * Slave address. Contains the specific slave address to be used by the I2C. Slave mode is the
+ * default I2C mode for an address match on the bus. The I2C_IADR holds the address the I2C responds
+ * to when addressed as a slave. The slave address is not the address sent on the bus during the
+ * address transfer. The register is not reset by a software reset.
+ */
+//@{
+#define BP_I2C_IADR_ADR      (1)      //!< Bit position for I2C_IADR_ADR.
+#define BM_I2C_IADR_ADR      (0x000000fe)  //!< Bit mask for I2C_IADR_ADR.
+
+//! @brief Get value of I2C_IADR_ADR from a register value.
+#define BG_I2C_IADR_ADR(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IADR_ADR) >> BP_I2C_IADR_ADR)
+
+//! @brief Format value for bitfield I2C_IADR_ADR.
+#define BF_I2C_IADR_ADR(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IADR_ADR) & BM_I2C_IADR_ADR)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the ADR field to a new value.
+#define BW_I2C_IADR_ADR(x, v)   (HW_I2C_IADR_WR(x, (HW_I2C_IADR_RD(x) & ~BM_I2C_IADR_ADR) | BF_I2C_IADR_ADR(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_IFDR - I2C Frequency Divider Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_IFDR - I2C Frequency Divider Register (RW)
+ *
+ * Reset value: 0x0000
+ *
+ * The I2C_IFDR provides a programmable prescaler to configure the clock for bit-rate selection. The
+ * register does not get reset by software reset. The following table describes the Divider values
+ * for register field "IC". Table below describes the register values for field "IC". I2C_IFDR
+ * Register Field Values IC Divider IC Divider IC Divider IC Divider 0x00 30 0x10 288 0x20 22 0x30
+ * 160 0x01 32 0x11 320 0x21 24 0x31 192 0x02 36 0x12 384 0x22 26 0x32 224 0x03 42 0x13 480 0x23 28
+ * 0x33 256 0x04 48 0x14 576 0x24 32 0x34 320 0x05 52 0x15 640 0x25 36 0x35 384 0x06 60 0x16 768
+ * 0x26 40 0x36 448 0x07 72 0x17 960 0x27 44 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88
+ * 0x19 1280 0x29 56 0x39 768 0x0A 104 0x1A 1536 0x2A 64 0x3A 896 0x0B 128 0x1B 1920 0x2B 72 0x3B
+ * 1024 0x0C 144 0x1C 2304 0x2C 80 0x3C 1280 0x0D 160 0x1D 2560 0x2D 96 0x3D 1536 0x0E 192 0x1E 3072
+ * 0x2E 112 0x3E 1792 0x0F 240 0x1F 3840 0x2F 128 0x3F 2048
+ */
+typedef union _hw_i2c_ifdr
+{
+    reg16_t U;
+    struct _hw_i2c_ifdr_bitfields
+    {
+        unsigned short IC : 6; //!< [5:0] I2C clock rate.
+        unsigned short RESERVED0 : 10; //!< [15:6] Reserved
+    } B;
+} hw_i2c_ifdr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_IFDR register
+ */
+//@{
+#define HW_I2C_IFDR_ADDR(x)      (REGS_I2C_BASE(x) + 0x4)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_IFDR(x)           (*(volatile hw_i2c_ifdr_t *) HW_I2C_IFDR_ADDR(x))
+#define HW_I2C_IFDR_RD(x)        (HW_I2C_IFDR(x).U)
+#define HW_I2C_IFDR_WR(x, v)     (HW_I2C_IFDR(x).U = (v))
+#define HW_I2C_IFDR_SET(x, v)    (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) |  (v)))
+#define HW_I2C_IFDR_CLR(x, v)    (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) & ~(v)))
+#define HW_I2C_IFDR_TOG(x, v)    (HW_I2C_IFDR_WR(x, HW_I2C_IFDR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual I2C_IFDR bitfields
+ */
+
+/*! @name Register I2C_IFDR, field IC[5:0] (RW)
+ *
+ * I2C clock rate. Pre-scales the clock for bit-rate selection. Due to potentially slow I2Cn_SCL and
+ * I2Cn_SDA rise and fall times, bus signals are sampled at the prescaler frequency. The serial bit
+ * clock frequency may be lower than IPG_CLK_ROOT divided by the divider shown in the I2C Data I/O
+ * Register. The IC value should not be changed during the data transfer, however, it can be changed
+ * before REPEAT START or START programming sequence in I2C. The I2C protocol supports bit rates up
+ * to 400 kbps. The IC bits need to be programmed in accordance with this constraint.
+ */
+//@{
+#define BP_I2C_IFDR_IC      (0)      //!< Bit position for I2C_IFDR_IC.
+#define BM_I2C_IFDR_IC      (0x0000003f)  //!< Bit mask for I2C_IFDR_IC.
+
+//! @brief Get value of I2C_IFDR_IC from a register value.
+#define BG_I2C_IFDR_IC(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_IFDR_IC) >> BP_I2C_IFDR_IC)
+
+//! @brief Format value for bitfield I2C_IFDR_IC.
+#define BF_I2C_IFDR_IC(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_IFDR_IC) & BM_I2C_IFDR_IC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IC field to a new value.
+#define BW_I2C_IFDR_IC(x, v)   (HW_I2C_IFDR_WR(x, (HW_I2C_IFDR_RD(x) & ~BM_I2C_IFDR_IC) | BF_I2C_IFDR_IC(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_I2CR - I2C Control Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_I2CR - I2C Control Register (RW)
+ *
+ * Reset value: 0x0000
+ *
+ * The I2C_I2CR is used to enable the I2C and the I2C interrupt. It also contains bits that govern
+ * operation as a slave or a master.
+ */
+typedef union _hw_i2c_i2cr
+{
+    reg16_t U;
+    struct _hw_i2c_i2cr_bitfields
+    {
+        unsigned short RESERVED0 : 2; //!< [1:0] Reserved
+        unsigned short RSTA : 1; //!< [2] Repeat start.
+        unsigned short TXAK : 1; //!< [3] Transmit acknowledge enable.
+        unsigned short MTX : 1; //!< [4] Transmit/receive mode select bit.
+        unsigned short MSTA : 1; //!< [5] Master/slave mode select bit.
+        unsigned short IIEN : 1; //!< [6] I2C interrupt enable.
+        unsigned short IEN : 1; //!< [7] I2C enable.
+        unsigned short RESERVED1 : 8; //!< [15:8] Reserved
+    } B;
+} hw_i2c_i2cr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_I2CR register
+ */
+//@{
+#define HW_I2C_I2CR_ADDR(x)      (REGS_I2C_BASE(x) + 0x8)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_I2CR(x)           (*(volatile hw_i2c_i2cr_t *) HW_I2C_I2CR_ADDR(x))
+#define HW_I2C_I2CR_RD(x)        (HW_I2C_I2CR(x).U)
+#define HW_I2C_I2CR_WR(x, v)     (HW_I2C_I2CR(x).U = (v))
+#define HW_I2C_I2CR_SET(x, v)    (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) |  (v)))
+#define HW_I2C_I2CR_CLR(x, v)    (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) & ~(v)))
+#define HW_I2C_I2CR_TOG(x, v)    (HW_I2C_I2CR_WR(x, HW_I2C_I2CR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual I2C_I2CR bitfields
+ */
+
+/*! @name Register I2C_I2CR, field RSTA[2] (WORZ)
+ *
+ * Repeat start. Always reads as 0. Attempting a repeat start without bus mastership causes loss of
+ * arbitration.
+ *
+ * Values:
+ * - 0 - No repeat start
+ * - 1 - Generates a repeated START condition
+ */
+//@{
+#define BP_I2C_I2CR_RSTA      (2)      //!< Bit position for I2C_I2CR_RSTA.
+#define BM_I2C_I2CR_RSTA      (0x00000004)  //!< Bit mask for I2C_I2CR_RSTA.
+
+//! @brief Get value of I2C_I2CR_RSTA from a register value.
+#define BG_I2C_I2CR_RSTA(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_RSTA) >> BP_I2C_I2CR_RSTA)
+
+//! @brief Format value for bitfield I2C_I2CR_RSTA.
+#define BF_I2C_I2CR_RSTA(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_RSTA) & BM_I2C_I2CR_RSTA)
+//@}
+
+/*! @name Register I2C_I2CR, field TXAK[3] (RW)
+ *
+ * Transmit acknowledge enable. Specifies the value driven onto I2Cn_SDA during acknowledge cycles
+ * for both master and slave receivers. Writing TXAK applies only when the I2C bus is a receiver.
+ *
+ * Values:
+ * - 0 - An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
+ * - 1 - No acknowledge signal response is sent (that is, the acknowledge bit = 1).
+ */
+//@{
+#define BP_I2C_I2CR_TXAK      (3)      //!< Bit position for I2C_I2CR_TXAK.
+#define BM_I2C_I2CR_TXAK      (0x00000008)  //!< Bit mask for I2C_I2CR_TXAK.
+
+//! @brief Get value of I2C_I2CR_TXAK from a register value.
+#define BG_I2C_I2CR_TXAK(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_TXAK) >> BP_I2C_I2CR_TXAK)
+
+//! @brief Format value for bitfield I2C_I2CR_TXAK.
+#define BF_I2C_I2CR_TXAK(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_TXAK) & BM_I2C_I2CR_TXAK)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the TXAK field to a new value.
+#define BW_I2C_I2CR_TXAK(x, v)   (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_TXAK) | BF_I2C_I2CR_TXAK(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2CR, field MTX[4] (RW)
+ *
+ * Transmit/receive mode select bit. Selects the direction of master and slave transfers.
+ *
+ * Values:
+ * - 0 - Receive. When a slave is addressed, the software should set MTX according to the slave read/write
+ *     bit in the I2C status register (I2C_I2SR[SRW]).
+ * - 1 - Transmit. In master mode, MTX should be set according to the type of transfer required. Therefore,
+ *     for address cycles, MTX is always 1.
+ */
+//@{
+#define BP_I2C_I2CR_MTX      (4)      //!< Bit position for I2C_I2CR_MTX.
+#define BM_I2C_I2CR_MTX      (0x00000010)  //!< Bit mask for I2C_I2CR_MTX.
+
+//! @brief Get value of I2C_I2CR_MTX from a register value.
+#define BG_I2C_I2CR_MTX(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MTX) >> BP_I2C_I2CR_MTX)
+
+//! @brief Format value for bitfield I2C_I2CR_MTX.
+#define BF_I2C_I2CR_MTX(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MTX) & BM_I2C_I2CR_MTX)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MTX field to a new value.
+#define BW_I2C_I2CR_MTX(x, v)   (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MTX) | BF_I2C_I2CR_MTX(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2CR, field MSTA[5] (RW)
+ *
+ * Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating
+ * a STOP signal. Module clock should be on for writing to the MSTA bit. The MSTA bit is cleared by
+ * software to generate a STOP condition; it can also be cleared by hardware when the I2C loses the
+ * bus arbitration.
+ *
+ * Values:
+ * - 0 - Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
+ * - 1 - Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
+ */
+//@{
+#define BP_I2C_I2CR_MSTA      (5)      //!< Bit position for I2C_I2CR_MSTA.
+#define BM_I2C_I2CR_MSTA      (0x00000020)  //!< Bit mask for I2C_I2CR_MSTA.
+
+//! @brief Get value of I2C_I2CR_MSTA from a register value.
+#define BG_I2C_I2CR_MSTA(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_MSTA) >> BP_I2C_I2CR_MSTA)
+
+//! @brief Format value for bitfield I2C_I2CR_MSTA.
+#define BF_I2C_I2CR_MSTA(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_MSTA) & BM_I2C_I2CR_MSTA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the MSTA field to a new value.
+#define BW_I2C_I2CR_MSTA(x, v)   (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_MSTA) | BF_I2C_I2CR_MSTA(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2CR, field IIEN[6] (RW)
+ *
+ * I2C interrupt enable. If data is written during the START condition, that is, just after setting
+ * the I2C_I2CR[MSTA] and I2C_I2CR[MTX] bits, then the ICF bit is cleared at the falling edge of
+ * SCLK after START. If data is written after the START condition and falling edge of SCLK, then ICF
+ * bit is cleared as soon as data is written.
+ *
+ * Values:
+ * - 0 - I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an interrupt
+ *     condition occurs.
+ * - 1 - I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
+ */
+//@{
+#define BP_I2C_I2CR_IIEN      (6)      //!< Bit position for I2C_I2CR_IIEN.
+#define BM_I2C_I2CR_IIEN      (0x00000040)  //!< Bit mask for I2C_I2CR_IIEN.
+
+//! @brief Get value of I2C_I2CR_IIEN from a register value.
+#define BG_I2C_I2CR_IIEN(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IIEN) >> BP_I2C_I2CR_IIEN)
+
+//! @brief Format value for bitfield I2C_I2CR_IIEN.
+#define BF_I2C_I2CR_IIEN(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IIEN) & BM_I2C_I2CR_IIEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IIEN field to a new value.
+#define BW_I2C_I2CR_IIEN(x, v)   (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IIEN) | BF_I2C_I2CR_IIEN(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2CR, field IEN[7] (RW)
+ *
+ * I2C enable. Also controls the software reset of the entire I2C. Resetting the bit generates an
+ * internal reset to the block. If the block is enabled in the middle of a byte transfer, slave mode
+ * ignores the current bus transfer and starts operating when the next start condition is detected.
+ * Master mode is not aware that the bus is busy so initiating a start cycle may corrupt the current
+ * bus cycle, ultimately causing either the current master or the I2C to lose arbitration. After
+ * which, bus operation returns to normal.
+ *
+ * Values:
+ * - 0 - The block is disabled, but registers can still be accessed.
+ * - 1 - The I2C is enabled. This bit must be set before any other I2C_I2CR bits have any effect.
+ */
+//@{
+#define BP_I2C_I2CR_IEN      (7)      //!< Bit position for I2C_I2CR_IEN.
+#define BM_I2C_I2CR_IEN      (0x00000080)  //!< Bit mask for I2C_I2CR_IEN.
+
+//! @brief Get value of I2C_I2CR_IEN from a register value.
+#define BG_I2C_I2CR_IEN(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2CR_IEN) >> BP_I2C_I2CR_IEN)
+
+//! @brief Format value for bitfield I2C_I2CR_IEN.
+#define BF_I2C_I2CR_IEN(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2CR_IEN) & BM_I2C_I2CR_IEN)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IEN field to a new value.
+#define BW_I2C_I2CR_IEN(x, v)   (HW_I2C_I2CR_WR(x, (HW_I2C_I2CR_RD(x) & ~BM_I2C_I2CR_IEN) | BF_I2C_I2CR_IEN(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_I2SR - I2C Status Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_I2SR - I2C Status Register (RW)
+ *
+ * Reset value: 0x0081
+ *
+ * The I2C_I2SR contains bits that indicate transaction direction and status.
+ */
+typedef union _hw_i2c_i2sr
+{
+    reg16_t U;
+    struct _hw_i2c_i2sr_bitfields
+    {
+        unsigned short RXAK : 1; //!< [0] Received acknowledge.
+        unsigned short IIF : 1; //!< [1] I2C interrupt.
+        unsigned short SRW : 1; //!< [2] Slave read/write.
+        unsigned short RESERVED0 : 1; //!< [3] Reserved
+        unsigned short IAL : 1; //!< [4] Arbitration lost.
+        unsigned short IBB : 1; //!< [5] I2C bus busy bit.
+        unsigned short IAAS : 1; //!< [6] I2C addressed as a slave bit.
+        unsigned short ICF : 1; //!< [7] Data transferring bit.
+        unsigned short RESERVED1 : 8; //!< [15:8] Reserved
+    } B;
+} hw_i2c_i2sr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_I2SR register
+ */
+//@{
+#define HW_I2C_I2SR_ADDR(x)      (REGS_I2C_BASE(x) + 0xc)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_I2SR(x)           (*(volatile hw_i2c_i2sr_t *) HW_I2C_I2SR_ADDR(x))
+#define HW_I2C_I2SR_RD(x)        (HW_I2C_I2SR(x).U)
+#define HW_I2C_I2SR_WR(x, v)     (HW_I2C_I2SR(x).U = (v))
+#define HW_I2C_I2SR_SET(x, v)    (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) |  (v)))
+#define HW_I2C_I2SR_CLR(x, v)    (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) & ~(v)))
+#define HW_I2C_I2SR_TOG(x, v)    (HW_I2C_I2SR_WR(x, HW_I2C_I2SR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual I2C_I2SR bitfields
+ */
+
+/*! @name Register I2C_I2SR, field RXAK[0] (RO)
+ *
+ * Received acknowledge. This is the value received of the I2Cn_SDA input for the acknowledge bit
+ * during a bus cycle.
+ *
+ * Values:
+ * - 0 - An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
+ * - 1 - A "No acknowledge" signal was detected at the ninth clock.
+ */
+//@{
+#define BP_I2C_I2SR_RXAK      (0)      //!< Bit position for I2C_I2SR_RXAK.
+#define BM_I2C_I2SR_RXAK      (0x00000001)  //!< Bit mask for I2C_I2SR_RXAK.
+
+//! @brief Get value of I2C_I2SR_RXAK from a register value.
+#define BG_I2C_I2SR_RXAK(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_RXAK) >> BP_I2C_I2SR_RXAK)
+//@}
+
+/*! @name Register I2C_I2SR, field IIF[1] (RW)
+ *
+ * I2C interrupt. Must be cleared by the software by writing a "0" to it in the interrupt routine.
+ * The software cannot set the bit.
+ *
+ * Values:
+ * - 0 - No I2C interrupt pending.
+ * - 1 - An interrupt is pending. This causes a processor interrupt request (if the interrupt enable is
+ *     asserted [IIEN = 1]). The interrupt is set when one of the following occurs:  One byte
+ *     transfer is completed (the interrupt is set at the falling edge of the ninth clock).  An
+ *     address is received that matches its own specific address in slave-receive mode.  Arbitration
+ *     is lost.
+ */
+//@{
+#define BP_I2C_I2SR_IIF      (1)      //!< Bit position for I2C_I2SR_IIF.
+#define BM_I2C_I2SR_IIF      (0x00000002)  //!< Bit mask for I2C_I2SR_IIF.
+
+//! @brief Get value of I2C_I2SR_IIF from a register value.
+#define BG_I2C_I2SR_IIF(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IIF) >> BP_I2C_I2SR_IIF)
+
+//! @brief Format value for bitfield I2C_I2SR_IIF.
+#define BF_I2C_I2SR_IIF(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IIF) & BM_I2C_I2SR_IIF)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IIF field to a new value.
+#define BW_I2C_I2SR_IIF(x, v)   (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IIF) | BF_I2C_I2SR_IIF(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2SR, field SRW[2] (RO)
+ *
+ * Slave read/write. When the I2C is addressed as a slave, IAAS is set, and the slave read/write bit
+ * (SRW) indicates the value of the R/W command bit of the calling address sent from the master. SRW
+ * is valid only when a complete transfer has occurred, no other transfers have been initiated, and
+ * the I2C is a slave and has an address match.
+ *
+ * Values:
+ * - 0 - Slave receive, master writing to slave
+ * - 1 - Slave transmit, master reading from slave
+ */
+//@{
+#define BP_I2C_I2SR_SRW      (2)      //!< Bit position for I2C_I2SR_SRW.
+#define BM_I2C_I2SR_SRW      (0x00000004)  //!< Bit mask for I2C_I2SR_SRW.
+
+//! @brief Get value of I2C_I2SR_SRW from a register value.
+#define BG_I2C_I2SR_SRW(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_SRW) >> BP_I2C_I2SR_SRW)
+//@}
+
+/*! @name Register I2C_I2SR, field IAL[4] (RW)
+ *
+ * Arbitration lost. Set by hardware in the following circumstances (IAL must be cleared by software
+ * by writing a "0" to it at the start of the interrupt service routine): I2Cn_SDA input sampled low
+ * when the master drives high during an address or data-transmit cycle. I2Cn_SDA input sampled low
+ * when the master drives high during the acknowledge bit of a data-receive cycle. For the above two
+ * cases, the bit is set at the falling edge of 9th I2Cn_SCL clock during the ACK cycle. A start
+ * cycle is attempted when the bus is busy. A repeated start cycle is requested in slave mode. A
+ * stop condition is detected when the master did not request it. Software cannot set the bit.
+ *
+ * Values:
+ * - 0 - No arbitration lost.
+ * - 1 - Arbitration is lost.
+ */
+//@{
+#define BP_I2C_I2SR_IAL      (4)      //!< Bit position for I2C_I2SR_IAL.
+#define BM_I2C_I2SR_IAL      (0x00000010)  //!< Bit mask for I2C_I2SR_IAL.
+
+//! @brief Get value of I2C_I2SR_IAL from a register value.
+#define BG_I2C_I2SR_IAL(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAL) >> BP_I2C_I2SR_IAL)
+
+//! @brief Format value for bitfield I2C_I2SR_IAL.
+#define BF_I2C_I2SR_IAL(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2SR_IAL) & BM_I2C_I2SR_IAL)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the IAL field to a new value.
+#define BW_I2C_I2SR_IAL(x, v)   (HW_I2C_I2SR_WR(x, (HW_I2C_I2SR_RD(x) & ~BM_I2C_I2SR_IAL) | BF_I2C_I2SR_IAL(v)))
+#endif
+//@}
+
+/*! @name Register I2C_I2SR, field IBB[5] (RO)
+ *
+ * I2C bus busy bit. Indicates the status of the bus. When I2C is enabled (I2C_I2CR[IEN] = 1), it
+ * continuously polls the bus data (SDAK) and clock (SCLK) signals to determine a START or STOP
+ * condition.
+ *
+ * Values:
+ * - 0 - Bus is idle. If a STOP signal is detected, IBB is cleared.
+ * - 1 - Bus is busy. When START is detected, IBB is set.
+ */
+//@{
+#define BP_I2C_I2SR_IBB      (5)      //!< Bit position for I2C_I2SR_IBB.
+#define BM_I2C_I2SR_IBB      (0x00000020)  //!< Bit mask for I2C_I2SR_IBB.
+
+//! @brief Get value of I2C_I2SR_IBB from a register value.
+#define BG_I2C_I2SR_IBB(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IBB) >> BP_I2C_I2SR_IBB)
+//@}
+
+/*! @name Register I2C_I2SR, field IAAS[6] (RO)
+ *
+ * I2C addressed as a slave bit. The ARM platform is interrupted if the interrupt enable
+ * (I2C_I2CR[IIEN]) is set. The ARM platform must check the slave read/write bit (SRW) and set its
+ * TX/RX mode accordingly. Writing to I2C_I2CR clears this bit.
+ *
+ * Values:
+ * - 0 - Not addressed
+ * - 1 - Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
+ */
+//@{
+#define BP_I2C_I2SR_IAAS      (6)      //!< Bit position for I2C_I2SR_IAAS.
+#define BM_I2C_I2SR_IAAS      (0x00000040)  //!< Bit mask for I2C_I2SR_IAAS.
+
+//! @brief Get value of I2C_I2SR_IAAS from a register value.
+#define BG_I2C_I2SR_IAAS(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_IAAS) >> BP_I2C_I2SR_IAAS)
+//@}
+
+/*! @name Register I2C_I2SR, field ICF[7] (RO)
+ *
+ * Data transferring bit. While one byte of data is transferred, ICF is cleared.
+ *
+ * Values:
+ * - 0 - Transfer is in progress.
+ * - 1 - Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte
+ *     transfer.
+ */
+//@{
+#define BP_I2C_I2SR_ICF      (7)      //!< Bit position for I2C_I2SR_ICF.
+#define BM_I2C_I2SR_ICF      (0x00000080)  //!< Bit mask for I2C_I2SR_ICF.
+
+//! @brief Get value of I2C_I2SR_ICF from a register value.
+#define BG_I2C_I2SR_ICF(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2SR_ICF) >> BP_I2C_I2SR_ICF)
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_I2C_I2DR - I2C Data I/O Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_I2C_I2DR - I2C Data I/O Register (RW)
+ *
+ * Reset value: 0x0000
+ *
+ * In master-receive mode, reading the data register allows a read to occur and initiates the next
+ * byte to be received. In slave mode, the same function is available after it is addressed.
+ */
+typedef union _hw_i2c_i2dr
+{
+    reg16_t U;
+    struct _hw_i2c_i2dr_bitfields
+    {
+        unsigned short DATA : 8; //!< [7:0] Data Byte.
+        unsigned short RESERVED0 : 8; //!< [15:8] Reserved
+    } B;
+} hw_i2c_i2dr_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire I2C_I2DR register
+ */
+//@{
+#define HW_I2C_I2DR_ADDR(x)      (REGS_I2C_BASE(x) + 0x10)
+
+#ifndef __LANGUAGE_ASM__
+#define HW_I2C_I2DR(x)           (*(volatile hw_i2c_i2dr_t *) HW_I2C_I2DR_ADDR(x))
+#define HW_I2C_I2DR_RD(x)        (HW_I2C_I2DR(x).U)
+#define HW_I2C_I2DR_WR(x, v)     (HW_I2C_I2DR(x).U = (v))
+#define HW_I2C_I2DR_SET(x, v)    (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) |  (v)))
+#define HW_I2C_I2DR_CLR(x, v)    (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) & ~(v)))
+#define HW_I2C_I2DR_TOG(x, v)    (HW_I2C_I2DR_WR(x, HW_I2C_I2DR_RD(x) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual I2C_I2DR bitfields
+ */
+
+/*! @name Register I2C_I2DR, field DATA[7:0] (RW)
+ *
+ * Data Byte. Holds the last data byte received or the next data byte to be transferred. Software
+ * writes the next data byte to be transmitted or reads the data byte received. The core-written
+ * value in I2C_I2DR cannot be read back by the core. Only data written by the I2C bus side can be
+ * read.
+ */
+//@{
+#define BP_I2C_I2DR_DATA      (0)      //!< Bit position for I2C_I2DR_DATA.
+#define BM_I2C_I2DR_DATA      (0x000000ff)  //!< Bit mask for I2C_I2DR_DATA.
+
+//! @brief Get value of I2C_I2DR_DATA from a register value.
+#define BG_I2C_I2DR_DATA(r)   ((__REG_VALUE_TYPE((r), reg16_t) & BM_I2C_I2DR_DATA) >> BP_I2C_I2DR_DATA)
+
+//! @brief Format value for bitfield I2C_I2DR_DATA.
+#define BF_I2C_I2DR_DATA(v)   ((__REG_VALUE_TYPE((v), reg16_t) << BP_I2C_I2DR_DATA) & BM_I2C_I2DR_DATA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the DATA field to a new value.
+#define BW_I2C_I2DR_DATA(x, v)   (HW_I2C_I2DR_WR(x, (HW_I2C_I2DR_RD(x) & ~BM_I2C_I2DR_DATA) | BF_I2C_I2DR_DATA(v)))
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_i2c_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All I2C module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_i2c
+{
+    volatile hw_i2c_iadr_t IADR; //!< I2C Address Register
+    reg16_t _reserved0;
+    volatile hw_i2c_ifdr_t IFDR; //!< I2C Frequency Divider Register
+    reg16_t _reserved1;
+    volatile hw_i2c_i2cr_t I2CR; //!< I2C Control Register
+    reg16_t _reserved2;
+    volatile hw_i2c_i2sr_t I2SR; //!< I2C Status Register
+    reg16_t _reserved3;
+    volatile hw_i2c_i2dr_t I2DR; //!< I2C Data I/O Register
+} hw_i2c_t;
+#pragma pack()
+
+//! @brief Macro to access all I2C registers.
+//! @param x I2C instance number.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_I2C(0)</code>.
+#define HW_I2C(x)     (*(hw_i2c_t *) REGS_I2C_BASE(x))
+#endif
+
+#endif // __HW_I2C_REGISTERS_H__
+// v18/121106/1.2.2
+// EOF

bsp/imx6ul/platform/include/mx6ul/registers/regsspba.h

@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ */
+/*
+ * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
+ *
+ * This file was generated automatically and any changes may be lost.
+ */
+#ifndef __HW_SPBA_REGISTERS_H__
+#define __HW_SPBA_REGISTERS_H__
+
+#include "regs.h"
+
+/*
+ * i.MX6UL SPBA
+ *
+ * Temperature Monitor
+ *
+ * Registers defined in this header file:
+ * - HW_SPBA_PRRn - Peripheral Rights Register
+ *
+ * - hw_spba_t - Struct containing all module registers.
+ */
+
+//! @name Module base addresses
+//@{
+#ifndef REGS_SPBA_BASE
+#define HW_SPBA_INSTANCE_COUNT (1) //!< Number of instances of the SPBA module.
+#define REGS_SPBA_BASE (0x0203c000) //!< Base address for SPBA.
+#endif
+//@}
+
+//-------------------------------------------------------------------------------------------
+// HW_SPBA_PRRn - Peripheral Rights Register
+//-------------------------------------------------------------------------------------------
+
+#ifndef __LANGUAGE_ASM__
+/*!
+ * @brief HW_SPBA_PRRn - Peripheral Rights Register (RW)
+ *
+ * Reset value: 0x00000007
+ *
+ * This register controls master ownership and access for a peripheral.
+ */
+typedef union _hw_spba_prrn
+{
+    reg32_t U;
+    struct _hw_spba_prrn_bitfields
+    {
+        unsigned RARA : 1; //!< [0] Resource Access Right.
+        unsigned RARB : 1; //!< [1] Resource Access Right.
+        unsigned RARC : 1; //!< [2] Resource Access Right.
+        unsigned RESERVED0 : 13; //!< [15:3] Reserved
+        unsigned ROI : 2; //!< [17:16] Resource Owner ID.
+        unsigned RESERVED1 : 12; //!< [29:18] Reserved
+        unsigned RMO : 2; //!< [31:30] Requesting Master Owner.
+    } B;
+} hw_spba_prrn_t;
+#endif
+
+/*!
+ * @name Constants and macros for entire SPBA_PRRn register
+ */
+//@{
+//! @brief Number of instances of the SPBA_PRRn register.
+#define HW_SPBA_PRRn_COUNT     (32)
+
+#define HW_SPBA_PRRn_ADDR(n)   (REGS_SPBA_BASE + 0x0 + (0x4 * (n)))
+
+#ifndef __LANGUAGE_ASM__
+#define HW_SPBA_PRRn(n)        (*(volatile hw_spba_prrn_t *) HW_SPBA_PRRn_ADDR(n))
+#define HW_SPBA_PRRn_RD(n)     (HW_SPBA_PRRn(n).U)
+#define HW_SPBA_PRRn_WR(n, v)  (HW_SPBA_PRRn(n).U = (v))
+#define HW_SPBA_PRRn_SET(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) |  (v)))
+#define HW_SPBA_PRRn_CLR(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) & ~(v)))
+#define HW_SPBA_PRRn_TOG(n, v) (HW_SPBA_PRRn_WR(n, HW_SPBA_PRRn_RD(n) ^  (v)))
+#endif
+//@}
+
+/*
+ * constants & macros for individual SPBA_PRRn bitfields
+ */
+
+/*! @name Register SPBA_PRRn, field RARA[0] (RW)
+ *
+ * Resource Access Right. Control and Status bit for master A. This field indicates whether master A
+ * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
+ * the master can be granted on a peripheral, but only one access at a time will be granted by
+ * SPBA).
+ *
+ * Values:
+ * - PROHIBITED = 0 - Access to peripheral is not allowed.
+ * - ALLOWED = 1 - Access to peripheral is granted.
+ */
+//@{
+#define BP_SPBA_PRRn_RARA      (0)      //!< Bit position for SPBA_PRRn_RARA.
+#define BM_SPBA_PRRn_RARA      (0x00000001)  //!< Bit mask for SPBA_PRRn_RARA.
+
+//! @brief Get value of SPBA_PRRn_RARA from a register value.
+#define BG_SPBA_PRRn_RARA(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARA) >> BP_SPBA_PRRn_RARA)
+
+//! @brief Format value for bitfield SPBA_PRRn_RARA.
+#define BF_SPBA_PRRn_RARA(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARA) & BM_SPBA_PRRn_RARA)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RARA field to a new value.
+#define BW_SPBA_PRRn_RARA(n, v)   (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARA) | BF_SPBA_PRRn_RARA(v)))
+#endif
+
+//! @brief Macro to simplify usage of value macros.
+#define BF_SPBA_PRRn_RARA_V(v) BF_SPBA_PRRn_RARA(BV_SPBA_PRRn_RARA__##v)
+
+#define BV_SPBA_PRRn_RARA__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
+#define BV_SPBA_PRRn_RARA__ALLOWED (0x1) //!< Access to peripheral is granted.
+//@}
+
+/*! @name Register SPBA_PRRn, field RARB[1] (RW)
+ *
+ * Resource Access Right. Control and Status bit for master B. This field indicates whether master B
+ * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
+ * the master can be granted on a peripheral, but only one access at a time will be granted by
+ * SPBA).
+ *
+ * Values:
+ * - PROHIBITED = 0 - Access to peripheral is not allowed.
+ * - ALLOWED = 1 - Access to peripheral is granted.
+ */
+//@{
+#define BP_SPBA_PRRn_RARB      (1)      //!< Bit position for SPBA_PRRn_RARB.
+#define BM_SPBA_PRRn_RARB      (0x00000002)  //!< Bit mask for SPBA_PRRn_RARB.
+
+//! @brief Get value of SPBA_PRRn_RARB from a register value.
+#define BG_SPBA_PRRn_RARB(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARB) >> BP_SPBA_PRRn_RARB)
+
+//! @brief Format value for bitfield SPBA_PRRn_RARB.
+#define BF_SPBA_PRRn_RARB(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARB) & BM_SPBA_PRRn_RARB)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RARB field to a new value.
+#define BW_SPBA_PRRn_RARB(n, v)   (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARB) | BF_SPBA_PRRn_RARB(v)))
+#endif
+
+//! @brief Macro to simplify usage of value macros.
+#define BF_SPBA_PRRn_RARB_V(v) BF_SPBA_PRRn_RARB(BV_SPBA_PRRn_RARB__##v)
+
+#define BV_SPBA_PRRn_RARB__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
+#define BV_SPBA_PRRn_RARB__ALLOWED (0x1) //!< Access to peripheral is granted.
+//@}
+
+/*! @name Register SPBA_PRRn, field RARC[2] (RW)
+ *
+ * Resource Access Right. Control and Status bit for master C. This field indicates whether master C
+ * can access the peripheral. From 0 up to 3 masters can have permission to access a resource (all
+ * the master can be granted on a peripheral, but only one access at a time will be granted by
+ * SPBA).
+ *
+ * Values:
+ * - PROHIBITED = 0 - Access to peripheral is not allowed.
+ * - ALLOWED = 1 - Access to peripheral is granted.
+ */
+//@{
+#define BP_SPBA_PRRn_RARC      (2)      //!< Bit position for SPBA_PRRn_RARC.
+#define BM_SPBA_PRRn_RARC      (0x00000004)  //!< Bit mask for SPBA_PRRn_RARC.
+
+//! @brief Get value of SPBA_PRRn_RARC from a register value.
+#define BG_SPBA_PRRn_RARC(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RARC) >> BP_SPBA_PRRn_RARC)
+
+//! @brief Format value for bitfield SPBA_PRRn_RARC.
+#define BF_SPBA_PRRn_RARC(v)   ((__REG_VALUE_TYPE((v), reg32_t) << BP_SPBA_PRRn_RARC) & BM_SPBA_PRRn_RARC)
+
+#ifndef __LANGUAGE_ASM__
+//! @brief Set the RARC field to a new value.
+#define BW_SPBA_PRRn_RARC(n, v)   (HW_SPBA_PRRn_WR(n, (HW_SPBA_PRRn_RD(n) & ~BM_SPBA_PRRn_RARC) | BF_SPBA_PRRn_RARC(v)))
+#endif
+
+//! @brief Macro to simplify usage of value macros.
+#define BF_SPBA_PRRn_RARC_V(v) BF_SPBA_PRRn_RARC(BV_SPBA_PRRn_RARC__##v)
+
+#define BV_SPBA_PRRn_RARC__PROHIBITED (0x0) //!< Access to peripheral is not allowed.
+#define BV_SPBA_PRRn_RARC__ALLOWED (0x1) //!< Access to peripheral is granted.
+//@}
+
+/*! @name Register SPBA_PRRn, field ROI[17:16] (RO)
+ *
+ * Resource Owner ID. This field indicates which master (one at a time) can access to the PRR for
+ * rights modification. This is a read-only register. After reset, ROI bits are cleared ("00" -> un-
+ * owned resource). A master performing a write access to the an un-owned PRR will get its ID
+ * automatically written into ROI, while modifying RARx bits. It can then read back the RMO, RAR,
+ * ROI bits to make sure RMO returns the right value, ROI bits contain its ID and RARx bits are
+ * correctly asserted. Then no other master (whom ID is different from the one stored in ROI) will
+ * be able to modify RAR fields. Owner master of a peripheral can assert its dead_owner signal, or
+ * write 1'b0 in the RARx to release the ownership (ROI[1:0] reset to 2'b0).
+ *
+ * Values:
+ * - UNOWNED = 00 - Unowned resource.
+ * - MASTER_A = 01 - The resource is owned by master A port.
+ * - MASTER_B = 10 - The resource is owned by master B port.
+ * - MASTER_C = 11 - The resource is owned by master C port.
+ */
+//@{
+#define BP_SPBA_PRRn_ROI      (16)      //!< Bit position for SPBA_PRRn_ROI.
+#define BM_SPBA_PRRn_ROI      (0x00030000)  //!< Bit mask for SPBA_PRRn_ROI.
+
+//! @brief Get value of SPBA_PRRn_ROI from a register value.
+#define BG_SPBA_PRRn_ROI(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_ROI) >> BP_SPBA_PRRn_ROI)
+
+//! @brief Macro to simplify usage of value macros.
+#define BF_SPBA_PRRn_ROI_V(v) BF_SPBA_PRRn_ROI(BV_SPBA_PRRn_ROI__##v)
+
+#define BV_SPBA_PRRn_ROI__UNOWNED (0x0) //!< Unowned resource.
+#define BV_SPBA_PRRn_ROI__MASTER_A (0x1) //!< The resource is owned by master A port.
+#define BV_SPBA_PRRn_ROI__MASTER_B (0x2) //!< The resource is owned by master B port.
+#define BV_SPBA_PRRn_ROI__MASTER_C (0x3) //!< The resource is owned by master C port.
+//@}
+
+/*! @name Register SPBA_PRRn, field RMO[31:30] (RO)
+ *
+ * Requesting Master Owner. This 2-bit register field indicates if the corresponding resource is
+ * owned by the requesting master or not. This register is reset to 2'b0 if ROI = 2'b0.
+ *
+ * Values:
+ * - UNOWNED = 00 - The resource is unowned.
+ * - 01 - Reserved.
+ * - ANOTHER_MASTER = 10 - The resource is owned by another master.
+ * - REQUESTING_MASTER = 11 - The resource is owned by the requesting master.
+ */
+//@{
+#define BP_SPBA_PRRn_RMO      (30)      //!< Bit position for SPBA_PRRn_RMO.
+#define BM_SPBA_PRRn_RMO      (0xc0000000)  //!< Bit mask for SPBA_PRRn_RMO.
+
+//! @brief Get value of SPBA_PRRn_RMO from a register value.
+#define BG_SPBA_PRRn_RMO(r)   ((__REG_VALUE_TYPE((r), reg32_t) & BM_SPBA_PRRn_RMO) >> BP_SPBA_PRRn_RMO)
+
+//! @brief Macro to simplify usage of value macros.
+#define BF_SPBA_PRRn_RMO_V(v) BF_SPBA_PRRn_RMO(BV_SPBA_PRRn_RMO__##v)
+
+#define BV_SPBA_PRRn_RMO__UNOWNED (0x0) //!< The resource is unowned.
+#define BV_SPBA_PRRn_RMO__ANOTHER_MASTER (0x2) //!< The resource is owned by another master.
+#define BV_SPBA_PRRn_RMO__REQUESTING_MASTER (0x3) //!< The resource is owned by the requesting master.
+//@}
+
+//-------------------------------------------------------------------------------------------
+// hw_spba_t - module struct
+//-------------------------------------------------------------------------------------------
+/*!
+ * @brief All SPBA module registers.
+ */
+#ifndef __LANGUAGE_ASM__
+#pragma pack(1)
+typedef struct _hw_spba
+{
+    volatile hw_spba_prrn_t PRRn[32]; //!< Peripheral Rights Register
+} hw_spba_t;
+#pragma pack()
+
+//! @brief Macro to access all SPBA registers.
+//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
+//!     use the '&' operator, like <code>&HW_SPBA</code>.
+#define HW_SPBA     (*(hw_spba_t *) REGS_SPBA_BASE)
+#endif
+
+#endif // __HW_SPBA_REGISTERS_H__
+// v18/121106/1.2.2
+// EOF

bsp/imx6ul/platform/include/mx6ul/regs.h

@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2012, Freescale Semiconductor, Inc. All Rights Reserved
+ * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
+ * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
+ * Freescale Semiconductor, Inc.
+ */
+
+#ifndef _REGS_H
+#define _REGS_H  1
+
+//
+// define base address of the register block only if it is not already
+// defined, which allows the compiler to override at build time for
+// users who've mapped their registers to locations other than the
+// physical location
+//
+
+#ifndef REGS_BASE
+#define REGS_BASE 0x00000000
+#endif
+
+//
+// common register types
+//
+
+#ifndef __LANGUAGE_ASM__
+typedef unsigned char reg8_t;
+typedef unsigned short reg16_t;
+typedef unsigned int reg32_t;
+#endif
+
+//
+// Typecast macro for C or asm. In C, the cast is applied, while in asm it is excluded. This is
+// used to simplify macro definitions in the module register headers.
+//
+#ifndef __REG_VALUE_TYPE
+    #ifndef __LANGUAGE_ASM__
+        #define __REG_VALUE_TYPE(v, t) ((t)(v))
+    #else
+        #define __REG_VALUE_TYPE(v, t) (v)
+    #endif
+#endif
+
+//
+// macros for single instance registers
+//
+
+#define BF_SET(reg, field)       HW_##reg##_SET(BM_##reg##_##field)
+#define BF_CLR(reg, field)       HW_##reg##_CLR(BM_##reg##_##field)
+#define BF_TOG(reg, field)       HW_##reg##_TOG(BM_##reg##_##field)
+
+#define BF_SETV(reg, field, v)   HW_##reg##_SET(BF_##reg##_##field(v))
+#define BF_CLRV(reg, field, v)   HW_##reg##_CLR(BF_##reg##_##field(v))
+#define BF_TOGV(reg, field, v)   HW_##reg##_TOG(BF_##reg##_##field(v))
+
+#define BV_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RD(reg, field)        HW_##reg.B.field
+#define BF_WR(reg, field, v)     BW_##reg##_##field(v)
+
+#define BF_CS1(reg, f1, v1)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for multiple instance registers
+//
+
+#define BF_SETn(reg, n, field)       HW_##reg##_SET(n, BM_##reg##_##field)
+#define BF_CLRn(reg, n, field)       HW_##reg##_CLR(n, BM_##reg##_##field)
+#define BF_TOGn(reg, n, field)       HW_##reg##_TOG(n, BM_##reg##_##field)
+
+#define BF_SETVn(reg, n, field, v)   HW_##reg##_SET(n, BF_##reg##_##field(v))
+#define BF_CLRVn(reg, n, field, v)   HW_##reg##_CLR(n, BF_##reg##_##field(v))
+#define BF_TOGVn(reg, n, field, v)   HW_##reg##_TOG(n, BF_##reg##_##field(v))
+
+#define BV_FLDn(reg, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BV_VALn(reg, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BF_RDn(reg, n, field)        HW_##reg(n).B.field
+#define BF_WRn(reg, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+//
+// macros for single instance MULTI-BLOCK registers
+//
+
+#define BFn_SET(reg, blk, field)       HW_##reg##_SET(blk, BM_##reg##_##field)
+#define BFn_CLR(reg, blk, field)       HW_##reg##_CLR(blk, BM_##reg##_##field)
+#define BFn_TOG(reg, blk, field)       HW_##reg##_TOG(blk, BM_##reg##_##field)
+
+#define BFn_SETV(reg, blk, field, v)   HW_##reg##_SET(blk, BF_##reg##_##field(v))
+#define BFn_CLRV(reg, blk, field, v)   HW_##reg##_CLR(blk, BF_##reg##_##field(v))
+#define BFn_TOGV(reg, blk, field, v)   HW_##reg##_TOG(blk, BF_##reg##_##field(v))
+
+#define BVn_FLD(reg, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VAL(reg, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RD(reg, blk, field)        HW_##reg(blk).B.field
+#define BFn_WR(reg, blk, field, v)     BW_##reg##_##field(blk, v)
+
+#define BFn_CS1(reg, blk, f1, v1)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
+
+#define BFn_CS2(reg, blk, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2)))
+
+#define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3)))
+
+#define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4)))
+
+#define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5)))
+
+#define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6)))
+
+#define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7)))
+
+#define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, BM_##reg##_##f1 |      \
+                        BM_##reg##_##f2 |      \
+                        BM_##reg##_##f3 |      \
+                        BM_##reg##_##f4 |      \
+                        BM_##reg##_##f5 |      \
+                        BM_##reg##_##f6 |      \
+                        BM_##reg##_##f7 |      \
+                        BM_##reg##_##f8),      \
+         HW_##reg##_SET(blk, BF_##reg##_##f1(v1) |  \
+                        BF_##reg##_##f2(v2) |  \
+                        BF_##reg##_##f3(v3) |  \
+                        BF_##reg##_##f4(v4) |  \
+                        BF_##reg##_##f5(v5) |  \
+                        BF_##reg##_##f6(v6) |  \
+                        BF_##reg##_##f7(v7) |  \
+                        BF_##reg##_##f8(v8)))
+
+//
+// macros for MULTI-BLOCK multiple instance registers
+//
+
+#define BFn_SETn(reg, blk, n, field)       HW_##reg##_SET(blk, n, BM_##reg##_##field)
+#define BFn_CLRn(reg, blk, n, field)       HW_##reg##_CLR(blk, n, BM_##reg##_##field)
+#define BFn_TOGn(reg, blk, n, field)       HW_##reg##_TOG(blk, n, BM_##reg##_##field)
+
+#define BFn_SETVn(reg, blk, n, field, v)   HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
+#define BFn_CLRVn(reg, blk, n, field, v)   HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
+#define BFn_TOGVn(reg, blk, n, field, v)   HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
+
+#define BVn_FLDn(reg, blk, n, field, sym)  BF_##reg##_##field(BV_##reg##_##field##__##sym)
+#define BVn_VALn(reg, blk, n, field, sym)  BV_##reg##_##field##__##sym
+
+#define BFn_RDn(reg, blk, n, field)        HW_##reg(n).B.field
+#define BFn_WRn(reg, blk, n, field, v)     BW_##reg##_##field(n, v)
+
+#define BFn_CS1n(reg, blk, n, f1, v1)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
+
+#define BFn_CS2n(reg, blk, n, f1, v1, f2, v2)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2))))
+
+#define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3))))
+
+#define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4))))
+
+#define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5))))
+
+#define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6))))
+
+#define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7))))
+
+#define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)  \
+        (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 |       \
+                            BM_##reg##_##f2 |       \
+                            BM_##reg##_##f3 |       \
+                            BM_##reg##_##f4 |       \
+                            BM_##reg##_##f5 |       \
+                            BM_##reg##_##f6 |       \
+                            BM_##reg##_##f7 |       \
+                            BM_##reg##_##f8)),      \
+         HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) |   \
+                            BF_##reg##_##f2(v2) |   \
+                            BF_##reg##_##f3(v3) |   \
+                            BF_##reg##_##f4(v4) |   \
+                            BF_##reg##_##f5(v5) |   \
+                            BF_##reg##_##f6(v6) |   \
+                            BF_##reg##_##f7(v7) |   \
+                            BF_##reg##_##f8(v8))))
+
+#endif // _REGS_H
+
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/mx6ul/soc_memory_map.h

@@ -0,0 +1,103 @@
+#ifndef _SOC_MEMORY_MAP_H
+#define _SOC_MEMORY_MAP_H
+
+#define ANATOP_IPS_BASE_ADDR 0x020c8000
+
+#define ADC1_BASE_ADDR 0x02198000
+#define ADC2_BASE_ADDR 0x0219c000
+#define APBH_BASE_ADDR 0x01804000
+#define ASRC_BASE_ADDR 0x02034000
+#define BCH_BASE_ADDR 0x01808000
+#define CCM_BASE_ADDR 0x020c4000
+#define CCM_ANALOG_BASE_ADDR 0x020c8000
+#define CSI_BASE_ADDR 0x021c4000
+#define ECSPI1_BASE_ADDR 0x02008000
+#define ECSPI2_BASE_ADDR 0x0200c000
+#define ECSPI3_BASE_ADDR 0x02010000
+#define ECSPI4_BASE_ADDR 0x02014000
+#define EIM_BASE_ADDR 0x021b8000
+#define EMVSIM1_BASE_ADDR 0x0218c000
+#define EMVSIM2_BASE_ADDR 0x021b4000
+#define ENET1_BASE_ADDR 0x02188000
+#define ENET2_BASE_ADDR 0x020b4000
+#define EPIT1_BASE_ADDR 0x020d0000
+#define EPIT2_BASE_ADDR 0x020d4000
+#define FLEXCAN1_BASE_ADDR 0x02090000
+#define FLEXCAN2_BASE_ADDR 0x02094000
+#define GPC_BASE_ADDR 0x020dc000
+#define GPIO1_BASE_ADDR 0x0209c000
+#define GPIO2_BASE_ADDR 0x020a0000
+#define GPIO3_BASE_ADDR 0x020a4000
+#define GPIO4_BASE_ADDR 0x020a8000
+#define GPIO5_BASE_ADDR 0x020ac000
+#define GPMI_BASE_ADDR 0x01806000
+#define GPT1_BASE_ADDR 0x02098000
+#define GPT2_BASE_ADDR 0x020e8000
+#define I2C1_BASE_ADDR 0x021a0000
+#define I2C2_BASE_ADDR 0x021a4000
+#define I2C3_BASE_ADDR 0x021a8000
+#define I2C4_BASE_ADDR 0x021f8000
+#define I2S1_BASE_ADDR 0x02028000
+#define I2S2_BASE_ADDR 0x0202c000
+#define I2S3_BASE_ADDR 0x02030000
+#define IOMUXC_BASE_ADDR 0x020e0000
+#define IOMUXC_GPR_BASE_ADDR 0x020e4000
+#define KPP_BASE_ADDR 0x020b8000
+#define LCDIF1_BASE_ADDR 0x02220000
+#define LCDIF2_BASE_ADDR 0x02224000
+#define MMDC_BASE_ADDR 0x021b0000
+#define OCOTP_BASE_ADDR 0x021bc000
+#define PMU_BASE_ADDR 0x020c8000
+#define PWM1_BASE_ADDR 0x02080000
+#define PWM2_BASE_ADDR 0x02084000
+#define PWM3_BASE_ADDR 0x02088000
+#define PWM4_BASE_ADDR 0x0208c000
+#define PWM5_BASE_ADDR 0x020f0000
+#define PWM6_BASE_ADDR 0x020f4000
+#define PWM7_BASE_ADDR 0x020f8000
+#define PWM8_BASE_ADDR 0x020fc000
+#define PXP_BASE_ADDR 0x021cc000
+#define QUADSPI_BASE_ADDR 0x021e0000
+#define ROMC_BASE_ADDR 0x021ac000
+#define SDMAARM_BASE_ADDR 0x020ec000
+#define SDMABP_BASE_ADDR 0x020ec000
+#define SDMACORE_BASE_ADDR 0x020ec000
+#define SJC_BASE_ADDR 0x00000000
+#define SNVS_BASE_ADDR 0x020cc000
+#define SPBA_BASE_ADDR 0x0203c000
+#define SPDIF_BASE_ADDR 0x02004000
+#define SRC_BASE_ADDR 0x020d8000
+#define TEMPMON_BASE_ADDR 0x020c8000
+#define UART1_BASE_ADDR 0x02020000
+#define UART2_BASE_ADDR 0x021e8000
+#define UART3_BASE_ADDR 0x021ec000
+#define UART4_BASE_ADDR 0x021f0000
+#define UART5_BASE_ADDR 0x021f4000
+#define UART6_BASE_ADDR 0x021fc000
+#define UART7_BASE_ADDR 0x02018000
+#define UART8_BASE_ADDR 0x02024000
+#define USB_BASE_ADDR 0x02184000
+#define USBNC_BASE_ADDR 0x02184000
+#define USBPHY1_BASE_ADDR 0x020c9000
+#define USBPHY2_BASE_ADDR 0x020ca000
+#define USDHC1_BASE_ADDR 0x02190000
+#define USDHC2_BASE_ADDR 0x02194000
+#define WDOG1_BASE_ADDR 0x020bc000
+#define WDOG2_BASE_ADDR 0x020c0000
+#define WDOG3_BASE_ADDR 0x021e4000
+#define XTALOSC24M_BASE_ADDR 0x020c8000
+
+#define USB_UOG1_BASE_ADDR USB_BASE_ADDR
+#define USB_UOG2_BASE_ADDR (USB_BASE_ADDR+0x200)
+
+#define CCM_ANALOG_PLL_USB1n (CCM_ANALOG_BASE_ADDR+0x10)
+#define CCM_ANALOG_PFD_528n (CCM_ANALOG_BASE_ADDR+0x100)
+
+#define CAN0_BASE_ADDR FLEXCAN1_BASE_ADDR
+#define CAN1_BASE_ADDR FLEXCAN2_BASE_ADDR
+#define CSD0_BASE_ADDR 0x80000000
+
+#define MMDC_P0_BASE_ADDR MMDC_BASE_ADDR
+
+
+#endif //_SOC_MEMORY_MAP_H

bsp/imx6ul/platform/include/sdk.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file sdk.h
+ * @brief       Basic defines
+ *
+ * @ingroup diag_init
+ */
+#ifndef __SDK_H__
+#define __SDK_H__
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+
+#include "sdk_types.h"
+#include "sdk_version.h"
+#include "io.h"
+
+#include "soc_memory_map.h"
+#include "registers.h"
+#include "iomux_define.h"
+#include "iomux_register.h"
+#include "interrupt.h"
+
+#include "gic.h"
+#include "ccm_pll.h"
+#include "imx_i2c.h"
+#include "imx_timer.h"
+#include "imx_uart.h"
+
+#endif // __SDK_H__

bsp/imx6ul/platform/include/sdk_types.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __SDK_TYPES_H__
+#define __SDK_TYPES_H__
+
+//! @addtogroup sdk_common
+//! @{
+
+/*!
+ * @file sdk_types.h
+ * @brief Basic types used throughout the SDK.
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdarg.h>
+#include <stdio.h>
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @name Alternate Boolean constants
+//@{
+#define TRUE        1
+#define FALSE       0
+//@}
+
+//! @brief 
+#define NONE_CHAR   (0xFF)
+
+//! @brief A parameter was out of range or otherwise invalid.
+#define INVALID_PARAMETER (-1)
+
+//! @name Min/max macros
+//@{
+#if !defined(MIN)
+    #define MIN(a, b)   ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+    #define MAX(a, b)   ((a) > (b) ? (a) : (b))
+#endif
+//@}
+
+//! @brief Computes the number of elements in an array.
+#define ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
+
+//! @brief Debug print utility.
+//!
+//! This print function will only output text when the @a DEBUG macro is defined.
+static inline void debug_printf(const char * format, ...)
+{
+#if defined(DEBUG)
+    va_list args;
+    va_start(args, format);
+    vprintf(format, args);
+    va_end(args);
+#endif
+}
+
+//! @name Test results
+typedef enum _test_return
+{
+    TEST_NOT_STARTED     = -3, // present in the menu, but not run
+    TEST_NOT_IMPLEMENTED = -2, // present in the menu, but not functional
+    TEST_FAILED          = -1,
+    TEST_PASSED          = 0,
+    TEST_BYPASSED        = 2,  // user elected to exit the test before it was run
+    TEST_NOT_PRESENT     = 3,  // not present in the menu.
+    TEST_CONTINUE        = 4   // proceed with the test. opposite of TEST_BYPASSED
+} test_return_t;
+
+//! @name Return codes
+//@{
+#define SUCCESS (0)
+#define FAIL (1)
+#define ERROR_GENERIC (-1)
+#define ERROR_OUT_OF_MEMORY (-2)
+//@}
+
+//! @brief Possible types of displays.
+enum display_type {
+    DISP_DEV_NULL = 0,
+    DISP_DEV_TFTLCD,
+    DISP_DEV_LVDS,
+    DISP_DEV_VGA,
+    DISP_DEV_HDMI,
+    DISP_DEV_TV,
+    DISP_DEV_MIPI,
+};
+
+//! @}
+
+#endif // __SDK_TYPES_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/platform/include/sdk_version.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2008-2013, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * @file sdk_version.h
+ * @brief SDK release version defines.
+ *
+ * @ingroup diag_util
+ */
+
+#if !defined(__SDK_VERSION_H__)
+#define __SDK_VERSION_H__
+
+////////////////////////////////////////////////////////////////////////////////
+// Definitions
+////////////////////////////////////////////////////////////////////////////////
+
+//! @brief Current version of the SDK.
+#define SDK_VERSION_STRING	"1.2"
+
+//! @name SDK version number components
+//@{
+#define SDK_VERSION_MAJOR 1
+#define SDK_VERSION_MINOR 1
+#define SDK_VERSION_BUGFIX 0
+//@}
+
+//! @brief Current version of the SDK.
+extern const char k_sdk_version[];
+
+//! @brief Copyright string for the SDK.
+extern const char k_sdk_copyright[];
+
+#endif // __SDK_VERSION_H__
+////////////////////////////////////////////////////////////////////////////////
+// EOF
+////////////////////////////////////////////////////////////////////////////////

bsp/imx6ul/rtconfig.h

@@ -0,0 +1,194 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
+
+// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
+#define RT_NAME_MAX	6
+// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
+#define RT_ALIGN_SIZE	4
+// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
+// <item description="8">8</item>
+// <item description="32">32</item>
+// <item description="256">256</item>
+// </integer>
+#define RT_THREAD_PRIORITY_MAX	32
+// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
+#define RT_TICK_PER_SECOND	1000
+// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
+#define IDLE_THREAD_STACK_SIZE	512
+// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
+#define RT_DEBUG
+// <integer name="RT_DEBUG_SCHEDULER" description="scheduler debug enable" default="0" />
+// #define RT_DEBUG_SCHEDULER  1
+// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
+#define RT_USING_OVERFLOW_CHECK
+// </section>
+
+// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+#define RT_USING_HOOK
+// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
+// #define RT_USING_TIMER_SOFT
+// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
+#define RT_TIMER_THREAD_PRIO	4
+// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
+#define RT_TIMER_THREAD_STACK_SIZE	512
+// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
+#define RT_TIMER_TICK_PER_SECOND	10
+// </section>
+
+// <section name="IPC" description="Inter-Thread communication" default="always" >
+// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_SEMAPHORE
+// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
+#define RT_USING_MUTEX
+// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
+#define RT_USING_EVENT
+// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
+#define RT_USING_MAILBOX
+// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
+#define RT_USING_MESSAGEQUEUE
+// </section>
+
+// <section name="MM" description="Memory Management" default="always" >
+// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+#define RT_USING_MEMPOOL
+// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
+// #define RT_USING_MEMHEAP
+// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
+#define RT_USING_HEAP
+// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
+// #define RT_USING_MEMHEAP_AS_HEAP
+// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_SMALL_MEM
+// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
+// #define RT_USING_SLAB
+// </section>
+
+// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using IPC in Device Driver Framework" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
+#define RT_USING_SERIAL
+// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
+#define RT_UART_RX_BUFFER_SIZE    64
+// <bool name="RT_USING_INTERRUPT_INFO" description="Using interrupt information description" default="true" />
+#define RT_USING_INTERRUPT_INFO
+// <bool name="RT_USING_UART0" description="Enable UART0" default="false" />
+// #define RT_USING_UART0
+// <bool name="RT_USING_UART1" description="Enable UART1" default="true" />
+#define RT_USING_UART1
+// </section>
+
+// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_CONSOLE
+// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
+#define RT_CONSOLE_DEVICE_NAME	"uart1"
+// </section>
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_FINSH
+// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
+#define FINSH_USING_MSH
+// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
+#define FINSH_USING_MSH_DEFAULT
+// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_USING_SYMTAB
+// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
+#define FINSH_USING_DESCRIPTION
+// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
+#define FINSH_THREAD_STACK_SIZE	4096
+// </section>
+
+// <section name="LIBC" description="C Runtime library setting" default="always" >
+// <bool name="RT_USING_LIBC" description="Using libc library" default="true" />
+#define RT_USING_LIBC
+// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
+#define RT_USING_PTHREADS
+// </section>
+
+// <section name="RT_USING_DFS" description="Device file system" default="true" >
+// #define RT_USING_DFS
+// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
+#define DFS_USING_WORKDIR
+// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
+#define DFS_FILESYSTEMS_MAX	2
+// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
+#define DFS_FD_MAX	4
+// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+// #define RT_USING_DFS_ELMFAT
+// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
+// <item description="LFN1">1</item>
+// <item description="LFN1">2</item>
+// </integer>
+#define RT_DFS_ELM_USE_LFN	1
+// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
+#define RT_DFS_ELM_MAX_LFN	64
+// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
+// #define RT_USING_DFS_YAFFS2
+// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
+// #define RT_USING_DFS_UFFS
+// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+#define RT_USING_DFS_DEVFS
+// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
+// #define RT_USING_DFS_NFS
+// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
+#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+// </section>
+
+// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
+// #define RT_USING_LWIP
+// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_LWIP_ICMP
+// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
+// #define RT_LWIP_IGMP
+// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_UDP
+// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
+#define RT_LWIP_TCP
+// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
+#define RT_LWIP_DNS
+// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
+// #define RT_LWIP_SNMP
+// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
+#define RT_LWIP_DHCP
+// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
+#define RT_LWIP_TCPTHREAD_PRIORITY	12
+// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
+#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
+#define RT_LWIP_ETHTHREAD_PRIORITY	14
+// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
+#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
+// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
+// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
+// </section>
+
+#define RT_USING_LOGTRACE
+
+// </RDTConfigurator>
+
+#endif

bsp/imx6ul/rtconfig.py

@@ -0,0 +1,101 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-a'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM 	= 'gcc'
+    EXEC_PATH   = '/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM 	= 'armcc'
+    EXEC_PATH 	= 'C:/Keil'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LINK_SCRIPT = 'imx6.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-imx6.map,-cref,-u,system_vectors'+\
+                      ' -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = ''
+
+    # generate debug info in all cases
+    AFLAGS += ' -gdwarf-2'
+    CFLAGS += ' -g -gdwarf-2'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+                  SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMP'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-imx6.map --scatter imx6.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' --cpu DARMP'
+
+    CFLAGS = ''
+    AFLAGS = ''
+    LFLAGS = ' --config imx6.icf'
+
+    EXEC_PATH += '/arm/bin/'
+    RT_USING_MINILIBC = False
+    POST_ACTION = ''

libcpu/Kconfig

@@ -33,21 +33,25 @@ config ARCH_ARM_MMU
     bool
     depends on ARCH_ARM
 
-config ARCH_ARM_CORTEX_A5
+config ARCH_ARM_CORTEX_A
     bool
     select ARCH_ARM
 
+config ARCH_ARM_CORTEX_A5
+    bool
+    select ARCH_ARM_CORTEX_A
+
 config ARCH_ARM_CORTEX_A7
     bool
-    select ARCH_ARM
+    select ARCH_ARM_CORTEX_A
 
 config ARCH_ARM_CORTEX_A8
     bool
-    select ARCH_ARM
+    select ARCH_ARM_CORTEX_A
 
 config ARCH_ARM_CORTEX_A9
     bool
-    select ARCH_ARM
+    select ARCH_ARM_CORTEX_A
 
 config ARCH_MIPS
     bool

libcpu/arm/cortex-a/armv7.h

@@ -0,0 +1,64 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+struct rt_hw_stack
+{
+	unsigned long cpsr;
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long lr;
+	unsigned long pc;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif

libcpu/arm/cortex-a/context_gcc.S

@@ -0,0 +1,105 @@
+/*
+ * File      : context.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .text, "ax"
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid i
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+.section .bss.share.isr
+_guest_switch_lvl:
+    .word 0
+
+.globl vmm_virq_update
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    orrne r4, r4, #0x20     @ it's thumb code
+
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r0, [ip]
+    str r3, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr

libcpu/arm/cortex-a/cp15.h

@@ -0,0 +1,12 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif

libcpu/arm/cortex-a/cp15_gcc.S

@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr

libcpu/arm/cortex-a/cpu.c

@@ -0,0 +1,37 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+	rt_uint32_t level;
+	rt_kprintf("shutdown...\n");
+
+	level = rt_hw_interrupt_disable();
+	while (level)
+	{
+		RT_ASSERT(0);
+	}
+}
+
+/*@}*/

libcpu/arm/cortex-a/interrupt.c

@@ -0,0 +1,152 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-06     Bernard      first version
+ * 2014-04-03     Grissiom     port to VMM
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <irq_numbers.h>
+#include <interrupt.h>
+
+#include <gic.h>
+#include "cp15.h"
+
+#define MAX_HANDLERS                IMX_INTERRUPT_COUNT
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+extern void rt_cpu_vector_set_base(unsigned int addr);
+extern int system_vectors;
+
+/* keep compatible with platform SDK */
+void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
+{
+    rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
+}
+
+void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
+{
+    gic_set_irq_priority(irq_id, priority);
+    gic_set_irq_security(irq_id, false);    // set IRQ as non-secure
+    gic_set_cpu_target(irq_id, cpu_id, true);
+    gic_enable_irq(irq_id, true);
+}
+
+void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
+{
+    gic_enable_irq(irq_id, false);
+    gic_set_cpu_target(irq_id, cpu_id, false);
+}
+
+static void rt_hw_vector_init(void)
+{
+    int sctrl;
+    unsigned int *src = (unsigned int *)&system_vectors;
+
+    /* C12-C0 is only active when SCTLR.V = 0 */
+    asm volatile ("mrc p15, #0, %0, c1, c0, #0"
+                  :"=r" (sctrl));
+    sctrl &= ~(1 << 13);
+    asm volatile ("mcr p15, #0, %0, c1, c0, #0"
+                  :
+                  :"r" (sctrl));
+
+    asm volatile ("mcr p15, #0, %0, c12, c0, #0"
+                  :
+                  :"r" (src));
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_hw_vector_init();
+    gic_init();
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    disable_interrupt(vector, 0);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    enable_interrupt(vector, 0, 0);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+        // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
+    }
+
+    return old_handler;
+}
+
+/**
+ * Trigger a software IRQ
+ *
+ * Since we are running in single core, the target CPU are always CPU0.
+ */
+void rt_hw_interrupt_trigger(int vector)
+{
+    // arm_gic_trigger(0, 1, vector);
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    gic_write_end_of_irq(vector);
+}

libcpu/arm/cortex-a/mmu.c

@@ -0,0 +1,207 @@
+/*
+ * File      : mmu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-01-10     bernard      porting to AM1808
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  // eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write without cache and write buffer */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+/* dump 2nd level page table */
+void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    for (i = 0; i < 256; i++)
+    {
+        rt_uint32_t pte2 = ptb[i];
+        if ((pte2 & 0x3) == 0)
+        {
+            if (fcnt == 0)
+                rt_kprintf("    ");
+            rt_kprintf("%04x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("    %04x: %x: ", i, pte2);
+        if ((pte2 & 0x3) == 0x1)
+        {
+            rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf,
+                       (pte2 >> 15) & 0x1,
+                       ((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
+                       ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
+                       ((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
+        }
+    }
+}
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* 4G 1:1 memory */
+    rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
+    /* IO memory region */
+    rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+

libcpu/arm/cortex-a/pmu.c

@@ -0,0 +1,12 @@
+#include <rtthread.h>
+#include "pmu.h"
+
+void rt_hw_pmu_dump_feature(void)
+{
+    unsigned long reg;
+
+    reg = rt_hw_pmu_get_control();
+    rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n",
+               reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f);
+    RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f));
+}

libcpu/arm/cortex-a/pmu.h

@@ -0,0 +1,151 @@
+#ifndef __PMU_H__
+#define __PMU_H__
+
+#include "board.h"
+
+/* Number of counters */
+#define ARM_PMU_CNTER_NR 4
+
+enum rt_hw_pmu_event_type {
+    ARM_PMU_EVENT_PMNC_SW_INCR      = 0x00,
+    ARM_PMU_EVENT_L1_ICACHE_REFILL  = 0x01,
+    ARM_PMU_EVENT_ITLB_REFILL       = 0x02,
+    ARM_PMU_EVENT_L1_DCACHE_REFILL  = 0x03,
+    ARM_PMU_EVENT_L1_DCACHE_ACCESS  = 0x04,
+    ARM_PMU_EVENT_DTLB_REFILL       = 0x05,
+    ARM_PMU_EVENT_MEM_READ          = 0x06,
+    ARM_PMU_EVENT_MEM_WRITE         = 0x07,
+    ARM_PMU_EVENT_INSTR_EXECUTED    = 0x08,
+    ARM_PMU_EVENT_EXC_TAKEN         = 0x09,
+    ARM_PMU_EVENT_EXC_EXECUTED      = 0x0A,
+    ARM_PMU_EVENT_CID_WRITE         = 0x0B,
+};
+
+/* Enable bit */
+#define ARM_PMU_PMCR_E   (0x01 << 0)
+/* Event counter reset */
+#define ARM_PMU_PMCR_P   (0x01 << 1)
+/* Cycle counter reset */
+#define ARM_PMU_PMCR_C   (0x01 << 2)
+/* Cycle counter divider */
+#define ARM_PMU_PMCR_D   (0x01 << 3)
+
+#ifdef __GNUC__
+rt_inline void rt_hw_pmu_enable_cnt(int divide64)
+{
+    unsigned long pmcr;
+    unsigned long pmcntenset;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
+    if (divide64)
+        pmcr |= ARM_PMU_PMCR_D;
+    else
+        pmcr &= ~ARM_PMU_PMCR_D;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+
+    /* enable all the counters */
+    pmcntenset = ~0;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
+    /* clear overflows(just in case) */
+    asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
+}
+
+rt_inline unsigned long rt_hw_pmu_get_control(void)
+{
+    unsigned long pmcr;
+    asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    return pmcr;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ceid(void)
+{
+    unsigned long reg;
+    /* only PMCEID0 is supported, PMCEID1 is RAZ. */
+    asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cnten(void)
+{
+    unsigned long pmcnt;
+    asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
+    return pmcnt;
+}
+
+rt_inline void rt_hw_pmu_reset_cycle(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_C;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_reset_event(void)
+{
+    unsigned long pmcr;
+
+    asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
+    pmcr |= ARM_PMU_PMCR_P;
+    asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
+    asm volatile ("isb");
+}
+
+rt_inline unsigned long rt_hw_pmu_get_cycle(void)
+{
+    unsigned long cyc;
+    asm volatile ("isb");
+    asm volatile ("mrc  p15, 0, %0, c9, c13, 0" : "=r"(cyc));
+    return cyc;
+}
+
+rt_inline void rt_hw_pmu_select_counter(int idx)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
+    /* Linux add an isb here, don't know why here. */
+    asm volatile ("isb");
+}
+
+rt_inline void rt_hw_pmu_select_event(int idx,
+                                      enum rt_hw_pmu_event_type eve)
+{
+    RT_ASSERT(idx < ARM_PMU_CNTER_NR);
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
+}
+
+rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
+{
+    unsigned long reg;
+
+    rt_hw_pmu_select_counter(idx);
+    asm volatile ("isb");
+    asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
+    return reg;
+}
+
+rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
+{
+    unsigned long reg;
+    asm volatile ("isb");
+    asm ("mrc  p15, 0, %0, c9, c12, 3" : "=r"(reg));
+    return reg;
+}
+
+rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
+{
+    asm ("mcr  p15, 0, %0, c9, c12, 3" : : "r"(reg));
+    asm volatile ("isb");
+}
+
+#endif
+
+void rt_hw_pmu_dump_feature(void);
+
+#endif /* end of include guard: __PMU_H__ */
+

libcpu/arm/cortex-a/stack.c

@@ -0,0 +1,66 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+#include <armv7.h>
+
+/**
+ * @addtogroup AM33xx
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_uint32_t *stk;
+
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+
+	/* cpsr */
+	if ((rt_uint32_t)tentry & 0x01)
+		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
+	else
+		*(--stk) = SVCMODE;					/* arm mode   */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/

libcpu/arm/cortex-a/start_gcc.S

@@ -0,0 +1,249 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,     0x00000000
+.equ SVC_Stack_Size,     0x00000100
+.equ ABT_Stack_Size,     0x00000000
+.equ RT_FIQ_STACK_PGSZ,  0x00000000
+.equ RT_IRQ_STACK_PGSZ,  0x00000100
+.equ USR_Stack_Size,     0x00000100
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
+
+.section .data.share.isr
+/* stack */
+.globl stack_start
+.globl stack_top
+
+stack_start:
+.rept ISR_Stack_Size
+.byte 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+    bl      rt_cpu_mmu_disable
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+ctor_end:
+
+    /* start RT-Thread Kernel */
+    ldr     pc, _rtthread_startup
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_FIQ_STACK_PGSZ
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #RT_IRQ_STACK_PGSZ
+
+    /* come back to SVC mode */
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+    bx      lr
+
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+.section .text.isr, "ax"
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc, lr, #4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+.globl      rt_current_thread
+.globl      vmm_thread
+.globl      vmm_virq_check
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq     rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc,  lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt. If the usr mode guest is
+    @ interrupted, this will just switch to the stack of kernel space.
+    @ save the registers in kernel space won't trigger data abort.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r6,  [r6]
+    ldr     sp,  [r6]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl	vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl	vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl	vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl	vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl	vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .

libcpu/arm/cortex-a/trap.c

@@ -0,0 +1,181 @@
+/*
+ * File      : trap.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "armv7.h"
+
+#include "gic.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0]
+    // send ack and get ID source
+    uint32_t vectNum = gic_read_irq_ack();
+
+    // Check that INT_ID isn't 1023 or 1022 (spurious interrupt)
+    if (vectNum & 0x0200)
+    {
+        gic_write_end_of_irq(vectNum);  // send end of irq
+    }
+    else
+    {
+        // copy the local value to the global image of CPUID
+        unsigned cpu = (vectNum >> 10) & 0x7;
+        unsigned irq = vectNum & 0x1FF;
+
+        /* skip warning */
+        cpu = cpu;
+
+        // Call the service routine stored in the handlers array. If there isn't
+        // one for this IRQ, then call the default handler.
+        /* get interrupt service routine */
+        isr_func = isr_table[irq].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+        isr_table[irq].counter++;
+#endif
+        if (isr_func)
+        {
+            /* Interrupt for myself. */
+            param = isr_table[irq].param;
+            /* turn to interrupt service routine */
+            isr_func(irq, param);
+        }
+
+        // Signal the end of the irq.
+        gic_write_end_of_irq(vectNum);
+    }
+}
+
+void rt_hw_trap_fiq(void)
+{
+    /* TODO */
+}

libcpu/arm/cortex-a/vector_gcc.S

@@ -0,0 +1,65 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl 	16,0xdeadbeef