mirror of https://github.com/RT-Thread/rt-thread
96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
|
|
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
|
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
|
|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
|
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
|
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
/*
|
|
* Copyright (c) 2006-2025, RT-Thread Development Team
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#ifndef DRV_TIMER_H__
|
|
#define DRV_TIMER_H__
|
|
#include <stdint.h>
|
|
#include <drivers/hwtimer.h>
|
|
#include "sysctl_clk.h"
|
|
|
|
#define MHz 1000000
|
|
/* TIMER Control Register */
|
|
#define TIMER_CR_ENABLE 0x00000001
|
|
#define TIMER_CR_MODE_MASK 0x00000002
|
|
#define TIMER_CR_FREE_MODE 0x00000000
|
|
#define TIMER_CR_USER_MODE 0x00000002
|
|
#define TIMER_CR_INTERRUPT_MASK 0x00000004
|
|
#define TIMER_CR_PWM_ENABLE 0x00000008
|
|
|
|
#define IRQN_TIMER_0_INTERRUPT 16+85
|
|
#define IRQN_TIMER_1_INTERRUPT 16+86
|
|
#define IRQN_TIMER_2_INTERRUPT 16+87
|
|
#define IRQN_TIMER_3_INTERRUPT 16+88
|
|
#define IRQN_TIMER_4_INTERRUPT 16+89
|
|
#define IRQN_TIMER_5_INTERRUPT 16+90
|
|
|
|
typedef struct _timer_regs_channel
|
|
{
|
|
/* TIMER_N Load Count Register (0x00+(N-1)*0x14) */
|
|
volatile uint32_t load_count;
|
|
/* TIMER_N Current Value Register (0x04+(N-1)*0x14) */
|
|
volatile uint32_t current_value;
|
|
/* TIMER_N Control Register (0x08+(N-1)*0x14) */
|
|
volatile uint32_t control;
|
|
/* TIMER_N Interrupt Clear Register (0x0c+(N-1)*0x14) */
|
|
volatile uint32_t eoi;
|
|
/* TIMER_N Interrupt Status Register (0x10+(N-1)*0x14) */
|
|
volatile uint32_t intr_stat;
|
|
} __attribute__((packed, aligned(4))) k230_timer_regs_channel_t;
|
|
|
|
typedef struct _k230_timer_regs
|
|
{
|
|
/* TIMER_N Register (0x00-0x4c) */
|
|
volatile k230_timer_regs_channel_t channel[5];
|
|
/* reserverd (0x50-0x9c) */
|
|
volatile uint32_t resv1[20];
|
|
/* TIMER Interrupt Status Register (0xa0) */
|
|
volatile uint32_t intr_stat;
|
|
/* TIMER Interrupt Clear Register (0xa4) */
|
|
volatile uint32_t eoi;
|
|
/* TIMER Raw Interrupt Status Register (0xa8) */
|
|
volatile uint32_t raw_intr_stat;
|
|
/* TIMER Component Version Register (0xac) */
|
|
volatile uint32_t comp_version;
|
|
/* TIMER_N Load Count2 Register (0xb0-0xbc) */
|
|
volatile uint32_t load_count2[4];
|
|
} __attribute__((packed, aligned(4))) k230_timer_regs_t;
|
|
|
|
struct k230_timer {
|
|
struct rt_hwtimer_device device;
|
|
const char *name;
|
|
rt_ubase_t base;
|
|
uint32_t id;
|
|
sysctl_clk_node_e clk;
|
|
sysctl_clk_node_e clk_src;
|
|
int irq_num;
|
|
};
|
|
|
|
#endif |