From 0984fd045f10a79c2a82e80a237be44bcea2a47f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 5 Apr 2025 10:46:39 -0400 Subject: [PATCH] Change `--trace` to `--trace-vcd`. --- Changes | 1 + bin/verilator | 3 +- docs/guide/exe_verilator.rst | 41 ++++++++++++------- docs/guide/extensions.rst | 2 +- docs/guide/faq.rst | 4 +- docs/guide/files.rst | 4 +- docs/guide/languages.rst | 2 +- docs/guide/verilating.rst | 14 ++++--- examples/make_protect_lib/Makefile | 2 +- examples/make_tracing_c/Makefile | 2 +- examples/make_tracing_sc/Makefile | 2 +- include/verilated.cpp | 2 +- include/verilated_saif_c.cpp | 4 +- include/verilated_vcd_c.cpp | 4 +- src/V3EmitCMake.cpp | 6 +-- src/V3EmitCModel.cpp | 2 +- src/V3EmitMk.cpp | 10 ++--- src/V3Options.cpp | 6 ++- test_regress/driver.py | 2 +- test_regress/t/t_a1_first_cc.py | 2 +- test_regress/t/t_a2_first_sc.py | 2 +- test_regress/t/t_case_incrdecr.py | 2 +- test_regress/t/t_ccache_report.py | 2 +- test_regress/t/t_clocker.py | 2 +- test_regress/t/t_cover_expr_trace.py | 2 +- test_regress/t/t_cover_line_trace.py | 3 +- test_regress/t/t_cover_sva_trace.py | 2 +- test_regress/t/t_cover_trace_always.py | 2 +- test_regress/t/t_cxx_equal_to.py | 2 +- test_regress/t/t_debug_trace.py | 2 +- test_regress/t/t_flag_build.py | 2 +- test_regress/t/t_flag_csplit.py | 2 +- test_regress/t/t_flag_csplit_groups.py | 2 +- test_regress/t/t_flag_csplit_off.py | 2 +- test_regress/t/t_force_release_net_trace.py | 2 +- test_regress/t/t_force_release_var_trace.py | 2 +- test_regress/t/t_forceable_net_cmt_trace.py | 2 +- test_regress/t/t_forceable_net_vlt_trace.py | 9 ++-- test_regress/t/t_forceable_var_cmt_trace.py | 2 +- test_regress/t/t_forceable_var_vlt_trace.py | 9 ++-- test_regress/t/t_func_public_trace.py | 2 +- test_regress/t/t_func_while.py | 2 +- test_regress/t/t_hier_block_sc_trace_vcd.py | 2 +- test_regress/t/t_hier_block_trace_vcd.py | 2 +- test_regress/t/t_hier_trace.py | 4 +- test_regress/t/t_hier_trace_noinl.py | 4 +- test_regress/t/t_interface1_modport_trace.py | 2 +- test_regress/t/t_interface_ref_trace.py | 2 +- test_regress/t/t_interface_ref_trace_inla.py | 2 +- test_regress/t/t_interface_ref_trace_inlab.py | 2 +- test_regress/t/t_interface_ref_trace_inlb.py | 2 +- test_regress/t/t_interface_ref_trace_noinl.py | 2 +- test_regress/t/t_lint_subout_bad.py | 2 +- test_regress/t/t_mem_multi_io.py | 2 +- test_regress/t/t_mem_multidim_trace.py | 2 +- test_regress/t/t_mem_trace_split.py | 2 +- test_regress/t/t_no_trace_top.py | 2 +- test_regress/t/t_opt_const_cov.py | 2 +- test_regress/t/t_order_clkinst.py | 2 +- test_regress/t/t_order_multidriven.py | 4 +- test_regress/t/t_param_type_bad.py | 2 +- test_regress/t/t_param_type_bad2.py | 2 +- test_regress/t/t_protect_ids.py | 2 +- test_regress/t/t_protect_ids_debug.py | 2 +- test_regress/t/t_scope_map.py | 4 +- test_regress/t/t_split_var_2_trace.py | 2 +- test_regress/t/t_split_var_types.py | 2 +- test_regress/t/t_split_var_types.v | 2 +- test_regress/t/t_struct_init_trace.py | 2 +- test_regress/t/t_time_vpi_1ms10ns.py | 2 +- test_regress/t/t_time_vpi_1ns1ns.py | 2 +- test_regress/t/t_timing_osc.py | 2 +- test_regress/t/t_timing_trace.py | 2 +- test_regress/t/t_trace_abort.py | 2 +- test_regress/t/t_trace_array.py | 2 +- test_regress/t/t_trace_array_threads_1.py | 2 +- test_regress/t/t_trace_ascendingrange.py | 2 +- test_regress/t/t_trace_cat.py | 4 +- test_regress/t/t_trace_cat_renew.py | 4 +- test_regress/t/t_trace_cat_reopen.py | 4 +- test_regress/t/t_trace_class.py | 4 +- test_regress/t/t_trace_complex.py | 2 +- test_regress/t/t_trace_complex_params.py | 2 +- test_regress/t/t_trace_complex_portable.py | 2 +- test_regress/t/t_trace_complex_structs.py | 2 +- test_regress/t/t_trace_complex_threads_1.py | 2 +- test_regress/t/t_trace_decoration.py | 2 +- test_regress/t/t_trace_dumpvars_dyn_vcd_0.py | 2 +- test_regress/t/t_trace_dumpvars_dyn_vcd_1.py | 2 +- test_regress/t/t_trace_empty.py | 2 +- test_regress/t/t_trace_event.py | 2 +- test_regress/t/t_trace_iface.py | 2 +- test_regress/t/t_trace_no_top_name.py | 2 +- test_regress/t/t_trace_no_top_name2_vcd.py | 2 +- test_regress/t/t_trace_noflag_bad.out | 2 +- .../t/t_trace_open_wrong_order_bad.py | 2 +- test_regress/t/t_trace_packed_struct.py | 2 +- test_regress/t/t_trace_param.py | 2 +- test_regress/t/t_trace_param_override.py | 2 +- test_regress/t/t_trace_primitive.py | 2 +- test_regress/t/t_trace_public_func.py | 2 +- test_regress/t/t_trace_public_func_vlt.py | 2 +- test_regress/t/t_trace_public_sig.py | 2 +- test_regress/t/t_trace_public_sig_vlt.py | 2 +- test_regress/t/t_trace_rollover.py | 4 +- test_regress/t/t_trace_sc_empty.py | 2 +- test_regress/t/t_trace_scope_no_inline.py | 2 +- test_regress/t/t_trace_scope_vlt.py | 2 +- test_regress/t/t_trace_scstruct.py | 2 +- test_regress/t/t_trace_split_cfuncs.py | 2 +- .../t/t_trace_split_cfuncs_dpi_export.py | 2 +- test_regress/t/t_trace_string.py | 2 +- test_regress/t/t_trace_string_fst.py | 2 +- test_regress/t/t_trace_string_fst_sc.py | 2 +- test_regress/t/t_trace_timescale.py | 2 +- test_regress/t/t_trace_timing1.py | 2 +- .../t/t_trace_ub_misaligned_address.py | 2 +- test_regress/t/t_trace_wide_struct.py | 2 +- test_regress/t/t_unopt_array_csplit.py | 2 +- test_regress/t/t_unroll_delay.py | 2 +- test_regress/t/t_var_pins_sc1.py | 2 +- test_regress/t/t_var_pins_sc2.py | 2 +- test_regress/t/t_var_pins_sc32.py | 2 +- test_regress/t/t_var_pins_sc64.py | 2 +- test_regress/t/t_var_pins_sc_biguint.py | 2 +- test_regress/t/t_var_pins_sc_uint.py | 2 +- test_regress/t/t_var_pins_sc_uint_biguint.py | 2 +- test_regress/t/t_var_pins_sc_uint_bool.py | 2 +- .../t/t_var_pins_sc_uint_bool_nomain.py | 2 +- test_regress/t/t_var_pins_scui.py | 2 +- test_regress/t/t_verilated_all.py | 2 +- test_regress/t/t_verilated_all_newest.py | 2 +- test_regress/t/t_verilated_threaded.py | 2 +- test_regress/t/t_vthread.py | 4 +- test_regress/t/t_wrapper_context.py | 2 +- test_regress/t/t_wrapper_context_seq.py | 2 +- verilator-config.cmake.in | 6 ++- 137 files changed, 214 insertions(+), 174 deletions(-) diff --git a/Changes b/Changes index 1e77503fa..f8643da99 100644 --- a/Changes +++ b/Changes @@ -23,6 +23,7 @@ Verilator 5.035 devel * Support command-line overriding `define (#5900) (#5908). [Brian Li] * Support `$setuphold` (#5884). [Krzysztof Sychla] * Support `systemc_interface and related inside `class`. +* Change `--trace` to `--trace-vcd`. * Add multi-thread hierarchical simulation (#2583) (#5871). [Bartłomiej Chmiel, Antmicro Ltd.] * Add check for `let` misused in statement context (#5733). * Add used language to `--preproc-resolve` output (#5795). [Kamil Rakoczy, Antmicro Ltd.] diff --git a/bin/verilator b/bin/verilator index f0a9af485..ac93e6e50 100755 --- a/bin/verilator +++ b/bin/verilator @@ -473,7 +473,7 @@ detailed descriptions of these arguments. --timescale-override Overrides all timescales --top Alias of --top-module --top-module Name of top-level input module - --trace Enable waveform creation + --trace Enable VCD waveform creation --trace-coverage Enable tracing of coverage --trace-depth Depth of tracing --trace-fst Enable FST waveform creation @@ -483,6 +483,7 @@ detailed descriptions of these arguments. --trace-saif Enable SAIF file creation --trace-structs Enable tracing structure names --trace-threads Enable FST waveform creation on separate threads + --trace-vcd Enable VCD waveform creation --no-trace-top Do not emit traces for signals in the top module generated by verilator --trace-underscore Enable tracing of _signals -U Undefine preprocessor define diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 19e5df650..7e1af30fb 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1493,7 +1493,7 @@ Summary: but may run in a multithreaded environment. With "--threads N", where N >= 2, the model is generated to run multithreaded on up to N threads. See :ref:`Multithreading`. This option also applies to - :vlopt:`--trace` (but not :vlopt:`--trace-fst`). + :vlopt:`--trace-vcd` (but not :vlopt:`--trace-fst`). .. option:: --no-threads @@ -1574,26 +1574,19 @@ Summary: .. option:: --trace - Adds waveform tracing code to the model using VCD format. This overrides - :vlopt:`--trace-fst`. + Deprecated; use :vlopt:`--trace-fst`, :vlopt:`--trace-saif` or + :vlopt:`--trace-vcd` instead. - Verilator will generate additional :file:`__Trace*.cpp` files - must be compiled. In addition :file:`verilated_vcd_sc.cpp` - (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be - compiled and linked in. If using the Verilator-generated Makefiles, - these files will be added to the source file lists for you. If you are - not using the Verilator Makefiles, you will need to add these to your - Makefile manually. + Using :vlopt:`--trace` without :vlopt:`--trace-fst` nor + :vlopt:`--trace-fst` requests VCD traces. - Having tracing compiled in may result in small performance losses, - even when tracing is not turned on during model execution. + Using :vlopt:`--trace` :vlopt:`--trace-fst` requests FST traces. - When using :vlopt:`--threads`, VCD tracing is parallelized, using the - same number of threads as passed to :vlopt:`--threads`. + Using :vlopt:`--trace` :vlopt:`--trace-saif` requests SAIF traces. .. option:: --trace-coverage - With :vlopt:`--trace` and ``--coverage-*``, enable tracing to include a + With `--trace-*` and ``--coverage-*``, enable tracing to include a traced signal for every :vlopt:`--coverage-line` or :vlopt:`--coverage-user`\ -inserted coverage point, to assist in debugging coverage items. Note :vlopt:`--coverage-toggle` does not get @@ -1673,6 +1666,24 @@ Summary: underscore. Otherwise, these signals are not output during tracing. See also :vlopt:`--coverage-underscore` option. +.. option:: --trace-vcd + + Adds waveform tracing code to the model using VCD format. + + Verilator will generate additional :file:`__Trace*.cpp` files + must be compiled. In addition :file:`verilated_vcd_sc.cpp` + (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be + compiled and linked in. If using the Verilator-generated Makefiles, + these files will be added to the source file lists for you. If you are + not using the Verilator Makefiles, you will need to add these to your + Makefile manually. + + Having tracing compiled in may result in small performance losses, + even when tracing is not turned on during model execution. + + When using :vlopt:`--threads`, VCD tracing is parallelized, using the + same number of threads as passed to :vlopt:`--threads`. + .. option:: -U Undefines the given preprocessor symbol. diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index d5eebc31f..31f65678a 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -619,7 +619,7 @@ or "`ifdef`"'s may break other tools. Attached to a DPI import to indicate that function should be called when initializing tracing. This attribute is indented only to be used internally in code that Verilator generates when :vlopt:`--lib-create` - or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`. + or :vlopt:`--hierarchical` is used along with :vlopt:`--trace-vcd`. .. option:: /*verilator&32;tracing_off*/ diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 10a5cbde7..d88220f9e 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -128,7 +128,7 @@ How do I generate waveforms (traces) in C++? See also the next question for tracing in SystemC mode. -A. Pass the :vlopt:`--trace` option to Verilator. Then you may use ``$dumpfile`` and +A. Pass the :vlopt:`--trace-vcd` option to Verilator. Then you may use ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any Verilog simulator, although Verilator ignores the arguments to ``$dumpvars``. See ``examples/make_tracing_c`` in the distribution. @@ -177,7 +177,7 @@ file. How do I generate waveforms (traces) in SystemC? """""""""""""""""""""""""""""""""""""""""""""""" -A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level +A. Pass the :vlopt:`--trace-vcd` option to Verilator, and in your top-level :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`. Then you may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as with any Verilog simulator; see the non-SystemC example in diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 9eab365b8..928ade947 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -65,9 +65,9 @@ For --cc/--sc, it creates: * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp - Infrequent cold routines (hashed to reduce build times) * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp - - Wave file generation code (from --trace) + - Wave file generation code (from --trace-*) * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp - - Wave file generation code (from --trace) + - Wave file generation code (from --trace-*) * - *{prefix}*\ __Dpi.h - DPI import and export declarations (from --dpi) * - *{prefix}*\ __Dpi.cpp diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index 4c8d3a022..a64ff1428 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -488,7 +488,7 @@ $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $dump/$dumpports and related $dumpfile or $dumpports will create a VCD or FST file (based on - the :vlopt:`--trace` option given when the model was Verilated). This + the :vlopt:`--trace-vcd` option given when the model was Verilated). This will take effect starting at the next eval() call. If you have multiple Verilated designs under the same C model, this will dump signals only from the design containing the $dumpvars. diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index 96fce9057..30b9b003e 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -221,7 +221,7 @@ model, it may be beneficial to performance to adjust the influences the partitioning of the model by adjusting the assumed execution time of DPI imports. -When using :vlopt:`--trace` to perform VCD tracing, the VCD trace +When using :vlopt:`--trace-vcd` to perform VCD tracing, the VCD trace construction is parallelized using the same number of threads as specified with :vlopt:`--threads`, and is executed on the same thread pool as the model. @@ -293,8 +293,8 @@ and must be called only by the eval thread. If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore, the eval thread and main thread must be the same. -If using :vlopt:`--trace`, the tracing classes must be constructed and -called from the main thread. +If using :vlopt:`--trace-vcd` or other trace options, the tracing classes +must be constructed and called from the main thread. If using :vlopt:`--vpi`, since SystemVerilog VPI was not architected by IEEE to be multithreaded, Verilator requires all VPI calls are only made @@ -457,8 +457,7 @@ SystemC include directories and link to the SystemC libraries. .. describe:: TRACE - Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS - --trace". + Deprecated. Same as TRACE_VCD, which should be used instead. .. describe:: TRACE_FST @@ -470,6 +469,11 @@ SystemC include directories and link to the SystemC libraries. Optional. Enables SAIF tracing if present, equivalent to "VERILATOR_ARGS --trace-saif". +.. describe:: TRACE_VCD + + Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS + --trace-vcd". + .. describe:: VERILATOR_ARGS Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir` diff --git a/examples/make_protect_lib/Makefile b/examples/make_protect_lib/Makefile index 359ece33e..5628db9c6 100644 --- a/examples/make_protect_lib/Makefile +++ b/examples/make_protect_lib/Makefile @@ -43,7 +43,7 @@ VERILATOR_FLAGS += -Wall VERILATOR_FLAGS += -CFLAGS -DVL_TIME_CONTEXT # Make waveforms -TOP_VERILATOR_FLAGS = $(VERILATOR_FLAGS) --trace +TOP_VERILATOR_FLAGS = $(VERILATOR_FLAGS) --trace-vcd ###################################################################### default: run diff --git a/examples/make_tracing_c/Makefile b/examples/make_tracing_c/Makefile index e7dcaf244..060c4fa39 100644 --- a/examples/make_tracing_c/Makefile +++ b/examples/make_tracing_c/Makefile @@ -40,7 +40,7 @@ VERILATOR_FLAGS += -x-assign fast # Warn abount lint issues; may not want this on less solid designs VERILATOR_FLAGS += -Wall # Make waveforms -VERILATOR_FLAGS += --trace +VERILATOR_FLAGS += --trace-vcd # Check SystemVerilog assertions VERILATOR_FLAGS += --assert # Generate coverage analysis diff --git a/examples/make_tracing_sc/Makefile b/examples/make_tracing_sc/Makefile index cf61c8b7a..b7b312d94 100644 --- a/examples/make_tracing_sc/Makefile +++ b/examples/make_tracing_sc/Makefile @@ -41,7 +41,7 @@ VERILATOR_FLAGS += -x-assign fast # Warn abount lint issues; may not want this on less solid designs VERILATOR_FLAGS += -Wall # Make waveforms -VERILATOR_FLAGS += --trace +VERILATOR_FLAGS += --trace-vcd # Check SystemVerilog assertions VERILATOR_FLAGS += --assert # Generate coverage analysis diff --git a/include/verilated.cpp b/include/verilated.cpp index d42cc43d6..3f9992222 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -3038,7 +3038,7 @@ void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) if (m_ns.m_traceBaseModelCbs.empty()) VL_FATAL_MT("", 0, "", "Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated" - " with --trace or --trace-vcd option"); + " with --trace-fst or --trace-vcd option"); for (auto& cbr : m_ns.m_traceBaseModelCbs) cbr(tfp, levels, options); } void VerilatedContext::traceBaseModelCbAdd(traceBaseModelCb_t cb) VL_MT_SAFE { diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index 22c96b626..4748d1bf2 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -15,9 +15,9 @@ /// \brief Verilated C++ tracing in SAIF format implementation code /// /// This file must be compiled and linked against all Verilated objects -/// that use --trace. +/// that use --trace-saif. /// -/// Use "verilator --trace" to add this to the Makefile for the linker. +/// Use "verilator --trace-saif" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 0a523ac0d..be44e1753 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -15,9 +15,9 @@ /// \brief Verilated C++ tracing in VCD format implementation code /// /// This file must be compiled and linked against all Verilated objects -/// that use --trace. +/// that use --trace-vcd. /// -/// Use "verilator --trace" to add this to the Makefile for the linker. +/// Use "verilator --trace-vcd" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index 182406281..d8a594ef8 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -110,15 +110,15 @@ class CMakeEmitter final { cmake_set_raw(*of, name + "_TIMING", v3Global.usesTiming() ? "1" : "0"); *of << "# Threaded output mode? 1/N threads (from --threads)\n"; cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads())); - *of << "# VCD Tracing output mode? 0/1 (from --trace)\n"; - cmake_set_raw(*of, name + "_TRACE_VCD", - (v3Global.opt.trace() && v3Global.opt.traceFormat().vcd()) ? "1" : "0"); *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n"; cmake_set_raw(*of, name + "_TRACE_FST", (v3Global.opt.trace() && v3Global.opt.traceFormat().fst()) ? "1" : "0"); *of << "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n"; cmake_set_raw(*of, name + "_TRACE_SAIF", (v3Global.opt.trace() && v3Global.opt.traceFormat().saif()) ? "1" : "0"); + *of << "# VCD Tracing output mode? 0/1 (from --trace-vcd)\n"; + cmake_set_raw(*of, name + "_TRACE_VCD", + (v3Global.opt.trace() && v3Global.opt.traceFormat().vcd()) ? "1" : "0"); *of << "\n### Sources...\n"; std::vector classes_fast; diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index 41c1574c7..60de32beb 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -584,7 +584,7 @@ class EmitCModel final : public EmitCFunc { puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName() + "::trace()' called on non-" + v3Global.opt.traceClassBase() + "C object;\"\n" + "\" use --trace-fst with VerilatedFst object," - + " and --trace with VerilatedVcd object\");\n"); + + " and --trace-vcd with VerilatedVcd object\");\n"); puts(/**/ "}\n"); puts(/**/ "stfp->spTrace()->addModel(this);\n"); puts(/**/ "stfp->spTrace()->addInitCb(&" + protect("trace_init") diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 0234bd3a4..54e1ef016 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -551,14 +551,10 @@ public: of.puts("VM_PARALLEL_BUILDS = "); of.puts(v3Global.useParallelBuild() ? "1" : "0"); of.puts("\n"); - of.puts("# Tracing output mode? 0/1 (from --trace/--trace-fst/--trace-saif)\n"); + of.puts("# Tracing output mode? 0/1 (from --trace-fst/--trace-saif/--trace-vcd)\n"); of.puts("VM_TRACE = "); of.puts(v3Global.opt.trace() ? "1" : "0"); of.puts("\n"); - of.puts("# Tracing output mode in VCD format? 0/1 (from --trace)\n"); - of.puts("VM_TRACE_VCD = "); - of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().vcd() ? "1" : "0"); - of.puts("\n"); of.puts("# Tracing output mode in FST format? 0/1 (from --trace-fst)\n"); of.puts("VM_TRACE_FST = "); of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().fst() ? "1" : "0"); @@ -567,6 +563,10 @@ public: of.puts("VM_TRACE_SAIF = "); of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().saif() ? "1" : "0"); of.puts("\n"); + of.puts("# Tracing output mode in VCD format? 0/1 (from --trace-vcd)\n"); + of.puts("VM_TRACE_VCD = "); + of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().vcd() ? "1" : "0"); + of.puts("\n"); of.puts("\n### Object file lists...\n"); for (int support = 0; support < 3; ++support) { diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 7f5af8b07..25f612395 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -930,7 +930,7 @@ void V3Options::notify() VL_MT_DISABLED { } if (trace()) { - // With --trace, --trace-threads is ignored + // With --trace-vcd, --trace-threads is ignored if (traceFormat().vcd()) m_traceThreads = 1; } @@ -1671,6 +1671,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }); DECL_OPTION("-no-trace-top", Set, &m_noTraceTop); DECL_OPTION("-trace-underscore", OnOff, &m_traceUnderscore); + DECL_OPTION("-trace-vcd", CbCall, [this]() { + m_trace = true; + m_traceFormat = TraceFormat::VCD; + }); DECL_OPTION("-U", CbPartialMatch, &V3PreShell::undef); DECL_OPTION("-underline-zero", OnOff, &m_underlineZero); // Deprecated diff --git a/test_regress/driver.py b/test_regress/driver.py index 62c72d735..8a95a7d2e 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -1036,7 +1036,7 @@ class VlTest: if Args.rr: verilator_flags += ["--rr"] if Args.trace: - verilator_flags += ["--trace"] + verilator_flags += ["--trace-vcd"] if Args.gdbsim or Args.rrsim: verilator_flags += ["-CFLAGS -ggdb -LDFLAGS -ggdb"] verilator_flags += ["--x-assign unique"] # More likely to be buggy diff --git a/test_regress/t/t_a1_first_cc.py b/test_regress/t/t_a1_first_cc.py index fd253303d..b56027489 100755 --- a/test_regress/t/t_a1_first_cc.py +++ b/test_regress/t/t_a1_first_cc.py @@ -26,7 +26,7 @@ test.run( ], verilator_run=True) -test.compile(verilator_flags2=[DEBUG_QUIET, "--trace"]) +test.compile(verilator_flags2=[DEBUG_QUIET, "--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_a2_first_sc.py b/test_regress/t/t_a2_first_sc.py index f8123f6db..b970d2fbc 100755 --- a/test_regress/t/t_a2_first_sc.py +++ b/test_regress/t/t_a2_first_sc.py @@ -18,7 +18,7 @@ test.top_filename = "t/t_a1_first_cc.v" DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" -test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace"]) +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace-vcd"]) test.execute() diff --git a/test_regress/t/t_case_incrdecr.py b/test_regress/t/t_case_incrdecr.py index 30ddf27c9..ca7e7f331 100755 --- a/test_regress/t/t_case_incrdecr.py +++ b/test_regress/t/t_case_incrdecr.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--trace --fno-split -x-assign 0"]) +test.compile(verilator_flags2=["--trace-vcd --fno-split -x-assign 0"]) test.execute() diff --git a/test_regress/t/t_ccache_report.py b/test_regress/t/t_ccache_report.py index 56d6a44af..40d5882b9 100755 --- a/test_regress/t/t_ccache_report.py +++ b/test_regress/t/t_ccache_report.py @@ -19,7 +19,7 @@ if not test.cfg_with_ccache: for filename in glob.glob(test.obj_dir + "/*.o"): test.unlink_ok(filename) -test.compile(verilator_flags2=['--trace'], make_flags=["ccache-report"]) +test.compile(verilator_flags2=['--trace-vcd'], make_flags=["ccache-report"]) report = test.obj_dir + "/" + test.vm_prefix + "__ccache_report.txt" diff --git a/test_regress/t/t_clocker.py b/test_regress/t/t_clocker.py index b03987abd..dbb378eea 100755 --- a/test_regress/t/t_clocker.py +++ b/test_regress/t/t_clocker.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--trace"]) +test.compile(verilator_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_cover_expr_trace.py b/test_regress/t/t_cover_expr_trace.py index c1fd9df23..5ea8ada9f 100755 --- a/test_regress/t/t_cover_expr_trace.py +++ b/test_regress/t/t_cover_expr_trace.py @@ -13,7 +13,7 @@ from pathlib import Path test.scenarios('simulator') test.top_filename = "t/t_cover_expr.v" -test.compile(verilator_flags2=['--cc', '--coverage-expr', '--trace']) +test.compile(verilator_flags2=['--cc', '--coverage-expr', '--trace-vcd']) test.execute() diff --git a/test_regress/t/t_cover_line_trace.py b/test_regress/t/t_cover_line_trace.py index 3a2fb4784..728e5d901 100755 --- a/test_regress/t/t_cover_line_trace.py +++ b/test_regress/t/t_cover_line_trace.py @@ -12,7 +12,8 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_line.v" -test.compile(verilator_flags2=['--cc --coverage-line --trace --trace-coverage +define+ATTRIBUTE']) +test.compile( + verilator_flags2=['--cc --coverage-line --trace-vcd --trace-coverage +define+ATTRIBUTE']) test.execute() diff --git a/test_regress/t/t_cover_sva_trace.py b/test_regress/t/t_cover_sva_trace.py index 5e5c25fdb..0cab5f4fe 100755 --- a/test_regress/t/t_cover_sva_trace.py +++ b/test_regress/t/t_cover_sva_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cover_sva_notflat.v" -test.compile(verilator_flags2=['--assert --cc --coverage-user --trace --trace-coverage']) +test.compile(verilator_flags2=['--assert --cc --coverage-user --trace-vcd --trace-coverage']) test.execute() diff --git a/test_regress/t/t_cover_trace_always.py b/test_regress/t/t_cover_trace_always.py index cdad47f3a..6d1e7aa98 100755 --- a/test_regress/t/t_cover_trace_always.py +++ b/test_regress/t/t_cover_trace_always.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--binary --coverage --trace-coverage --trace']) +test.compile(verilator_flags2=['--binary --coverage --trace-coverage --trace-vcd']) test.execute(all_run_flags=["+verilator+coverage+file+" + test.obj_dir + "/coverage_renamed.dat"]) diff --git a/test_regress/t/t_cxx_equal_to.py b/test_regress/t/t_cxx_equal_to.py index cd346b532..0fb95e6fc 100755 --- a/test_regress/t/t_cxx_equal_to.py +++ b/test_regress/t/t_cxx_equal_to.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_cxx_equal_to.v" -test.compile(verilator_flags2=['--binary --trace']) +test.compile(verilator_flags2=['--binary --trace-vcd']) test.execute() diff --git a/test_regress/t/t_debug_trace.py b/test_regress/t/t_debug_trace.py index ecf01e167..fddb42972 100755 --- a/test_regress/t/t_debug_trace.py +++ b/test_regress/t/t_debug_trace.py @@ -13,6 +13,6 @@ test.scenarios('vlt') test.compile( # Check we can call dump() on graph, and other things - v_flags=["--trace --debug --debugi 0 --debugi-V3Trace 9"]) + v_flags=["--trace-vcd --debug --debugi 0 --debugi-V3Trace 9"]) test.passes() diff --git a/test_regress/t/t_flag_build.py b/test_regress/t/t_flag_build.py index e7603f123..6eff8cf80 100755 --- a/test_regress/t/t_flag_build.py +++ b/test_regress/t/t_flag_build.py @@ -14,7 +14,7 @@ test.top_filename = "t/t_flag_make_cmake.v" test.compile( # Don't call cmake nor gmake from driver.py verilator_flags2=[ - '--exe --cc --build -j 2', '../' + test.main_filename, '-MAKEFLAGS -p --trace' + '--exe --cc --build -j 2', '../' + test.main_filename, '-MAKEFLAGS -p --trace-vcd' ]) test.execute() diff --git a/test_regress/t/t_flag_csplit.py b/test_regress/t/t_flag_csplit.py index d05df9e3c..a63e3ac2a 100755 --- a/test_regress/t/t_flag_csplit.py +++ b/test_regress/t/t_flag_csplit.py @@ -80,7 +80,7 @@ def check_gcc_flags(filename): if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") -test.compile(v_flags2=["--trace", +test.compile(v_flags2=["--trace-vcd", "--output-split 1", "--output-split-cfuncs 1", "--exe", diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py index 0b96a05e8..3f259b08b 100755 --- a/test_regress/t/t_flag_csplit_groups.py +++ b/test_regress/t/t_flag_csplit_groups.py @@ -82,7 +82,7 @@ def check_gcc_flags(filename): if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") -test.compile(v_flags2=["--trace", +test.compile(v_flags2=["--trace-vcd", "--output-split 1", "--output-groups 2", "--output-split-cfuncs 1", diff --git a/test_regress/t/t_flag_csplit_off.py b/test_regress/t/t_flag_csplit_off.py index bdad4a618..0afb8c7c0 100755 --- a/test_regress/t/t_flag_csplit_off.py +++ b/test_regress/t/t_flag_csplit_off.py @@ -42,7 +42,7 @@ def check_gcc_flags(filename): if not test.make_version or float(test.make_version) < 4.1: test.skip("Test requires GNU Make version >= 4.1") -test.compile(v_flags2=["--trace --output-split 0 --exe ../" + test.main_filename], +test.compile(v_flags2=["--trace-vcd --output-split 0 --exe ../" + test.main_filename], verilator_make_gmake=False) # We don't use the standard test_regress rules, as want to test the rules diff --git a/test_regress/t/t_force_release_net_trace.py b/test_regress/t/t_force_release_net_trace.py index 721b7b0e4..5e40d1a78 100755 --- a/test_regress/t/t_force_release_net_trace.py +++ b/test_regress/t/t_force_release_net_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_net.v" -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() diff --git a/test_regress/t/t_force_release_var_trace.py b/test_regress/t/t_force_release_var_trace.py index d8f366168..e58afb2bb 100755 --- a/test_regress/t/t_force_release_var_trace.py +++ b/test_regress/t/t_force_release_var_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_force_release_var.v" -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() diff --git a/test_regress/t/t_forceable_net_cmt_trace.py b/test_regress/t/t_forceable_net_cmt_trace.py index bed940206..1c67a9f77 100755 --- a/test_regress/t/t_forceable_net_cmt_trace.py +++ b/test_regress/t/t_forceable_net_cmt_trace.py @@ -16,7 +16,7 @@ test.golden_filename = "t/t_forceable_net_trace.vcd" test.compile(make_top_shell=False, make_main=False, - verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) test.execute() diff --git a/test_regress/t/t_forceable_net_vlt_trace.py b/test_regress/t/t_forceable_net_vlt_trace.py index 59b55a74e..dfb289e37 100755 --- a/test_regress/t/t_forceable_net_vlt_trace.py +++ b/test_regress/t/t_forceable_net_vlt_trace.py @@ -14,10 +14,11 @@ test.pli_filename = "t/t_forceable_net.cpp" test.top_filename = "t/t_forceable_net.v" test.golden_filename = "t/t_forceable_net_trace.vcd" -test.compile( - make_top_shell=False, - make_main=False, - verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_net.vlt"]) +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + '--exe', '--trace-vcd', test.pli_filename, test.t_dir + "/t_forceable_net.vlt" + ]) test.execute() diff --git a/test_regress/t/t_forceable_var_cmt_trace.py b/test_regress/t/t_forceable_var_cmt_trace.py index a59d2e6c5..2903764cf 100755 --- a/test_regress/t/t_forceable_var_cmt_trace.py +++ b/test_regress/t/t_forceable_var_cmt_trace.py @@ -16,7 +16,7 @@ test.golden_filename = "t/t_forceable_var_trace.vcd" test.compile(make_top_shell=False, make_main=False, - verilator_flags2=['-DCMT=1', '--exe', '--trace', test.pli_filename]) + verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) test.execute() diff --git a/test_regress/t/t_forceable_var_vlt_trace.py b/test_regress/t/t_forceable_var_vlt_trace.py index fad62ca60..65a829dbe 100755 --- a/test_regress/t/t_forceable_var_vlt_trace.py +++ b/test_regress/t/t_forceable_var_vlt_trace.py @@ -14,10 +14,11 @@ test.pli_filename = "t/t_forceable_var.cpp" test.top_filename = "t/t_forceable_var.v" test.golden_filename = "t/t_forceable_var_trace.vcd" -test.compile( - make_top_shell=False, - make_main=False, - verilator_flags2=['--exe', '--trace', test.pli_filename, test.t_dir + "/t_forceable_var.vlt"]) +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=[ + '--exe', '--trace-vcd', test.pli_filename, test.t_dir + "/t_forceable_var.vlt" + ]) test.execute() diff --git a/test_regress/t/t_func_public_trace.py b/test_regress/t/t_func_public_trace.py index 296e9f1cf..e7cacfb8f 100755 --- a/test_regress/t/t_func_public_trace.py +++ b/test_regress/t/t_func_public_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_func_public.v" -test.compile(verilator_flags2=["--trace"]) +test.compile(verilator_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_func_while.py b/test_regress/t/t_func_while.py index 320934d1d..6827b0e69 100755 --- a/test_regress/t/t_func_while.py +++ b/test_regress/t/t_func_while.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--trace"]) +test.compile(verilator_flags2=["--trace-vcd"]) test.passes() diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.py b/test_regress/t/t_hier_block_sc_trace_vcd.py index a2b2d0353..dff5601e7 100755 --- a/test_regress/t/t_hier_block_sc_trace_vcd.py +++ b/test_regress/t/t_hier_block_sc_trace_vcd.py @@ -22,7 +22,7 @@ test.clean_objs() test.compile(v_flags2=['t/t_hier_block.cpp'], verilator_flags2=[ '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"', - "--CFLAGS", '"-O0 -ggdb"', "--trace" + "--CFLAGS", '"-O0 -ggdb"', "--trace-vcd" ], threads=(6 if test.vltmt else 1)) diff --git a/test_regress/t/t_hier_block_trace_vcd.py b/test_regress/t/t_hier_block_trace_vcd.py index 8952878f4..7bffe147f 100755 --- a/test_regress/t/t_hier_block_trace_vcd.py +++ b/test_regress/t/t_hier_block_trace_vcd.py @@ -21,7 +21,7 @@ test.compile( verilator_flags2=[ '--hierarchical', '--Wno-TIMESCALEMOD', - '--trace', + '--trace-vcd', '--no-trace-underscore', # To avoid handle mismatches ], threads=(6 if test.vltmt else 1)) diff --git a/test_regress/t/t_hier_trace.py b/test_regress/t/t_hier_trace.py index 4da2102bc..4562d5688 100755 --- a/test_regress/t/t_hier_trace.py +++ b/test_regress/t/t_hier_trace.py @@ -12,8 +12,8 @@ import vltest_bootstrap test.scenarios('simulator') test.compile(verilator_flags2=[ - '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', - '-F t/t_hier_trace_sub/top.F' + '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', + '--hierarchical', '-F t/t_hier_trace_sub/top.F' ]) test.execute(all_run_flags=['-j 4']) diff --git a/test_regress/t/t_hier_trace_noinl.py b/test_regress/t/t_hier_trace_noinl.py index 890644b91..21c479ec2 100755 --- a/test_regress/t/t_hier_trace_noinl.py +++ b/test_regress/t/t_hier_trace_noinl.py @@ -13,8 +13,8 @@ test.scenarios('simulator') test.top_filename = "t/t_hier_trace.v" test.compile(verilator_flags2=[ - '--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical', - '--fno-inline', '-F t/t_hier_trace_sub/top.F' + '--trace-vcd', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', + '--hierarchical', '--fno-inline', '-F t/t_hier_trace_sub/top.F' ]) test.execute(all_run_flags=['-j 4']) diff --git a/test_regress/t/t_interface1_modport_trace.py b/test_regress/t/t_interface1_modport_trace.py index c16b2aa0e..e8d6f2272 100755 --- a/test_regress/t/t_interface1_modport_trace.py +++ b/test_regress/t/t_interface1_modport_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_interface1_modport.v" -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() diff --git a/test_regress/t/t_interface_ref_trace.py b/test_regress/t/t_interface_ref_trace.py index b62c5c728..b9b76c6e4 100755 --- a/test_regress/t/t_interface_ref_trace.py +++ b/test_regress/t/t_interface_ref_trace.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--trace-structs --trace']) +test.compile(verilator_flags2=['--trace-structs --trace-vcd']) test.execute() diff --git a/test_regress/t/t_interface_ref_trace_inla.py b/test_regress/t/t_interface_ref_trace_inla.py index cef0f6ce1..0ef92f346 100755 --- a/test_regress/t/t_interface_ref_trace_inla.py +++ b/test_regress/t/t_interface_ref_trace_inla.py @@ -13,7 +13,7 @@ test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" -test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace']) +test.compile(v_flags2=['+define+NO_INLINE_A'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() diff --git a/test_regress/t/t_interface_ref_trace_inlab.py b/test_regress/t/t_interface_ref_trace_inlab.py index b0eece321..e9db453ac 100755 --- a/test_regress/t/t_interface_ref_trace_inlab.py +++ b/test_regress/t/t_interface_ref_trace_inlab.py @@ -14,7 +14,7 @@ test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" test.compile(v_flags2=['+define+NO_INLINE_A +define+NO_INLINE_B'], - verilator_flags2=['--trace-structs --trace']) + verilator_flags2=['--trace-structs --trace-vcd']) test.execute() diff --git a/test_regress/t/t_interface_ref_trace_inlb.py b/test_regress/t/t_interface_ref_trace_inlb.py index 946cc2ece..48d3a1ba3 100755 --- a/test_regress/t/t_interface_ref_trace_inlb.py +++ b/test_regress/t/t_interface_ref_trace_inlb.py @@ -13,7 +13,7 @@ test.scenarios('simulator') test.top_filename = "t/t_interface_ref_trace.v" test.golden_filename = "t/t_interface_ref_trace.out" -test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace']) +test.compile(v_flags2=['+define+NO_INLINE_B'], verilator_flags2=['--trace-structs --trace-vcd']) test.execute() diff --git a/test_regress/t/t_interface_ref_trace_noinl.py b/test_regress/t/t_interface_ref_trace_noinl.py index aff9b32b8..81fca1242 100755 --- a/test_regress/t/t_interface_ref_trace_noinl.py +++ b/test_regress/t/t_interface_ref_trace_noinl.py @@ -15,7 +15,7 @@ test.top_filename = "t/t_interface_ref_trace.v" # in a different order. Sadly vcddiff can't check equivalence # test.golden_filename = "t/t_interface_ref_trace.out" -test.compile(verilator_flags2=['-fno-inline --trace-structs --trace']) +test.compile(verilator_flags2=['-fno-inline --trace-structs --trace-vcd']) test.execute() diff --git a/test_regress/t/t_lint_subout_bad.py b/test_regress/t/t_lint_subout_bad.py index 2ea3b149a..8ddea4fed 100755 --- a/test_regress/t/t_lint_subout_bad.py +++ b/test_regress/t/t_lint_subout_bad.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.compile( # No --lint-only as got compile error - verilator_flags2=["--trace"], + verilator_flags2=["--trace-vcd"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_mem_multi_io.py b/test_regress/t/t_mem_multi_io.py index 7b164ec7b..ca839f8e4 100755 --- a/test_regress/t/t_mem_multi_io.py +++ b/test_regress/t/t_mem_multi_io.py @@ -13,7 +13,7 @@ test.scenarios('simulator') test.compile( # Disable inlining, this test is trivial without it - verilator_flags2=["-fno-inline --trace"], + verilator_flags2=["-fno-inline --trace-vcd"], verilator_flags3=[]) test.execute() diff --git a/test_regress/t/t_mem_multidim_trace.py b/test_regress/t/t_mem_multidim_trace.py index 8ac322e79..b59d45ff6 100755 --- a/test_regress/t/t_mem_multidim_trace.py +++ b/test_regress/t/t_mem_multidim_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_mem_multidim.v" -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_mem_trace_split.py b/test_regress/t/t_mem_trace_split.py index ec8e60aae..14fc22b86 100755 --- a/test_regress/t/t_mem_trace_split.py +++ b/test_regress/t/t_mem_trace_split.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--trace", "--trace-structs", "--output-split-ctrace", "32"]) +test.compile(verilator_flags2=["--trace-vcd", "--trace-structs", "--output-split-ctrace", "32"]) if test.vlt_all: test.file_grep_count(test.obj_dir + "/V" + test.name + "__Trace__0.cpp", diff --git a/test_regress/t/t_no_trace_top.py b/test_regress/t/t_no_trace_top.py index 06f1eac14..3a550f86d 100755 --- a/test_regress/t/t_no_trace_top.py +++ b/test_regress/t/t_no_trace_top.py @@ -14,7 +14,7 @@ test.top_filename = "t_trace_cat.v" test.compile(make_top_shell=False, make_main=False, - v_flags2=["--trace --no-trace-top --exe", test.pli_filename]) + v_flags2=["--trace-vcd --no-trace-top --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_opt_const_cov.py b/test_regress/t/t_opt_const_cov.py index 147adc0df..862db88cc 100755 --- a/test_regress/t/t_opt_const_cov.py +++ b/test_regress/t/t_opt_const_cov.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace"]) +test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", "--coverage", "--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_order_clkinst.py b/test_regress/t/t_order_clkinst.py index 7b88a42a2..3f7b706e5 100755 --- a/test_regress/t/t_order_clkinst.py +++ b/test_regress/t/t_order_clkinst.py @@ -17,7 +17,7 @@ test.scenarios('simulator') # closely enough to pass the same test? # If not -- probably we should switch this to be vlt-only. -test.compile(verilator_flags2=["--trace"]) +test.compile(verilator_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_order_multidriven.py b/test_regress/t/t_order_multidriven.py index ec6142999..202e6a897 100755 --- a/test_regress/t/t_order_multidriven.py +++ b/test_regress/t/t_order_multidriven.py @@ -11,7 +11,9 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_param_type_bad.py b/test_regress/t/t_param_type_bad.py index 13aced9dc..45bc705e4 100755 --- a/test_regress/t/t_param_type_bad.py +++ b/test_regress/t/t_param_type_bad.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.lint( # Bug1575 required trace to crash - verilator_flags2=["--trace"], + verilator_flags2=["--trace-vcd"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_param_type_bad2.py b/test_regress/t/t_param_type_bad2.py index dd2d92256..95efb5b13 100755 --- a/test_regress/t/t_param_type_bad2.py +++ b/test_regress/t/t_param_type_bad2.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.lint( # Bug1575 required trace to crash - verilator_flags2=["--trace --cc"], + verilator_flags2=["--trace-vcd --cc"], fails=True, expect_filename=test.golden_filename) diff --git a/test_regress/t/t_protect_ids.py b/test_regress/t/t_protect_ids.py index 1c610fc8e..46de898d8 100755 --- a/test_regress/t/t_protect_ids.py +++ b/test_regress/t/t_protect_ids.py @@ -19,7 +19,7 @@ for filename in (glob.glob(test.obj_dir + "/*_PS*.cpp") + glob.glob(test.obj_dir test.unlink_ok(filename) test.compile(verilator_flags2=[ - "--protect-ids", "--protect-key SECRET_KEY", "--trace", "--coverage", "-Wno-INSECURE", + "--protect-ids", "--protect-key SECRET_KEY", "--trace-vcd", "--coverage", "-Wno-INSECURE", "t/t_protect_ids_c.cpp" ]) diff --git a/test_regress/t/t_protect_ids_debug.py b/test_regress/t/t_protect_ids_debug.py index 10b0e15bb..8d66ea5d5 100755 --- a/test_regress/t/t_protect_ids_debug.py +++ b/test_regress/t/t_protect_ids_debug.py @@ -15,7 +15,7 @@ test.top_filename = "t/t_protect_ids.v" test.compile(verilator_flags2=[ "--protect-ids", "--protect-key SECRET_KEY", - "--trace", + "--trace-vcd", "--debug-protect", "--coverage", "-Wno-INSECURE", diff --git a/test_regress/t/t_scope_map.py b/test_regress/t/t_scope_map.py index ec6142999..202e6a897 100755 --- a/test_regress/t/t_scope_map.py +++ b/test_regress/t/t_scope_map.py @@ -11,7 +11,9 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_split_var_2_trace.py b/test_regress/t/t_split_var_2_trace.py index c765a49fa..7a9eac173 100755 --- a/test_regress/t/t_split_var_2_trace.py +++ b/test_regress/t/t_split_var_2_trace.py @@ -15,7 +15,7 @@ test.top_filename = "t/t_split_var_0.v" # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performance, but ok. -test.compile(verilator_flags2=['--cc --trace --stats +define+TEST_ATTRIBUTES'], +test.compile(verilator_flags2=['--cc --trace-vcd --stats +define+TEST_ATTRIBUTES'], threads=(6 if test.vltmt else 1)) test.execute() diff --git a/test_regress/t/t_split_var_types.py b/test_regress/t/t_split_var_types.py index 6c6dd3e23..3fac9c971 100755 --- a/test_regress/t/t_split_var_types.py +++ b/test_regress/t/t_split_var_types.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() test.passes() diff --git a/test_regress/t/t_split_var_types.v b/test_regress/t/t_split_var_types.v index b61923ec0..148c6ae84 100644 --- a/test_regress/t/t_split_var_types.v +++ b/test_regress/t/t_split_var_types.v @@ -20,7 +20,7 @@ module t(/*AUTOARG*/ endmodule -// #5782 internal error with --trace. Bit range is not properly handled. +// #5782 internal error with --trace-vcd. Bit range is not properly handled. module bug5782 ( output logic [31:0][15:0] data_out ); diff --git a/test_regress/t/t_struct_init_trace.py b/test_regress/t/t_struct_init_trace.py index 4ca547717..812fc2737 100755 --- a/test_regress/t/t_struct_init_trace.py +++ b/test_regress/t/t_struct_init_trace.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_struct_init.v" -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_time_vpi_1ms10ns.py b/test_regress/t/t_time_vpi_1ms10ns.py index b7460eb4e..501137c36 100755 --- a/test_regress/t/t_time_vpi_1ms10ns.py +++ b/test_regress/t/t_time_vpi_1ms10ns.py @@ -16,7 +16,7 @@ test.main_time_multiplier = 1e-3 / 10e-9 test.compile( v_flags2=['+define+time_scale_units=1ms +define+time_scale_prec=10ns', test.pli_filename], - verilator_flags2=['--vpi --trace']) + verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_time_vpi_1ns1ns.py b/test_regress/t/t_time_vpi_1ns1ns.py index ac7e49500..8c333e2ec 100755 --- a/test_regress/t/t_time_vpi_1ns1ns.py +++ b/test_regress/t/t_time_vpi_1ns1ns.py @@ -16,7 +16,7 @@ test.main_time_multiplier = 1e-9 / 1e-9 test.compile( v_flags2=['+define+time_scale_units=1ns +define+time_scale_prec=1ns', test.pli_filename], - verilator_flags2=['--vpi --trace']) + verilator_flags2=['--vpi --trace-vcd']) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_timing_osc.py b/test_regress/t/t_timing_osc.py index bc97f4d76..6bff8c8f0 100755 --- a/test_regress/t/t_timing_osc.py +++ b/test_regress/t/t_timing_osc.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--exe --main --timing --trace"], make_main=False) +test.compile(verilator_flags2=["--exe --main --timing --trace-vcd"], make_main=False) test.execute() diff --git a/test_regress/t/t_timing_trace.py b/test_regress/t/t_timing_trace.py index 6a9d5689d..1adbf685b 100755 --- a/test_regress/t/t_timing_trace.py +++ b/test_regress/t/t_timing_trace.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--exe --main --timing --trace -Wno-MINTYPMAXDLY"]) +test.compile(verilator_flags2=["--exe --main --timing --trace-vcd -Wno-MINTYPMAXDLY"]) test.execute() diff --git a/test_regress/t/t_trace_abort.py b/test_regress/t/t_trace_abort.py index ed957bcf9..b1fca5884 100755 --- a/test_regress/t/t_trace_abort.py +++ b/test_regress/t/t_trace_abort.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute(fails=True) diff --git a/test_regress/t/t_trace_array.py b/test_regress/t/t_trace_array.py index e178ccb9b..3bfe43d92 100755 --- a/test_regress/t/t_trace_array.py +++ b/test_regress/t/t_trace_array.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--cc --trace --trace-structs']) +test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs']) test.execute() diff --git a/test_regress/t/t_trace_array_threads_1.py b/test_regress/t/t_trace_array_threads_1.py index 3400f7771..52839b5d9 100755 --- a/test_regress/t/t_trace_array_threads_1.py +++ b/test_regress/t/t_trace_array_threads_1.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.top_filename = "t/t_trace_array.v" test.golden_filename = "t/t_trace_array.out" -test.compile(verilator_flags2=['--cc --trace --trace-threads 1 --trace-structs']) +test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1 --trace-structs']) test.execute() diff --git a/test_regress/t/t_trace_ascendingrange.py b/test_regress/t/t_trace_ascendingrange.py index d90888a48..6d7562957 100755 --- a/test_regress/t/t_trace_ascendingrange.py +++ b/test_regress/t/t_trace_ascendingrange.py @@ -14,7 +14,7 @@ test.scenarios('simulator') # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # Strangely, asking for more threads makes it go away. -test.compile(verilator_flags2=['--cc --trace --trace-params -Wno-ASCRANGE'], +test.compile(verilator_flags2=['--cc --trace-vcd --trace-params -Wno-ASCRANGE'], threads=(6 if test.vltmt else 1)) test.execute() diff --git a/test_regress/t/t_trace_cat.py b/test_regress/t/t_trace_cat.py index 5b89b99fd..28d5fec65 100755 --- a/test_regress/t/t_trace_cat.py +++ b/test_regress/t/t_trace_cat.py @@ -11,7 +11,9 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_cat_renew.py b/test_regress/t/t_trace_cat_renew.py index 99db77d20..8f81fd65e 100755 --- a/test_regress/t/t_trace_cat_renew.py +++ b/test_regress/t/t_trace_cat_renew.py @@ -13,7 +13,9 @@ test.scenarios('vlt_all') test.pli_filename = "t/t_trace_cat.cpp" test.top_filename = "t/t_trace_cat.v" -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_cat_reopen.py b/test_regress/t/t_trace_cat_reopen.py index 99db77d20..8f81fd65e 100755 --- a/test_regress/t/t_trace_cat_reopen.py +++ b/test_regress/t/t_trace_cat_reopen.py @@ -13,7 +13,9 @@ test.scenarios('vlt_all') test.pli_filename = "t/t_trace_cat.cpp" test.top_filename = "t/t_trace_cat.v" -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_class.py b/test_regress/t/t_trace_class.py index c57dc225f..95ad1b66e 100755 --- a/test_regress/t/t_trace_class.py +++ b/test_regress/t/t_trace_class.py @@ -12,8 +12,8 @@ import vltest_bootstrap test.scenarios('vlt') test.compile( - # verilator_flags2 = ['--binary --trace'], - verilator_flags2=['--binary --trace']) + # verilator_flags2 = ['--binary --trace-vcd'], + verilator_flags2=['--binary --trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_complex.py b/test_regress/t/t_trace_complex.py index b7da0f5f5..219c74d41 100755 --- a/test_regress/t/t_trace_complex.py +++ b/test_regress/t/t_trace_complex.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_complex_params.py b/test_regress/t/t_trace_complex_params.py index 566dc8a73..e331a365c 100755 --- a/test_regress/t/t_trace_complex_params.py +++ b/test_regress/t/t_trace_complex_params.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" -test.compile(verilator_flags2=['--cc --trace --no-trace-structs --trace-params']) +test.compile(verilator_flags2=['--cc --trace-vcd --no-trace-structs --trace-params']) test.execute() diff --git a/test_regress/t/t_trace_complex_portable.py b/test_regress/t/t_trace_complex_portable.py index 4e0bdcff1..bd072f3ac 100755 --- a/test_regress/t/t_trace_complex_portable.py +++ b/test_regress/t/t_trace_complex_portable.py @@ -15,7 +15,7 @@ test.scenarios('vlt') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex.out" -test.compile(verilator_flags2=['--cc --trace -CFLAGS -DVL_PORTABLE_ONLY']) +test.compile(verilator_flags2=['--cc --trace-vcd -CFLAGS -DVL_PORTABLE_ONLY']) test.execute() diff --git a/test_regress/t/t_trace_complex_structs.py b/test_regress/t/t_trace_complex_structs.py index 9e8df28e9..cbe5ceb16 100755 --- a/test_regress/t/t_trace_complex_structs.py +++ b/test_regress/t/t_trace_complex_structs.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" -test.compile(verilator_flags2=['--cc --trace --trace-structs --no-trace-params']) +test.compile(verilator_flags2=['--cc --trace-vcd --trace-structs --no-trace-params']) test.execute() diff --git a/test_regress/t/t_trace_complex_threads_1.py b/test_regress/t/t_trace_complex_threads_1.py index bf3e9e999..182da2312 100755 --- a/test_regress/t/t_trace_complex_threads_1.py +++ b/test_regress/t/t_trace_complex_threads_1.py @@ -13,7 +13,7 @@ test.scenarios('simulator') test.top_filename = "t/t_trace_complex.v" test.golden_filename = "t/t_trace_complex.out" -test.compile(verilator_flags2=['--cc --trace --trace-threads 1']) +test.compile(verilator_flags2=['--cc --trace-vcd --trace-threads 1']) test.execute() diff --git a/test_regress/t/t_trace_decoration.py b/test_regress/t/t_trace_decoration.py index 86750fc3c..7f423d2a9 100755 --- a/test_regress/t/t_trace_decoration.py +++ b/test_regress/t/t_trace_decoration.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--cc --trace --no-decoration']) +test.compile(verilator_flags2=['--cc --trace-vcd --no-decoration']) test.execute() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py index 17f76e69b..9f2efb003 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_0.py @@ -13,7 +13,7 @@ test.scenarios('vlt_all') test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" -test.compile(make_main=False, verilator_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py index 9e369b46e..1771ec5e6 100755 --- a/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py +++ b/test_regress/t/t_trace_dumpvars_dyn_vcd_1.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_trace_dumpvars_dyn.cpp" test.top_filename = "t/t_trace_dumpvars_dyn.v" test.compile(make_main=False, - verilator_flags2=["--trace --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) + verilator_flags2=["--trace-vcd --exe", test.pli_filename, "-CFLAGS -DVL_DEBUG"]) test.execute() diff --git a/test_regress/t/t_trace_empty.py b/test_regress/t/t_trace_empty.py index 317f700bc..d9be4bbf9 100755 --- a/test_regress/t/t_trace_empty.py +++ b/test_regress/t/t_trace_empty.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_event.py b/test_regress/t/t_trace_event.py index 215c5d6dc..cc6494c42 100755 --- a/test_regress/t/t_trace_event.py +++ b/test_regress/t/t_trace_event.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--trace --binary']) +test.compile(verilator_flags2=['--trace-vcd --binary']) test.execute() diff --git a/test_regress/t/t_trace_iface.py b/test_regress/t/t_trace_iface.py index de8cf58ff..0f4312521 100755 --- a/test_regress/t/t_trace_iface.py +++ b/test_regress/t/t_trace_iface.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') -test.compile(verilator_flags2=['--trace']) +test.compile(verilator_flags2=['--trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_no_top_name.py b/test_regress/t/t_trace_no_top_name.py index e3e6887f1..ebe166cbc 100755 --- a/test_regress/t/t_trace_no_top_name.py +++ b/test_regress/t/t_trace_no_top_name.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--binary --main-top-name '-' --trace -Wno-MULTITOP"]) +test.compile(verilator_flags2=["--binary --main-top-name '-' --trace-vcd -Wno-MULTITOP"]) test.execute() diff --git a/test_regress/t/t_trace_no_top_name2_vcd.py b/test_regress/t/t_trace_no_top_name2_vcd.py index 06a524d42..77142cc7b 100755 --- a/test_regress/t/t_trace_no_top_name2_vcd.py +++ b/test_regress/t/t_trace_no_top_name2_vcd.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.pli_filename = "t/t_trace_no_top_name2.cpp" test.top_filename = "t/t_trace_no_top_name2.v" -test.compile(make_main=False, verilator_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_main=False, verilator_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_noflag_bad.out b/test_regress/t/t_trace_noflag_bad.out index 6169150e9..9ba8f8632 100644 --- a/test_regress/t/t_trace_noflag_bad.out +++ b/test_regress/t/t_trace_noflag_bad.out @@ -1,2 +1,2 @@ -%Error: Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated with --trace or --trace-vcd option +%Error: Testbench C call to 'VerilatedContext::trace()' requires model(s) Verilated with --trace-fst or --trace-vcd option Aborting... diff --git a/test_regress/t/t_trace_open_wrong_order_bad.py b/test_regress/t/t_trace_open_wrong_order_bad.py index 691cb579b..67239c35d 100755 --- a/test_regress/t/t_trace_open_wrong_order_bad.py +++ b/test_regress/t/t_trace_open_wrong_order_bad.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') -test.compile(verilator_flags2=["--cc --trace --exe", test.pli_filename], +test.compile(verilator_flags2=["--cc --trace-vcd --exe", test.pli_filename], make_top_shell=False, make_main=False) diff --git a/test_regress/t/t_trace_packed_struct.py b/test_regress/t/t_trace_packed_struct.py index 66b2dd8cd..142fd5a91 100755 --- a/test_regress/t/t_trace_packed_struct.py +++ b/test_regress/t/t_trace_packed_struct.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(v_flags2=["--trace"]) +test.compile(v_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_trace_param.py b/test_regress/t/t_trace_param.py index 7ed3e770d..1cdcbdd57 100755 --- a/test_regress/t/t_trace_param.py +++ b/test_regress/t/t_trace_param.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(v_flags2=["--trace"]) +test.compile(v_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_trace_param_override.py b/test_regress/t/t_trace_param_override.py index 928c0acde..2f9c739f3 100755 --- a/test_regress/t/t_trace_param_override.py +++ b/test_regress/t/t_trace_param_override.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=["--exe --main --trace -GPOVERRODE=31"]) +test.compile(verilator_flags2=["--exe --main --trace-vcd -GPOVERRODE=31"]) test.execute() diff --git a/test_regress/t/t_trace_primitive.py b/test_regress/t/t_trace_primitive.py index 7d9702fd0..8ffc1cbfb 100755 --- a/test_regress/t/t_trace_primitive.py +++ b/test_regress/t/t_trace_primitive.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(v_flags2=["--trace"]) +test.compile(v_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_trace_public_func.py b/test_regress/t/t_trace_public_func.py index 415f64bc3..b9350881d 100755 --- a/test_regress/t/t_trace_public_func.py +++ b/test_regress/t/t_trace_public_func.py @@ -15,7 +15,7 @@ test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, - v_flags2=["-DATTRIBUTES -DPUB_FUNC --trace --exe", test.pli_filename]) + v_flags2=["-DATTRIBUTES -DPUB_FUNC --trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_public_func_vlt.py b/test_regress/t/t_trace_public_func_vlt.py index da815dcdd..1b361af85 100755 --- a/test_regress/t/t_trace_public_func_vlt.py +++ b/test_regress/t/t_trace_public_func_vlt.py @@ -17,7 +17,7 @@ test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, v_flags2=[ - "-DPUB_FUNC --trace --exe", test.pli_filename, + "-DPUB_FUNC --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_trace_public_func.vlt" ]) diff --git a/test_regress/t/t_trace_public_sig.py b/test_regress/t/t_trace_public_sig.py index 21f4444c9..4aa00e389 100755 --- a/test_regress/t/t_trace_public_sig.py +++ b/test_regress/t/t_trace_public_sig.py @@ -15,7 +15,7 @@ test.golden_filename = "t/t_trace_public.out" test.compile(make_top_shell=False, make_main=False, - v_flags2=["-DATTRIBUTES --trace --exe", test.pli_filename]) + v_flags2=["-DATTRIBUTES --trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_public_sig_vlt.py b/test_regress/t/t_trace_public_sig_vlt.py index 5cb738257..e0b6c8498 100755 --- a/test_regress/t/t_trace_public_sig_vlt.py +++ b/test_regress/t/t_trace_public_sig_vlt.py @@ -19,7 +19,7 @@ out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(make_top_shell=False, make_main=False, v_flags2=[ - "--trace --exe", test.pli_filename, + "--trace-vcd --exe", test.pli_filename, test.t_dir + "/t_trace_public_sig.vlt --no-json-edit-nums" ]) diff --git a/test_regress/t/t_trace_rollover.py b/test_regress/t/t_trace_rollover.py index 4764e4ba6..299193528 100755 --- a/test_regress/t/t_trace_rollover.py +++ b/test_regress/t/t_trace_rollover.py @@ -12,7 +12,9 @@ import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t_trace_cat.v" -test.compile(make_top_shell=False, make_main=False, v_flags2=["--trace --exe", test.pli_filename]) +test.compile(make_top_shell=False, + make_main=False, + v_flags2=["--trace-vcd --exe", test.pli_filename]) test.execute() diff --git a/test_regress/t/t_trace_sc_empty.py b/test_regress/t/t_trace_sc_empty.py index ae5b13494..0c413116d 100755 --- a/test_regress/t/t_trace_sc_empty.py +++ b/test_regress/t/t_trace_sc_empty.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['-sc', '--trace']) +test.compile(verilator_flags2=['-sc', '--trace-vcd']) test.passes() diff --git a/test_regress/t/t_trace_scope_no_inline.py b/test_regress/t/t_trace_scope_no_inline.py index 0944e381c..dc37817c5 100755 --- a/test_regress/t/t_trace_scope_no_inline.py +++ b/test_regress/t/t_trace_scope_no_inline.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') -test.compile(verilator_flags2=["--cc --trace -fno-inline t/" + test.name + ".vlt"]) +test.compile(verilator_flags2=["--cc --trace-vcd -fno-inline t/" + test.name + ".vlt"]) test.execute() diff --git a/test_regress/t/t_trace_scope_vlt.py b/test_regress/t/t_trace_scope_vlt.py index 7c58f9479..7d91064b2 100755 --- a/test_regress/t/t_trace_scope_vlt.py +++ b/test_regress/t/t_trace_scope_vlt.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_trace_scope_vlt.v" -test.compile(v_flags2=["--trace t/t_trace_scope_vlt.vlt"]) +test.compile(v_flags2=["--trace-vcd t/t_trace_scope_vlt.vlt"]) test.execute() diff --git a/test_regress/t/t_trace_scstruct.py b/test_regress/t/t_trace_scstruct.py index 3dd077924..03ec178a4 100755 --- a/test_regress/t/t_trace_scstruct.py +++ b/test_regress/t/t_trace_scstruct.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--sc --trace --trace-structs --pins-bv 2']) +test.compile(verilator_flags2=['--sc --trace-vcd --trace-structs --pins-bv 2']) #test.execute() # didn't bother with top shell diff --git a/test_regress/t/t_trace_split_cfuncs.py b/test_regress/t/t_trace_split_cfuncs.py index b1b588c76..c2536c656 100755 --- a/test_regress/t/t_trace_split_cfuncs.py +++ b/test_regress/t/t_trace_split_cfuncs.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) +test.compile(v_flags2=["--trace-vcd", "--output-split-cfuncs", "1"]) test.passes() diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.py b/test_regress/t/t_trace_split_cfuncs_dpi_export.py index b1b588c76..c2536c656 100755 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.py +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(v_flags2=["--trace", "--output-split-cfuncs", "1"]) +test.compile(v_flags2=["--trace-vcd", "--output-split-cfuncs", "1"]) test.passes() diff --git a/test_regress/t/t_trace_string.py b/test_regress/t/t_trace_string.py index f9c1f82de..41f81a0a2 100755 --- a/test_regress/t/t_trace_string.py +++ b/test_regress/t/t_trace_string.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_string_fst.py b/test_regress/t/t_trace_string_fst.py index cf926f0d2..32dc6d8d2 100755 --- a/test_regress/t/t_trace_string_fst.py +++ b/test_regress/t/t_trace_string_fst.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_trace_string.v" -test.compile(verilator_flags2=['--cc --trace']) +test.compile(verilator_flags2=['--cc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_string_fst_sc.py b/test_regress/t/t_trace_string_fst_sc.py index dc56e4069..5bc0d3ad4 100755 --- a/test_regress/t/t_trace_string_fst_sc.py +++ b/test_regress/t/t_trace_string_fst_sc.py @@ -15,7 +15,7 @@ test.top_filename = "t/t_trace_string.v" if not test.have_sc: test.skip("No SystemC installed") -test.compile(verilator_flags2=['--sc --trace']) +test.compile(verilator_flags2=['--sc --trace-vcd']) test.execute() diff --git a/test_regress/t/t_trace_timescale.py b/test_regress/t/t_trace_timescale.py index 8c2aacbfb..ce8cf9a96 100755 --- a/test_regress/t/t_trace_timescale.py +++ b/test_regress/t/t_trace_timescale.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('vlt_all') -test.compile(v_flags2=["--trace"]) +test.compile(v_flags2=["--trace-vcd"]) test.execute() diff --git a/test_regress/t/t_trace_timing1.py b/test_regress/t/t_trace_timing1.py index 1ddc50dab..4813384d9 100755 --- a/test_regress/t/t_trace_timing1.py +++ b/test_regress/t/t_trace_timing1.py @@ -15,7 +15,7 @@ test.compile( verilator_flags=[ # Custom as don't want -cc "-Mdir", test.obj_dir, "--debug-check" ], - verilator_flags2=['--binary --trace'], + verilator_flags2=['--binary --trace-vcd'], make_main=False) test.execute() diff --git a/test_regress/t/t_trace_ub_misaligned_address.py b/test_regress/t/t_trace_ub_misaligned_address.py index b86a92b34..8dba84376 100755 --- a/test_regress/t/t_trace_ub_misaligned_address.py +++ b/test_regress/t/t_trace_ub_misaligned_address.py @@ -13,7 +13,7 @@ test.scenarios('simulator') test.top_filename = "t/t_trace_ub_misaligned_address.v" test.compile(verilator_flags2=[ - "--binary --trace", "-CFLAGS -fsanitize=address,undefined", + "--binary --trace-vcd", "-CFLAGS -fsanitize=address,undefined", "-LDFLAGS -fsanitize=address,undefined" ]) diff --git a/test_regress/t/t_trace_wide_struct.py b/test_regress/t/t_trace_wide_struct.py index 89f022528..d25b73259 100755 --- a/test_regress/t/t_trace_wide_struct.py +++ b/test_regress/t/t_trace_wide_struct.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--trace --trace-structs']) +test.compile(verilator_flags2=['--trace-vcd --trace-structs']) test.passes() diff --git a/test_regress/t/t_unopt_array_csplit.py b/test_regress/t/t_unopt_array_csplit.py index 26fd8b3d1..ce0e4bae6 100755 --- a/test_regress/t/t_unopt_array_csplit.py +++ b/test_regress/t/t_unopt_array_csplit.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('vlt_all') test.top_filename = "t/t_unopt_array.v" -test.compile(v_flags2=["--trace --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"]) +test.compile(v_flags2=["--trace-vcd --output-split 1 --output-split-cfuncs 1 -Wno-UNOPTFLAT"]) test.execute() diff --git a/test_regress/t/t_unroll_delay.py b/test_regress/t/t_unroll_delay.py index 7729ce031..340ad8afb 100755 --- a/test_regress/t/t_unroll_delay.py +++ b/test_regress/t/t_unroll_delay.py @@ -11,7 +11,7 @@ import vltest_bootstrap test.scenarios('simulator') -test.compile(verilator_flags2=['--binary --trace']) +test.compile(verilator_flags2=['--binary --trace-vcd']) test.execute(expect_filename=test.golden_filename) diff --git a/test_regress/t/t_var_pins_sc1.py b/test_regress/t/t_var_pins_sc1.py index 69d66746d..3fdd5bb81 100755 --- a/test_regress/t/t_var_pins_sc1.py +++ b/test_regress/t/t_var_pins_sc1.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ - "-sc -pins-bv 1 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" + "-sc -pins-bv 1 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) diff --git a/test_regress/t/t_var_pins_sc2.py b/test_regress/t/t_var_pins_sc2.py index ef358bd83..845b9ddc9 100755 --- a/test_regress/t/t_var_pins_sc2.py +++ b/test_regress/t/t_var_pins_sc2.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ - "-sc -pins-bv 2 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" + "-sc -pins-bv 2 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) diff --git a/test_regress/t/t_var_pins_sc32.py b/test_regress/t/t_var_pins_sc32.py index 184ba2d2b..43b22fcd8 100755 --- a/test_regress/t/t_var_pins_sc32.py +++ b/test_regress/t/t_var_pins_sc32.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ - "-sc -no-pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" + "-sc -no-pins64 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) diff --git a/test_regress/t/t_var_pins_sc64.py b/test_regress/t/t_var_pins_sc64.py index 4dca57a9d..e51114c44 100755 --- a/test_regress/t/t_var_pins_sc64.py +++ b/test_regress/t/t_var_pins_sc64.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=[ - "-sc -pins64 --trace --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" + "-sc -pins64 --trace-vcd --exe", test.pli_filename, test.t_dir + "/t_var_pinsizes.vlt" ], make_main=False) diff --git a/test_regress/t/t_var_pins_sc_biguint.py b/test_regress/t/t_var_pins_sc_biguint.py index a50232864..9bfab903b 100755 --- a/test_regress/t/t_var_pins_sc_biguint.py +++ b/test_regress/t/t_var_pins_sc_biguint.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" -test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace --exe", test.pli_filename], +test.compile(verilator_flags2=["-sc --pins-sc-biguint --trace-vcd --exe", test.pli_filename], make_main=False) diff --git a/test_regress/t/t_var_pins_sc_uint.py b/test_regress/t/t_var_pins_sc_uint.py index 42602c6d0..8ad431263 100755 --- a/test_regress/t/t_var_pins_sc_uint.py +++ b/test_regress/t/t_var_pins_sc_uint.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" -test.compile(verilator_flags2=["-sc --pins-sc-uint --trace --exe", test.pli_filename], +test.compile(verilator_flags2=["-sc --pins-sc-uint --trace-vcd --exe", test.pli_filename], make_main=False) diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.py b/test_regress/t/t_var_pins_sc_uint_biguint.py index c480b6b87..1ebd47243 100755 --- a/test_regress/t/t_var_pins_sc_uint_biguint.py +++ b/test_regress/t/t_var_pins_sc_uint_biguint.py @@ -14,7 +14,7 @@ test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile( - verilator_flags2=["-sc --pins-sc-uint --pins-sc-biguint --trace --exe", test.pli_filename], + verilator_flags2=["-sc --pins-sc-uint --pins-sc-biguint --trace-vcd --exe", test.pli_filename], make_main=False) diff --git a/test_regress/t/t_var_pins_sc_uint_bool.py b/test_regress/t/t_var_pins_sc_uint_bool.py index 20acac5fe..8809d0bd4 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool.py +++ b/test_regress/t/t_var_pins_sc_uint_bool.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" -test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace --exe", test.pli_filename], +test.compile(verilator_flags2=["-sc --pins-sc-uint-bool --trace-vcd --exe", test.pli_filename], make_main=False) diff --git a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py index a6e5a22f5..daf0769be 100755 --- a/test_regress/t/t_var_pins_sc_uint_bool_nomain.py +++ b/test_regress/t/t_var_pins_sc_uint_bool_nomain.py @@ -18,7 +18,7 @@ test.top_filename = "t/t_a1_first_cc.v" DEBUG_QUIET = "--debug --debugi 0 --gdbbt --no-dump-tree" -test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace --pins-sc-uint-bool"]) +test.compile(verilator_flags2=[DEBUG_QUIET, "-sc --trace-vcd --pins-sc-uint-bool"]) test.execute() diff --git a/test_regress/t/t_var_pins_scui.py b/test_regress/t/t_var_pins_scui.py index 0f9beb9a2..02fa69cb8 100755 --- a/test_regress/t/t_var_pins_scui.py +++ b/test_regress/t/t_var_pins_scui.py @@ -13,7 +13,7 @@ test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" -test.compile(verilator_flags2=["-sc -pins-uint8 --trace --exe", test.pli_filename], +test.compile(verilator_flags2=["-sc -pins-uint8 --trace-vcd --exe", test.pli_filename], make_main=False) test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i1;') diff --git a/test_regress/t/t_verilated_all.py b/test_regress/t/t_verilated_all.py index 6c603bf31..e78a65173 100755 --- a/test_regress/t/t_verilated_all.py +++ b/test_regress/t/t_verilated_all.py @@ -20,7 +20,7 @@ test.compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2=[ "--cc", "--coverage-toggle --coverage-line --coverage-user", - "--trace --vpi ", "--trace-threads 1", + "--trace-vcd --vpi ", "--trace-threads 1", ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY"), "--prof-exec", "--prof-pgo", root + "/include/verilated_save.cpp" ], diff --git a/test_regress/t/t_verilated_all_newest.py b/test_regress/t/t_verilated_all_newest.py index 3a22434c1..99b357595 100755 --- a/test_regress/t/t_verilated_all_newest.py +++ b/test_regress/t/t_verilated_all_newest.py @@ -17,7 +17,7 @@ root = ".." test.compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2=[ - "--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi " + "--cc --coverage-toggle --coverage-line --coverage-user --trace-vcd --prof-exec --prof-pgo --vpi " + root + "/include/verilated_save.cpp", ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") ], diff --git a/test_regress/t/t_verilated_threaded.py b/test_regress/t/t_verilated_threaded.py index af80be73f..aec7efee3 100755 --- a/test_regress/t/t_verilated_threaded.py +++ b/test_regress/t/t_verilated_threaded.py @@ -17,7 +17,7 @@ root = ".." test.compile( # Can't use --coverage and --savable together, so cheat and compile inline verilator_flags2=[ - "--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi " + root + + "--cc --coverage-toggle --coverage-line --coverage-user --trace-vcd --vpi " + root + "/include/verilated_save.cpp", ("--timing" if test.have_coroutines else "--no-timing -Wno-STMTDLY") ], diff --git a/test_regress/t/t_vthread.py b/test_regress/t/t_vthread.py index f0c0d547c..5ee5d1e2d 100755 --- a/test_regress/t/t_vthread.py +++ b/test_regress/t/t_vthread.py @@ -42,8 +42,8 @@ def gen(filename, n): gen(test.top_filename, 6000) test.compile( - # use --trace to generate trace files that can be parallelized - verilator_flags2=["--stats --trace --verilate-jobs 2"]) + # use --trace-vcd to generate trace files that can be parallelized + verilator_flags2=["--stats --trace-vcd --verilate-jobs 2"]) test.execute() diff --git a/test_regress/t/t_wrapper_context.py b/test_regress/t/t_wrapper_context.py index 62943d1c4..8463741ab 100755 --- a/test_regress/t/t_wrapper_context.py +++ b/test_regress/t/t_wrapper_context.py @@ -15,7 +15,7 @@ test.compile( make_top_shell=False, make_main=False, # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + verilator_flags2=["--exe", test.pli_filename, "--trace-vcd --coverage -cc"], threads=1, make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) diff --git a/test_regress/t/t_wrapper_context_seq.py b/test_regress/t/t_wrapper_context_seq.py index 94fe6aa28..ebcdee42e 100755 --- a/test_regress/t/t_wrapper_context_seq.py +++ b/test_regress/t/t_wrapper_context_seq.py @@ -17,7 +17,7 @@ test.compile( make_top_shell=False, make_main=False, # link threads library, add custom .cpp code, add tracing & coverage support - verilator_flags2=["--exe", test.pli_filename, "--trace --coverage -cc"], + verilator_flags2=["--exe", test.pli_filename, "--trace-vcd --coverage -cc"], threads=1, make_flags=['CPPFLAGS_ADD=-DVL_NO_LEGACY']) diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index 1380b6278..a1d2d515f 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -281,7 +281,7 @@ function(verilate TARGET) endif() if(VERILATE_TRACE) - list(APPEND VERILATOR_ARGS --trace) + list(APPEND VERILATOR_ARGS --trace-vcd) endif() if(VERILATE_TRACE_FST) @@ -292,6 +292,10 @@ function(verilate TARGET) list(APPEND VERILATOR_ARGS --trace-saif) endif() + if(VERILATE_TRACE_VCD) + list(APPEND VERILATOR_ARGS --trace-vcd) + endif() + if(VERILATE_SYSTEMC) list(APPEND VERILATOR_ARGS --sc) else()