Support "#delay <statement>;" with associated STMTDLY warning.

git-svn-id: file://localhost/svn/verilator/trunk/verilator@965 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.65****
 
+***  Support "#delay <statement>;" with associated STMTDLY warning.
+
 **** Fix divide-by-zero errors in constant propagator.  [Rodney Sinclair]
 
 **** Fix wrong result with obscure signed-shift underneath a "? :".

bin/verilator

@@ -1718,6 +1718,16 @@ not really needed.  The best solution is to insure that each module is in a
 unique file by the same name.  Otherwise, make sure all library files are
 read in as libraries with -v, instead of automatically with -y.
 
+=item STMTDLY
+
+Warns that you have a statement with a delayed time in front of it, for
+example:
+
+    #100 $finish;
+
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item TASKNSVAR
 
 Error when a call to a task or function has a output from that task tied to

src/V3Error.h

@@ -48,6 +48,7 @@ public:
 	CASEX,		// Casex
 	CMPCONST,	// Comparison is constant due to limited range
 	COMBDLY,	// Combinatorial delayed assignment
+	STMTDLY,	// Delayed statement
 	GENCLK,		// Generated Clock
 	IMPLICIT,	// Implicit wire
 	IMPURE,		// Impure function not being inlined
@@ -76,7 +77,7 @@ public:
 	    " FIRST_WARN",
 	    "BLKANDNBLK",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",
-	    "COMBDLY", "GENCLK", "IMPLICIT", "IMPURE",
+	    "COMBDLY", "STMTDLY", "GENCLK", "IMPLICIT", "IMPURE",
 	    "MULTIDRIVEN",
 	    "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
 	    "VARHIDDEN", "WIDTH",

src/verilog.y

@@ -284,7 +284,7 @@ class AstSenTree;
 %token<fileline>	yPSL_BRA	"{"
 %token<fileline>	yPSL_KET	"}"
 
-%token<fileline>	';' '=' ',' '(' '.' '!' '~' '[' '@'
+%token<fileline>	';' '=' ',' '(' '.' '!' '~' '[' '@' '#'
 
 // [* is not a operator, as "[ * ]" is legal
 // [= and [-> could be repitition operators, but to match [* we don't add them.
@@ -332,6 +332,7 @@ class AstSenTree;
 %type<nodep>	generateRegion
 %type<nodep>	genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
 %type<nodep>	dlyTerm
+%type<fileline> delay
 %type<varp>	sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId
 %type<varp>	netSig netSigList
 %type<rangep>	rangeListE regrangeE anyrange rangeList delayrange portRangeE
@@ -639,10 +640,10 @@ delayE:		/* empty */				{ }
 	|	delay					{ } /* ignored */
 	;
 
-delay:		'#' dlyTerm				{ } /* ignored */
+delay:		'#' dlyTerm				{ $$ = $1; } /* ignored */
-	|	'#' '(' dlyInParen ')'			{ } /* ignored */
+	|	'#' '(' dlyInParen ')'			{ $$ = $1; } /* ignored */
-	|	'#' '(' dlyInParen ',' dlyInParen ')'		{ } /* ignored */
+	|	'#' '(' dlyInParen ',' dlyInParen ')'			{ $$ = $1; } /* ignored */
-	|	'#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')'	{ } /* ignored */
+	|	'#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')'	{ $$ = $1; } /* ignored */
 	;
 
 dlyTerm:	yaID 					{ $$ = NULL; }
@@ -829,6 +830,8 @@ stmt:		';'					{ $$ = NULL; }
 	|	labeledStmt				{ $$ = $1; }
 	|	yaID ':' labeledStmt			{ $$ = new AstBegin($2, *$1, $3); }  /*S05 block creation rule*/
 
+	|	delay stmtBlock				{ $$ = $2; $1->v3warn(STMTDLY,"Ignoring delay on this delayed statement.\n"); }
+
 	|	varRefDotBit yP_LTE delayE expr ';'	{ $$ = new AstAssignDly($2,$1,$4); }
 	|	varRefDotBit '=' delayE expr ';'	{ $$ = new AstAssign($2,$1,$4); }
 	|	varRefDotBit '=' yD_FOPEN '(' expr ',' expr ')' ';'	{ $$ = new AstFOpen($3,$1,$5,$7); }

test_regress/t/t_delay.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => [$Last_Self->{v3}?'-Wno-STMTDLY':''],
 	 );
 
 execute (

test_regress/t/t_delay.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -30,7 +30,7 @@ module t (/*AUTOARG*/
       else if (cyc==3) begin
 	 if (dly0 !== 32'h23) $stop;
 	 $write("*-* All Finished *-*\n");
-	 $finish;
+	 #100 $finish;
       end
    end
 

test_regress/t/t_delay_stmtdly_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_delay.v");
+
+compile (
+	 fails=>1,
+	 expect=>
+'%Warning-STMTDLY: t/t_delay.v:\d+: Ignoring delay on this delayed statement.
+.*%Error: Exiting due to.*',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;