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verilator
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Support V2K portlists with input a,b,... 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@932 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-06-12 13:58:56 +00:00
parent 2b5d7eeb50
commit 1265e8cce8
3 changed files with 19 additions and 6 deletions
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4
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@ -3,6 +3,10 @@ Revision history for Verilator
The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.65***
**** Support V2K portlists with "input a,b,...". [Mark Nodine]
* Verilator 3.651 5/22/2007
*** Added verilator_profcfunc utility. [Gene Weber]

17
src/verilog.y
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@ -288,7 +288,7 @@ class AstSenTree;
// Trailing E indicates this type may have empty match
%type<modulep> modHdr
%type<nodep> modPortsE portList port
%type<nodep> portV2kList portV2kSig
%type<nodep> portV2kArgs portV2kList portV2kSecond portV2kSig
%type<nodep> portV2kDecl ioDecl varDecl
%type<nodep> modParDecl modParList modParE
%type<nodep> modItem modItemList modItemListE modOrGenItem
@ -386,7 +386,7 @@ modParList: modParDecl { $$ = $1; }
modPortsE: /* empty */ { $$ = NULL; }
| '(' ')' { $$ = NULL; }
| '(' {V3Parse::s_pinNum=1;} portList ')' { $$ = $3; }
| '(' {V3Parse::s_pinNum=1;} portV2kList ')' { $$ = $3; }
| '(' {V3Parse::s_pinNum=1;} portV2kArgs ')' { $$ = $3; }
;
portList: port { $$ = $1; }
@ -396,8 +396,17 @@ portList: port { $$ = $1; }
port: yaID portRangeE { $$ = new AstPort(CRELINE(),V3Parse::s_pinNum++,*$1); }
;
portV2kList: portV2kDecl { $$ = $1; }
| portV2kList ',' portV2kDecl { $$ = $1->addNext($3); }
portV2kArgs: portV2kDecl { $$ = $1; }
| portV2kDecl ',' portV2kList { $$ = $1->addNext($3); }
;
portV2kList: portV2kSecond { $$ = $1; }
| portV2kList ',' portV2kSecond { $$ = $1->addNext($3); }
;
// Called only after a comma in a v2k list, to allow parsing "input a,b"
portV2kSecond: portV2kDecl { $$ = $1; }
| portV2kSig { $$ = $1; }
;
portV2kSig: sigAndAttr { $$=$1; $$->addNext(new AstPort(CRELINE(),V3Parse::s_pinNum++, V3Parse::s_varAttrp->name())); }

4
test_regress/t/t_func_outp.v
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@ -56,7 +56,7 @@ endmodule
module ftest(
input [ 7:0 ] a,
input [ 7:0 ] b,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
@ -85,7 +85,7 @@ endmodule // ftest
module mytop (
input [ 7:0 ] a,
input [ 7:0 ] b,
b,
input clk,
output [ 7:0 ] z
);