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Ignore protect, and allow empty case 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@926 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-05-18 14:03:50 +00:00
parent 2c5a183368
commit 18cb210eac
7 changed files with 42 additions and 19 deletions
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4
Changes
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@ -11,6 +11,10 @@ indicates the contributor was also the author of the fix; Thanks!
**** Warn if flex is not installed. [Ralf Karge]
**** Ignore `protect and `endprotect.
**** Allow empty case/endcase blocks.
* Verilator 3.650 4/20/2007
** Add --compiler msvc option. This is now required when Verilated code

3
src/V3Case.cpp
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@ -62,9 +62,6 @@ private:
//int debug() { return 9; }
virtual void visit(AstNodeCase* nodep, AstNUser*) {
// We report a syntax error on empty "case (x) endcase" blocks, so never no items at all
if (!nodep->itemsp()) nodep->v3fatalSrc("No items (not even default) under case statement?\n");
// Detect multiple defaults
bool hitDefault = false;
for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {

8
src/V3PreLex.l
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@ -57,6 +57,7 @@ static void pslMoreNeeded(bool flag) { V3PreLex::s_currentLexp->m_pslMoreNeeded
%x DEFMODE
%x ARGMODE
%x INCMODE
%x PRTMODE
/* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
@ -106,6 +107,13 @@ psl [p]sl
if (V3PreLex::s_currentLexp->m_parenLevel) appendDefValue(yytext,yyleng);
else return (VP_STRING); }
/* Protected blocks */
<INITIAL>"`protected" { yy_push_state(PRTMODE); yymore(); }
<PRTMODE><<EOF>> { linenoInc(); yyerror("EOF in `protected"); yyleng=0; yyterminate(); }
<PRTMODE>{crnl} { linenoInc(); yymore(); }
<PRTMODE>. { yymore(); }
<PRTMODE>"`endprotected" { yy_pop_state(); return (VP_TEXT); }
/* Pass-through include <> filenames */
<INCMODE><<EOF>> { linenoInc(); yyerror("EOF in unterminated include filename"); yyleng=0; yyterminate(); }
<INCMODE>{crnl} { linenoInc(); yyerror("Unterminated include filename"); BEGIN(INITIAL); }

4
src/V3PreShell.cpp
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@ -61,10 +61,6 @@ protected:
s_preprocp->define(prefl,"verilator3", "1");
s_preprocp->define(prefl,"systemc_clock", "/*verilator systemc_clock*/");
s_preprocp->define(prefl,"coverage_block_off", "/*verilator coverage_block_off*/");
// Standards - We ignore
s_preprocp->define(prefl,"resetall", "");
s_preprocp->define(prefl,"portcoerce", "");
s_preprocp->define(prefl,"inline", "");
}
}

13
src/verilog.l
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@ -626,18 +626,18 @@ escid \\[^ \t\f\r\n]+
yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
return yaINTNUM;
}
[0-9]+[_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]* {
[0-9][_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]* {
yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
return yaINTNUM;
}
[0-9]* { yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
[0-9][_0-9]* { yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext);
return yaINTNUM;
}
[-+]?[0-9]+(\.[0-9]+)([eE][-+]?[0-9]+)? {
[0-9][_0-9]*(\.[0-9]+)([eE][-+]?[0-9]+)? {
yylval.cdouble = 0; /* Only for delays, not used yet */
return yaFLOATNUM;
}
[-+]?[0-9]+(\.[0-9]+)?([eE][-+]?[0-9]+) {
[0-9][_0-9]*(\.[0-9]+)?([eE][-+]?[0-9]+) {
yylval.cdouble = 0; /* Only for delays, not used yet */
return yaFLOATNUM;
}
@ -674,8 +674,13 @@ escid \\[^ \t\f\r\n]+
<V95,V01,V05,S05,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
"`celldefine" { V3Read::inCellDefine(true); }
"`endcelldefine" { V3Read::inCellDefine(false); }
"`endprotect" { }
"`inline" { }
"`line"{ws}+[^\n]*\n { V3Read::ppline(yytext); }
"`portcoerce" { }
"`protect" { }
"`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
"`resetall" { }
"`systemc_ctor" { BEGIN SYSCCTOR; }
"`systemc_dtor" { BEGIN SYSCDTOR; }
"`systemc_header" { BEGIN SYSCHDR; }

26
src/verilog.y
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@ -292,7 +292,7 @@ class AstSenTree;
%type<nodep> portV2kDecl ioDecl varDecl
%type<nodep> modParDecl modParList modParE
%type<nodep> modItem modItemList modItemListE modOrGenItem
%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseList
%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
%type<nodep> dlyTerm
%type<varp> sigAndAttr sigId sigIdRange sigList regsig regsigList regSigId
%type<varp> netSig netSigList
@ -310,7 +310,7 @@ class AstSenTree;
%type<nodep> assertStmt
%type<beginp> beginNamed
%type<casep> caseStmt
%type<caseitemp> caseList
%type<caseitemp> caseList caseListE
%type<nodep> caseCondList assignList assignOne
%type<nodep> constExpr exprNoStr expr exprPsl exprStrText
%type<nodep> exprList cateList cStrList
@ -537,7 +537,7 @@ genItemList: genItem { $$ = $1; }
;
genItem: modOrGenItem { $$ = $1; }
| yCASE '(' expr ')' genCaseList yENDCASE { $$ = new AstGenCase($1,$3,$5); }
| yCASE '(' expr ')' genCaseListE yENDCASE { $$ = new AstGenCase($1,$3,$5); }
| yIF expr genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$2,$3,NULL); }
| yIF expr genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$2,$3,$5); }
| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' genItemBlock
@ -546,6 +546,10 @@ genItem: modOrGenItem { $$ = $1; }
,$13);}
;
genCaseListE: /* empty */ { $$ = NULL; }
| genCaseList { $$ = $1; }
;
genCaseList: caseCondList ':' genItemBlock { $$ = new AstCaseItem($2,$1,$3); }
| yDEFAULT ':' genItemBlock { $$ = new AstCaseItem($2,NULL,$3); }
| yDEFAULT genItemBlock { $$ = new AstCaseItem($1,NULL,$2); }
@ -643,9 +647,9 @@ regrangeE: /* empty */ { $$ = NULL; VARRANGE($$); }
anyrange: '[' constExpr ':' constExpr ']' { $$ = new AstRange($1,$2,$4); }
;
delayrange: delayE regrangeE { $$ = $2; }
| ySCALARED delayE regrangeE { $$ = $3; }
| yVECTORED delayE regrangeE { $$ = $3; }
delayrange: regrangeE delayE { $$ = $1; }
| ySCALARED regrangeE delayE { $$ = $2; }
| yVECTORED regrangeE delayE { $$ = $2; }
;
portRangeE: /* empty */ { $$ = NULL; }
@ -792,7 +796,7 @@ stmt: ';' { $$ = NULL; }
//************************************************
// Case/If
stateCaseForIf: caseStmt caseAttrE caseList yENDCASE { $$ = $1; $1->addItemsp($3); }
stateCaseForIf: caseStmt caseAttrE caseListE yENDCASE { $$ = $1; if ($3) $1->addItemsp($3); }
| yIF expr stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$2,$3,NULL); }
| yIF expr stmtBlock yELSE stmtBlock { $$ = new AstIf($1,$2,$3,$5); }
| yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock
@ -813,6 +817,10 @@ caseAttrE: /*empty*/ { }
| caseAttrE yVL_PARALLEL_CASE { V3Parse::s_caseAttrp->parallelPragma(true); }
;
caseListE: /* empty */ { $$ = NULL; }
| caseList { $$ = $1; }
;
caseList: caseCondList ':' stmtBlock { $$ = new AstCaseItem($2,$1,$3); }
| yDEFAULT ':' stmtBlock { $$ = new AstCaseItem($2,NULL,$3); }
| yDEFAULT stmtBlock { $$ = new AstCaseItem($1,NULL,$2); }
@ -1053,7 +1061,7 @@ specifyJunk: dlyTerm {} /* ignored */
| '&' {}
| '(' {}
| ')' {}
| '*' {} | '/' {} | '%' {} | yP_POW {}
| '*' {} | '/' {} | '%' {}
| '+' {} | '-' {}
| ',' {}
| ':' {}
@ -1076,10 +1084,12 @@ specifyJunk: dlyTerm {} /* ignored */
| yP_ANDAND {} | yP_GTE {} | yP_LTE {}
| yP_EQUAL {} | yP_NOTEQUAL {}
| yP_CASEEQUAL {} | yP_CASENOTEQUAL {}
| yP_XNOR {} | yP_NOR {} | yP_NAND {}
| yP_OROR {}
| yP_SLEFT {} | yP_SRIGHT {} | yP_SSRIGHT {}
| yP_PLUSCOLON {} | yP_MINUSCOLON {}
| yP_POW {}
| yP_LOGIF {}
| yP_LOGIFF {}

3
test_regress/t/t_case_wild.v
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@ -60,6 +60,9 @@ module sub (/*AUTOARG*/
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};