Tests: Rename some tests

2022-09-27 18:42:03 -04:00 · 2022-09-27 18:42:03 -04:00 · 1b1907af49
parent 1b18eee5dc
commit 1b1907af49
5 changed files with 6 additions and 0 deletions
--- a/test_regress/t/t_write_format_bug.out
+++ b/test_regress/t/t_write_format_bug.out
--- a/test_regress/t/t_write_format_bug.pl
+++ b/test_regress/t/t_write_format_bug.pl
--- a/test_regress/t/t_write_format_bug.v
+++ b/test_regress/t/t_write_format_bug.v
--- a/test_regress/t/t_queue_void_ops.pl
+++ b/test_regress/t/t_queue_void_ops.pl
--- a/test_regress/t/t_queue_void_ops.v
+++ b/test_regress/t/t_queue_void_ops.v
@ -1,3 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
 module t
  (/*AUTOARG*/
   // Inputs