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Fix pattern assignment to real inside struct (#5713).

This commit is contained in:
Wilson Snyder 2025-01-03 19:39:48 -05:00
parent 8ca49d98c1
commit 1d0563212e
4 changed files with 16 additions and 5 deletions
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@ -15,6 +15,7 @@ Verilator 5.033 devel
* Fix V3Simulate constant reuse (#5709). [Geza Lore]
* Fix man pages what-is section (#5710). [Ahmed El-Mahmoudy]
* Fix pattern assignment to real inside struct (#5713).
* Fix %p format output for real inside struct (#5713).

2
src/V3Width.cpp
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@ -2874,8 +2874,8 @@ class WidthVisitor final : public VNVisitor {
if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed
// Iterate into subDTypep() to resolve that type and update pointer.
nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
nodep->dtypep(nodep); // The member itself, not subDtype
nodep->widthFromSub(nodep->subDTypep());
nodep->dtypeFrom(nodep->subDTypep());
if (nodep->valuep()) {
userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p());
iterateCheckAssign(nodep, "Initial value", nodep->valuep(), FINAL, nodep->dtypep());

8
test_regress/t/t_json_only_tag.out
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@ -69,10 +69,10 @@
{"type":"BASICDTYPE","name":"logic","addr":"(RB)","loc":"d,24:7,24:12","dtypep":"(RB)","keyword":"logic","generic":false,"rangep": []},
{"type":"STRUCTDTYPE","name":"m.my_struct","addr":"(K)","loc":"d,20:12,20:18","dtypep":"(K)","packed":true,"isFourstate":true,"generic":false,"classOrPackagep":"UNLINKED",
"membersp": [
{"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(SB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(TB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(UB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(VB)","generic":false,"childDTypep": [],"valuep": []}
{"type":"MEMBERDTYPE","name":"clk","addr":"(SB)","loc":"d,21:19,21:22","dtypep":"(OB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"k","addr":"(TB)","loc":"d,22:19,22:20","dtypep":"(PB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"enable","addr":"(UB)","loc":"d,23:19,23:25","dtypep":"(QB)","generic":false,"childDTypep": [],"valuep": []},
{"type":"MEMBERDTYPE","name":"data","addr":"(VB)","loc":"d,24:19,24:23","dtypep":"(RB)","generic":false,"childDTypep": [],"valuep": []}
]},
{"type":"IFACEREFDTYPE","name":"","addr":"(O)","loc":"d,29:8,29:12","dtypep":"(O)","isPortDecl":false,"isVirtual":false,"cellName":"itop","ifaceName":"ifc","modportName":"","generic":false,"ifacep":"UNLINKED","cellp":"(L)","modportp":"UNLINKED","paramsp": []},
{"type":"BASICDTYPE","name":"logic","addr":"(S)","loc":"d,31:27,31:28","dtypep":"(S)","keyword":"logic","range":"31:0","generic":true,"rangep": []},

10
test_regress/t/t_struct_pat.v
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@ -31,8 +31,14 @@ module t(/*AUTOARG*/);
bit [3:0][31:0] b4;
} sab4p_t;
typedef struct {
int i;
real r;
} sir_t;
sab4u_t ab4u[2][3];
sab4p_t ab4p[2][3];
sir_t sir;
initial begin
abcp = '{1, 2, 3};
@ -96,6 +102,10 @@ module t(/*AUTOARG*/);
if (ab4u[1][2].b4[2] !== 20) $stop;
if (ab4u[1][2].b4[3] !== 30) $stop;
sir = '{1, 2.2};
if (sir.i !== 1) $stop;
if (sir.r !== 2.2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end