Tests: Verify function ref (#3385)

This commit is contained in:
Wilson Snyder 2024-11-25 20:38:41 -05:00
parent 25d75ee86f
commit 2ba0749993
2 changed files with 38 additions and 0 deletions

View File

@ -24,6 +24,16 @@ module t (/*AUTOARG*/);
int b;
int arr[1];
MyInt mi;
task update_inout(inout int flag, input bit upflag);
flag = upflag ? 1 + flag : flag;
endtask
task update_ref(ref int flag, input bit upflag);
flag = upflag ? 1 + flag : flag;
endtask
int my_flag;
initial begin
mi = new(1);
b = get_val_set_5(mi.x);
@ -35,6 +45,15 @@ module t (/*AUTOARG*/);
`checkh(arr[0], 5);
`checkh(b, 10);
update_ref(my_flag, 1);
if (my_flag !== 1) $stop;
update_ref(my_flag, 0);
if (my_flag !== 1) $stop;
update_inout(my_flag, 1);
if (my_flag !== 2) $stop;
update_inout(my_flag, 0);
if (my_flag !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

View File

@ -0,0 +1,19 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_func_ref.v"
test.compile()
test.execute()
test.passes()