Fix unresolved typedefs as parameters (#5850).

Changes

@@ -42,12 +42,13 @@ Verilator 5.035 devel
 * Fix checking built-in method arguments (#5839).
 * Fix splitting of packed ports with non-zero based ranges (#5842). [Geza Lore]
 * Fix NBA shared flag reuse (#5848). [Geza Lore]
+* Fix unresolved typedefs as parameters (#5850). [Eugene Feinberg, Brian Li]
 * Fix removal of callbacks no longer in current list (#5851) (#5852). [Gilberto Abram]
 * Fix segmentation fault on member compare (#5853).
 * Fix recursive error on virtual interfaces (#5854). [Yilou Wang]
 * Fix streaming of unpacked arrays concatenations (#5856). [Ryszard Rozak, Antmicro Ltd.]
 * Fix Windows paths in Perl (#5858) (#5860). [Tobias Jensen]
-* Fix algorithm header portability in V3Os.cpp (for std::replace). (#5861). [William D. Jones]
+* Fix algorithm header portability in V3Os.cpp (for std::replace) (#5861). [William D. Jones]
 
 
 Verilator 5.034 2025-02-24

src/V3Param.cpp

@@ -778,6 +778,10 @@ class ParamProcessor final {
                               << modvarp->prettyNameQ());
             } else {
                 UINFO(9, "Parameter type assignment expr=" << exprp << " to " << origp << endl);
+                V3Const::constifyParamsEdit(pinp->exprp());  // Reconcile typedefs
+                // Constify may have caused pinp->exprp to change
+                rawTypep = VN_AS(pinp->exprp(), NodeDType);
+                exprp = rawTypep->skipRefToNonRefp();
                 if (exprp->similarDType(origp)) {
                     // Setting parameter to its default value.  Just ignore it.
                     // This prevents making additional modules, and makes coverage more

test_regress/t/t_param_typedef.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.lint()
+
+test.passes()

test_regress/t/t_param_typedef.v

@@ -0,0 +1,54 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilator lint_off IMPLICIT
+
+module fifo_v3 #(
+    parameter int unsigned DATA_WIDTH = 32,
+    parameter int unsigned DEPTH = 8,
+    parameter type dtype_t = logic [DATA_WIDTH-1:0]
+)(
+    input int data_i,
+    output int data_o
+);
+    if (DEPTH == 0) begin : gen_pass_through
+    end
+endmodule
+
+module axi_lite_mux #(
+  parameter int unsigned NoSlvPorts = 32'd32,
+  parameter int unsigned MaxTrans = 32'd0
+) (
+  input logic clk_i,
+  input logic rst_ni
+);
+   wire [31:0] ar_select;
+   wire [31:0] r_select;
+
+   if (NoSlvPorts == 32'h1) begin : gen_no_mux
+   end
+   else begin : gen_mux
+      typedef logic [$clog2(NoSlvPorts)-1:0] select_t;
+      fifo_v3 #(
+                .DEPTH ( MaxTrans ),
+                .dtype_t ( select_t )
+                )
+      i_r_fifo (
+                .data_i ( ar_select ),
+                .data_o ( r_select )
+                );
+   end
+endmodule
+
+module t
+  (
+   input logic clk_i,
+   input logic rst_ni
+   );
+   axi_lite_mux i_axi_mux (
+                           .clk_i,
+                           .rst_ni);
+endmodule