More cleanup to match VParse, and support celldefine properly
git-svn-id: file://localhost/svn/verilator/trunk/verilator@922 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
b3dd18b215
commit
3aee7f918a
2
Changes
2
Changes
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.65**
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*** Treat modules within `celldefine and `endcelldefine as if in library.
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**** Warn if flex is not installed. [Ralf Karge]
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* Verilator 3.650 4/20/2007
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@ -62,8 +62,6 @@ protected:
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s_preprocp->define(prefl,"systemc_clock", "/*verilator systemc_clock*/");
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s_preprocp->define(prefl,"coverage_block_off", "/*verilator coverage_block_off*/");
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// Standards - We ignore
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s_preprocp->define(prefl,"endcelldefine", "");
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s_preprocp->define(prefl,"celldefine", "");
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s_preprocp->define(prefl,"resetall", "");
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s_preprocp->define(prefl,"portcoerce", "");
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s_preprocp->define(prefl,"inline", "");
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@ -38,7 +38,8 @@ class V3Read {
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V3Lexer* m_lexerp; // Current FlexLexer
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static V3Read* s_readp; // Current THIS, bison() isn't class based
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FileLine* m_fileline; // Filename/linenumber currently active
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bool m_inLibrary; // Currently reading a library vs. regular file
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bool m_inCellDefine; // Inside a `celldefine
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bool m_inLibrary; // Currently reading a library vs. regular file
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int m_inBeginKwd; // Inside a `begin_keywords
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int m_lastVerilogState; // Last LEX state in `begin_keywords
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deque<string*> m_stringps; // Created strings for later cleanup
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@ -92,6 +93,8 @@ public: // But for internal use only
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static FileLine* fileline() { return s_readp->m_fileline; }
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static AstNetlist* rootp() { return s_readp->m_rootp; }
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static FileLine* copyOrSameFileLine() { return s_readp->fileline()->copyOrSameFileLine(); }
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static bool inCellDefine() { return s_readp->m_inCellDefine; }
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static void inCellDefine(bool flag) { s_readp->m_inCellDefine = flag; }
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static bool inLibrary() { return s_readp->m_inLibrary; }
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static void stateExitPsl(); // Parser -> lexer communication
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static void statePushVlg(); // Parser -> lexer communication
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@ -102,6 +105,7 @@ public:
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// CREATORS
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V3Read(AstNetlist* rootp) {
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m_rootp = rootp; m_lexerp = NULL;
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m_inCellDefine = false;
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m_inLibrary = false;
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m_inBeginKwd = 0;
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m_lastVerilogState = stateVerilogRecent();
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@ -109,6 +109,7 @@ void yyerrorf(const char* format, ...) {
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%s IGNORE
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ws [ \t\f\r]+
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wsnr [ \t\f]+
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/* identifier */
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id [a-zA-Z_][a-zA-Z0-9_$]*
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/* escaped identifier */
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@ -182,7 +183,7 @@ escid \\[^ \t\f\r\n]+
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"not" {yylval.fileline = CRELINE(); return yNOT;}
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"or" {yylval.fileline = CRELINE(); return yOR;}
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"output" {yylval.fileline = CRELINE(); return yOUTPUT;}
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"parameter" {yylval.fileline = CRELINE(); return yPARAM;}
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"parameter" {yylval.fileline = CRELINE(); return yPARAMETER;}
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"posedge" {yylval.fileline = CRELINE(); return yPOSEDGE;}
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"reg" {yylval.fileline = CRELINE(); return yREG;}
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"scalared" {yylval.fileline = CRELINE(); return ySCALARED;}
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@ -640,9 +641,6 @@ escid \\[^ \t\f\r\n]+
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yylval.cdouble = 0; /* Only for delays, not used yet */
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return yaFLOATNUM;
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}
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"`timescale"{ws}+[^\n]* {}
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"`line"{ws}+[^\n]*\n {V3Read::ppline(yytext);}
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}
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/************************************************************************/
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@ -656,26 +654,29 @@ escid \\[^ \t\f\r\n]+
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return yaSTRING; }
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/************************************************************************/
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/* Preprocessor*/
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/* Common for all SYSC header states */
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/* OPTIMIZE: we return one per line, make it one for the entire block */
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<V95,V01,V05,S05,PSL,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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[ \t]*"`verilog" { BEGIN V3Read::lastVerilogState(); }
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[ \t]*"`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
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[ \t]*"`systemc_header" { BEGIN SYSCHDR; }
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[ \t]*"`systemc_ctor" { BEGIN SYSCCTOR; }
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[ \t]*"`systemc_dtor" { BEGIN SYSCDTOR; }
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[ \t]*"`systemc_interface" { BEGIN SYSCINT; }
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[ \t]*"`systemc_implementation" { BEGIN SYSCIMP; }
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[ \t]*"`systemc_imp_header" { BEGIN SYSCIMPH; }
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"`celldefine" { V3Read::inCellDefine(true); }
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"`endcelldefine" { V3Read::inCellDefine(false); }
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"`line"{ws}+[^\n]*\n { V3Read::ppline(yytext); }
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"`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } }
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"`systemc_ctor" { BEGIN SYSCCTOR; }
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"`systemc_dtor" { BEGIN SYSCDTOR; }
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"`systemc_header" { BEGIN SYSCHDR; }
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"`systemc_imp_header" { BEGIN SYSCIMPH; }
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"`systemc_implementation" { BEGIN SYSCIMP; }
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"`systemc_interface" { BEGIN SYSCINT; }
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"`timescale"{ws}+[^\n]* {}
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"`verilog" { BEGIN V3Read::lastVerilogState(); }
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[ \t]*"`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);}
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[ \t]*"`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
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[ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
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[ \t]*"`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);}
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[ \t]*"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);}
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[ \t]*"`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
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"`line"[ \t][^\n]*\n {V3Read::ppline(yytext);}
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"`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);}
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"`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
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"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);}
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"`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);}
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"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);}
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"`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
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}
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<SYSCHDR>[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR;}
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@ -688,7 +689,8 @@ escid \\[^ \t\f\r\n]+
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/* Pick up text-type data */
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<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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[ \t]*\n { NEXTLINE(); yymore();}
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{wsnr}* { yymore();}
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\n { NEXTLINE(); yymore();}
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\r ;
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}
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@ -697,9 +699,7 @@ escid \\[^ \t\f\r\n]+
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<V95,V01,V05,S05,PSL>{
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"`"[a-zA-Z_0-9]+ { yyerrorf("Define or directive not defined: %s",yytext); }
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"//"[^\n]+ { } /* throw away single line comments */
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. {yylval.fileline = CRELINE(); return yytext[0];} /* return single char ops. */
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}
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@ -30,7 +30,7 @@
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#include "V3Ast.h"
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#include "V3Global.h"
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#define YYERROR_VERBOSE
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#define YYERROR_VERBOSE 1
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#define YYMAXDEPTH 500
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// Pick up new lexer
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@ -83,11 +83,13 @@ AstVar* V3Parse::s_varAttrp = NULL;
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AstCase* V3Parse::s_caseAttrp = NULL;
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#define CRELINE() (V3Read::copyOrSameFileLine())
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#define VARRESET() { VARDECL(UNKNOWN); VARIO(UNKNOWN); VARSIGNED(false); VARRANGE(NULL); }
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#define VARDECL(type) { V3Parse::s_varDecl = AstVarType::type; }
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#define VARIO(type) { V3Parse::s_varIO = AstVarType::type; }
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#define VARSIGNED(value) { V3Parse::s_varSigned = value; }
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#define VARRANGE(range) { V3Parse::s_varRangep=(range); }
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#define INSTPREP(modname,paramsp) { V3Parse::s_impliedDecl = true; V3Parse::s_instModule = modname; V3Parse::s_instParamp = paramsp; }
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//======================================================================
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@ -157,7 +159,7 @@ class AstSenTree;
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%token<fileline> yDEFPARAM "defparam"
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%token<fileline> yDO "do"
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%token<fileline> yELSE "else"
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%token<fileline> yEND "bend"
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%token<fileline> yEND "end"
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%token<fileline> yENDCASE "endcase"
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%token<fileline> yENDFUNCTION "endfunction"
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%token<fileline> yENDGENERATE "endgenerate"
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@ -182,7 +184,7 @@ class AstSenTree;
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%token<fileline> yNOT "not"
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%token<fileline> yOR "or"
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%token<fileline> yOUTPUT "output"
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%token<fileline> yPARAM "param"
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%token<fileline> yPARAMETER "parameter"
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%token<fileline> yPOSEDGE "posedge"
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%token<fileline> yPSL "psl"
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%token<fileline> yREG "reg"
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@ -295,9 +297,10 @@ class AstSenTree;
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%type<varp> netSig netSigList
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%type<rangep> rangeListE regrangeE anyrange rangeList delayrange portRangeE
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%type<varp> param paramList
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%type<nodep> instDecl
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%type<nodep> instnameList
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%type<cellp> instname
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%type<pinp> cellpinList cellpinItList cellpinitemE instparamListE
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%type<cellp> instnameParen
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%type<pinp> cellpinList cellpinItList cellpinItemE instparamListE
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%type<nodep> defpList defpOne
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%type<sentreep> sensitivityE
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%type<senitemp> senList senitem senitemEdge
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@ -339,18 +342,18 @@ class AstSenTree;
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//**********************************************************************
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// Feedback to the Lexer
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stateExitPsl: { V3Read::stateExitPsl(); }
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stateExitPsl: /* empty */ { V3Read::stateExitPsl(); }
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;
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statePushVlg: { V3Read::statePushVlg(); }
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statePushVlg: /* empty */ { V3Read::statePushVlg(); }
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;
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statePop: { V3Read::statePop(); }
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statePop: /* empty */ { V3Read::statePop(); }
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;
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//**********************************************************************
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// Files
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file: mod
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| file mod
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file: mod { }
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| file mod { }
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;
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//**********************************************************************
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@ -362,19 +365,19 @@ mod: modHdr modParE modPortsE ';' modItemListE yENDMODULE
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;
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modHdr: yMODULE { V3Parse::s_trace=v3Global.opt.trace();}
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yaID { $$ = new AstModule($1,*$3); $$->inLibrary(V3Read::inLibrary());
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yaID { $$ = new AstModule($1,*$3); $$->inLibrary(V3Read::inLibrary()||V3Read::inCellDefine());
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$$->modTrace(v3Global.opt.trace());
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V3Read::rootp()->addModulep($$); }
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;
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modParE: /* empty */ { $$ = NULL; }
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| '#' '(' ')' { $$ = NULL; }
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| '#' '(' modParList ')' { $$ = $3; }
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| '#' '(' modParList ';' ')' { $$ = $3; }
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modParE: /* empty */ { $$ = NULL; }
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| '#' '(' ')' { $$ = NULL; }
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| '#' '(' modParList ')' { $$ = $3; }
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| '#' '(' modParList ';' ')' { $$ = $3; }
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;
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modParList: modParDecl { $$ = $1; }
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| modParList ';' modParDecl { $$ = $1->addNext($3); }
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modParList: modParDecl { $$ = $1; }
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| modParList ';' modParDecl { $$ = $1->addNext($3); }
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;
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modPortsE: /* empty */ { $$ = NULL; }
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@ -436,7 +439,7 @@ varNet: ySUPPLY0 { VARDECL(SUPPLY0); }
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| yWIRE { VARDECL(WIRE); }
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| yTRI { VARDECL(TRIWIRE); }
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;
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varGParam: yPARAM { VARDECL(GPARAM); }
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varGParam: yPARAMETER { VARDECL(GPARAM); }
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;
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varLParam: yLOCALPARAM { VARDECL(LPARAM); }
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;
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@ -498,12 +501,13 @@ modOrGenItem: yALWAYS sensitivityE stmtBlock { $$ = new AstAlways($1,$2,$3); }
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| yINITIAL stmtBlock { $$ = new AstInitial($1,$2); }
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| yASSIGN delayE assignList ';' { $$ = $3; }
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| yDEFPARAM defpList ';' { $$ = $2; }
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| yaID instparamListE {INSTPREP(*$1,$2);} instnameList ';' { $$ = $4; V3Parse::s_impliedDecl=false;}
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| instDecl { $$ = $1; }
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| taskDecl { $$ = $1; }
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| funcDecl { $$ = $1; }
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| gateDecl { $$ = $1; }
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| ioDecl { $$ = $1; }
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| varDecl { $$ = $1; }
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//No: | tableDecl // Unsupported
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| pslStmt { $$ = $1; }
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;
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@ -570,8 +574,7 @@ dlyTerm: yaID { $$ = NULL; }
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| yaFLOATNUM { $$ = NULL; }
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;
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sigAndAttr: sigId { $$ = $1; }
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| sigId sigAttrList { $$ = $1; }
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sigAndAttr: sigId sigAttrListE { $$ = $1; }
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;
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netSigList: netSig { $$ = $1; }
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@ -598,11 +601,10 @@ sigList: sigAndAttr { $$ = $1; }
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| sigList ',' sigAndAttr { $$ = $1; $1->addNext($3); }
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;
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regsig: regSigId {}
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| regSigId sigAttrList {}
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regsig: regSigId sigAttrListE {}
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;
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sigAttrListE: /*empty*/ {}
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sigAttrListE: /* empty */ {}
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| sigAttrList {}
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;
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@ -662,25 +664,27 @@ defpOne: yaID '.' yaID '=' expr { $$ = new AstDefParam($4,*$1,*$3,$5); }
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//************************************************
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// Instances
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instDecl: yaID instparamListE {INSTPREP(*$1,$2);} instnameList ';' { $$ = $4; V3Parse::s_impliedDecl=false;}
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instparamListE: /* empty */ { $$ = NULL; }
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| '#' '(' cellpinList ')' { $$ = $3; }
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;
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instnameList: instname { $$ = $1; }
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| instnameList ',' instname { $$ = $1->addNext($3); }
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instnameList: instnameParen { $$ = $1; }
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| instnameList ',' instnameParen { $$ = $1->addNext($3); }
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;
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instname: yaID funcRangeE '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); }
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instnameParen: yaID funcRangeE '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); }
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;
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cellpinList: {V3Parse::s_pinNum=1; V3Parse::s_pinStar=false; } cellpinItList { $$ = $2; }
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;
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cellpinItList: cellpinitemE { $$ = $1; }
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| cellpinItList ',' cellpinitemE { $$ = $1->addNextNull($3)->castPin(); }
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cellpinItList: cellpinItemE { $$ = $1; }
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| cellpinItList ',' cellpinItemE { $$ = $1->addNextNull($3)->castPin(); }
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;
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cellpinitemE: /* empty */ { $$ = NULL; V3Parse::s_pinNum++; }
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cellpinItemE: /* empty: ',,' is legal */ { $$ = NULL; V3Parse::s_pinNum++; }
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| '.' '*' { $$ = NULL; if (V3Parse::s_pinStar) $1->v3error("Duplicate .* in a cell"); V3Parse::s_pinStar=true; }
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| '.' yaID { $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
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| '.' yaID '(' ')' { $$ = NULL; V3Parse::s_pinNum++; }
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@ -1012,11 +1016,15 @@ gateXorPinList: expr { $$ = $1; }
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| gateXorPinList ',' expr { $$ = new AstXor($2,$1,$3); }
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;
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//************************************************
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// Tables
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// Not supported
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//************************************************
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// Specify
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specifyJunkList: specifyJunk /* ignored */
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| specifyJunkList specifyJunk /* ignored */
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specifyJunkList: specifyJunk {} /* ignored */
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| specifyJunkList specifyJunk {} /* ignored */
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;
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specifyJunk: dlyTerm {} /* ignored */
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