Fix unpacked to packed parameter assignment (#6088) (#6081)

src/V3Const.cpp

@@ -2752,11 +2752,6 @@ class ConstVisitor final : public VNVisitor {
             } else {
                 AstNode* const fromp = nodep->fromp()->unlinkFrBack();
                 nodep->replaceWithKeepDType(fromp);
-                if (VN_IS(fromp->dtypep()->skipRefp(), NodeArrayDType)) {
-                    // Strip off array to find what array references
-                    fromp->dtypeFrom(
-                        VN_AS(fromp->dtypep()->skipRefp(), NodeArrayDType)->subDTypep());
-                }
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             }
         }

test_regress/t/t_unpacked_to_packed_param.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("vlt")
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_unpacked_to_packed_param.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Confirm x randomization stability
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+    // Inputs
+    clk
+    );
+
+    input clk;
+
+    always @(posedge clk) begin
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+
+    localparam logic [1:0][7:0] foo_unpacked [2:0] = '{"12", "34", "56"};
+    localparam logic [2:0][1:0][7:0] foo_packed = '{"12", "34", "56"};
+
+    sub #(
+        .foos ({foo_unpacked[0], foo_unpacked[1], foo_unpacked[2]})
+    ) the_unpacked_sub();
+
+    sub #(
+        .foos ({foo_packed[0], foo_packed[1], foo_packed[2]})
+    ) the_packed_sub();
+
+endmodule
+
+module sub #(
+    parameter logic [2:0][1:0][7:0] foos
+);
+    initial begin
+        if (foos != "563412") $stop;
+    end
+endmodule