Tests: Split and rename t_parse_sync_bad

test_regress/t/t_parse_sync_bad.out

@@ -0,0 +1,11 @@
+%Error: t/t_parse_sync_bad.v:19:22: syntax error, unexpected IDENTIFIER, expecting "'{"
+   19 |       pkg::cls::defi invalid;   
+      |                      ^~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_parse_sync_bad.v:25:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
+   25 |    logic clk /*verilator clocker*/ ;
+      |              ^~~~~~~~~~~~~~~~~~~~~
+%Error: t/t_parse_sync_bad.v:29:1: syntax error, unexpected endmodule
+   29 | endmodule
+      | ^~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_parse_sync_bad.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Dan Petrisko.
+// SPDX-License-Identifier: CC0-1.0
+
+package pkg;
+   class cls;
+      typedef unknown defu;
+      typedef int defi;
+   endclass
+endpackage
+
+module t;
+   task tsk;
+      begin
+      valid1 = 5;  // valid statement
+
+      pkg::cls::defi invalid;  // invalid statement
+      end
+   endtask
+endmodule
+
+typedef struct packed {
+   logic clk /*verilator clocker*/;
+   logic data;
+} ss_s;
+
+endmodule

test_regress/t/t_parse_sync_bad2.out

@@ -0,0 +1,8 @@
+%Error: t/t_parse_sync_bad2.v:17:16: syntax error, unexpected IDENTIFIER
+   17 |       Invalid1 invalid1;   
+      |                ^~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_parse_sync_bad2.v:20:16: syntax error, unexpected IDENTIFIER
+   20 |       Invalid2 invalid2;   
+      |                ^~~~~~~~
+%Error: Exiting due to

test_regress/t/t_parse_sync_bad2.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_parse_sync_bad2.v

@@ -18,17 +18,6 @@ module t;
       pkg::cls::defi valid1;  // valid declaration
       pkg::cls::defu valid2;  // valid declaration
       Invalid2 invalid2;  // invalid declaration
-
-      valid1 = 5;  // valid statement
-
-      pkg::cls::defi invalid;  // invalid statement
       end
    endtask
 endmodule
-
-typedef struct packed {
-   logic clk /*verilator clocker*/;
-   logic data;
-} ss_s;
-
-endmodule

test_regress/t/t_source_sync_bad.out

@@ -1,17 +0,0 @@
-%Error: t/t_source_sync_bad.v:17:16: syntax error, unexpected IDENTIFIER
-   17 |       Invalid1 invalid1;   
-      |                ^~~~~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_source_sync_bad.v:20:16: syntax error, unexpected IDENTIFIER
-   20 |       Invalid2 invalid2;   
-      |                ^~~~~~~~
-%Error: t/t_source_sync_bad.v:24:22: syntax error, unexpected IDENTIFIER, expecting "'{"
-   24 |       pkg::cls::defi invalid;   
-      |                      ^~~~~~~
-%Error: t/t_source_sync_bad.v:30:14: syntax error, unexpected /*verilator clocker*/, expecting ',' or ';'
-   30 |    logic clk /*verilator clocker*/ ;
-      |              ^~~~~~~~~~~~~~~~~~~~~
-%Error: t/t_source_sync_bad.v:34:1: syntax error, unexpected endmodule
-   34 | endmodule
-      | ^~~~~~~~~
-%Error: Exiting due to