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Fix parsing input wire with default and range (#5800).

This commit is contained in:
Wilson Snyder 2025-02-24 03:51:49 -05:00
parent 7ec32799b0
commit 4ce8164277
3 changed files with 39 additions and 13 deletions
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1
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@ -58,6 +58,7 @@ Verilator 5.033 devel
* Fix unpacked split_var (#5782) (#5785). [Yutetsu TAKATSUKASA]
* Fix time import error on time parameters (#5786). [Luca Colagrande]
* Fix `$monitor` with dotted references (#5794). [Ahmed Elzeftawi]
* Fix parsing input wire with default and range (#5800). [RJ Cunningham]
* Fix matching language extension options including dots.

36
src/verilog.y
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@ -1479,13 +1479,13 @@ portsStarE<nodep>: // IEEE: .* + list_of_ports + list_of_port_decla
;
list_of_portsE<nodep>: // IEEE: [ list_of_ports + list_of_port_declarations ]
portAndTagE { $$ = $1; }
portAndTagE { $$ = $1; }
| list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); }
;
list_of_ports<nodep>: // IEEE: list_of_ports + list_of_port_declarations
portAndTag { $$ = $1; }
| list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); }
portAndTag { $$ = $1; }
| list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); }
;
portAndTagE<nodep>:
@ -1584,33 +1584,43 @@ port<nodep>: // ==IEEE: port
//
| portDirNetE data_type portSig variable_dimensionListE sigAttrListE
{ $$ = $3; VARDTYPE($2); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); }
| portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $3; VARDTYPE($2); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE
{ $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
{ $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE signing portSig variable_dimensionListE sigAttrListE
{ $$ = $3;
AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2};
VARDTYPE_NDECL(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $4, $5)); }
| portDirNetE signing portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $3;
AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2};
VARDTYPE_NDECL(dtp); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
| portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE
{ $$ = $4;
AstNodeDType* const dtp = GRAMMARP->addRange(
new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}, $3, true);
VARDTYPE_NDECL(dtp);
addNextNull($$, VARDONEP($$, $5, $6)); }
| portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4;
AstNodeDType* const dtp = GRAMMARP->addRange(
new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}, $3, true);
VARDTYPE_NDECL(dtp);
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE
{ $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); }
//
| portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $3; VARDTYPE($2); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $2; /*VARDTYPE-same*/
if (AstVar* vp = VARDONEP($$, $3, $4)) { addNextNull($$, vp); vp->valuep($6); } }

15
test_regress/t/t_module_input_default_value.v
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@ -43,6 +43,15 @@ module dut_default_input_logic32
endmodule
module dut_default_input_wire32
(
input wire [31:0] i = 32'h12345678,
output logic [31:0] o
);
assign o = i;
endmodule
module t
(/*AUTOARG*/
// Inputs
@ -104,6 +113,11 @@ module t
(.i(), // open
.o(dut_logic32_o_open));
logic [31:0] dut_wire32_o_open;
dut_default_input_wire32 u_dut_wire32_open
(.i(), // open
.o(dut_wire32_o_open));
// 3. DUT instances with overriden values
// instance names are u_dut*_overriden
@ -153,6 +167,7 @@ module t
if (dut0_o_open != 0) $error;
if (dut1_o_open != 1) $error;
if (dut_logic32_o_open != 32'h1234_5678) $error;
if (dut_wire32_o_open != 32'h1234_5678) $error;
// despite the port map override. At least the parameter goes through?
$display("%t %m: outputs - overrides got {%0d %0d %0x} want {1 0 %0x}",