Internals: Rename to instances, and other minor cleanups
This commit is contained in:
Wilson Snyder
parent
01e66ac349
commit
51616ecf2f
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@ -183,7 +183,7 @@ Summary:
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With :vlopt:`--clk`, the specified signal is marked as a clock signal.
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The provided signal name is specified using a RTL hierarchy path. For
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example, v.foo.bar. If the signal is the input to top-module, then
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example, v.foo.bar. If the signal is the input to the top-module, then
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directly provide the signal name. Alternatively, use a
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:option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
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signal directly.
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@ -40,7 +40,7 @@ class ClassVisitor final : public VNVisitor {
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const VNUser1InUse m_inuser1;
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// MEMBERS
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string m_prefix; // String prefix to add to name based on hier
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string m_prefix; // String prefix to add to class name based on hier
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V3UniqueNames m_names; // For unique naming of structs and unions
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AstNodeModule* m_modp = nullptr; // Current module
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AstNodeModule* m_classPackagep = nullptr; // Package moving into
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@ -415,7 +415,7 @@ const V3ParseBisonYYSType* V3ParseImp::tokenPeekp(size_t depth) {
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return &m_tokensAhead.at(depth);
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}
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size_t V3ParseImp::tokenPipeScanIdCell(size_t depthIn) {
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size_t V3ParseImp::tokenPipeScanIdInst(size_t depthIn) {
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// Search around IEEE module_instantiation/interface_instantiation/program_instantiation
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// Return location of following token, or input if not found
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// yaID/*module_identifier*/ [ '#' '('...')' ] yaID/*name_of_instance*/ [ '['...']' ] '(' ...
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@ -533,7 +533,7 @@ int V3ParseImp::tokenPipelineId(int token) {
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VL_RESTORER(yylval); // Remember value, as about to read ahead
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if (m_tokenLastBison.token != '@' && m_tokenLastBison.token != '#'
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&& m_tokenLastBison.token != '.') {
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if (const size_t depth = tokenPipeScanIdCell(0)) return yaID__aCELL;
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if (const size_t depth = tokenPipeScanIdInst(0)) return yaID__aINST;
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}
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if (nexttok == '#') { // e.g. class_type parameter_value_assignment '::'
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const size_t depth = tokenPipeScanParam(0, false);
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@ -757,7 +757,7 @@ std::ostream& operator<<(std::ostream& os, const V3ParseBisonYYSType& rhs) {
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if (rhs.token == yaID__ETC //
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|| rhs.token == yaID__CC //
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|| rhs.token == yaID__LEX //
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|| rhs.token == yaID__aCELL //
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|| rhs.token == yaID__aINST //
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|| rhs.token == yaID__aTYPE) {
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os << " strp='" << *(rhs.strp) << "'";
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}
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@ -314,9 +314,9 @@ private:
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void tokenPipeline() VL_MT_DISABLED; // Internal; called from tokenToBison
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int tokenPipelineId(int token) VL_MT_DISABLED;
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void tokenPipelineSym() VL_MT_DISABLED;
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size_t tokenPipeScanIdCell(size_t depth) VL_MT_DISABLED;
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size_t tokenPipeScanIdInst(size_t depth) VL_MT_DISABLED;
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size_t tokenPipeScanBracket(size_t depth) VL_MT_DISABLED;
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size_t tokenPipeScanParam(size_t depth, bool forCell) VL_MT_DISABLED;
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size_t tokenPipeScanParam(size_t depth, bool forInst) VL_MT_DISABLED;
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size_t tokenPipeScanTypeEq(size_t depth) VL_MT_DISABLED;
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const V3ParseBisonYYSType* tokenPeekp(size_t depth) VL_MT_DISABLED;
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void preprocDumps(std::ostream& os, bool forInputs) VL_MT_DISABLED;
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@ -430,7 +430,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
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%token<strp> yaID__ETC "IDENTIFIER"
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%token<strp> yaID__CC "IDENTIFIER-::"
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%token<strp> yaID__LEX "IDENTIFIER-in-lex"
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%token<strp> yaID__aCELL "IDENTIFIER-for-cell"
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%token<strp> yaID__aINST "IDENTIFIER-for-instance"
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%token<strp> yaID__aTYPE "IDENTIFIER-for-type"
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// Can't predecode aFUNCTION, can declare after use
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// Can't predecode aINTERFACE, can declare after use
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@ -1444,7 +1444,7 @@ parameter_value_assignmentClassE<pinp>: // IEEE: [ parameter_value_assignme
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;
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parameter_value_assignmentInst<pinp>: // IEEE: parameter_value_assignment for instance
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'#' '(' cellparamListE ')' { $$ = $3; }
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'#' '(' instParamListE ')' { $$ = $3; }
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// // Parentheses are optional around a single parameter
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// // IMPORTANT: Below hardcoded in tokenPipeScanParam
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| '#' yaINTNUM { $$ = new AstPin{$<fl>2, 1, "", new AstConst{$<fl>2, *$2}}; }
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@ -1459,7 +1459,7 @@ parameter_value_assignmentInst<pinp>: // IEEE: parameter_value_assignment
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parameter_value_assignmentClass<pinp>: // IEEE: parameter_value_assignment (for classes)
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// // Like parameter_value_assignment, but for classes only, which always have #()
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'#' '(' cellparamListE ')' { $$ = $3; }
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'#' '(' instParamListE ')' { $$ = $3; }
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;
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parameter_port_listE<nodep>: // IEEE: parameter_port_list + empty == parameter_value_assignment
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@ -3017,7 +3017,7 @@ loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
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initp->unlinkFrBackWithNext(); // Detach 2nd from varp, make 1st init
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blkp->addStmtsp(varp);
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}
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// Statements are under 'genforp' as cells under this
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// Statements are under 'genforp' as instances under this
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// for loop won't get an extra layer of hierarchy tacked on
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blkp->genforp(new AstGenFor{$1, initp, $5, $7, lowerNoBegp});
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$$ = blkp;
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@ -3324,8 +3324,8 @@ etcInst<nodep>: // IEEE: module_instantiation + gate_instantiati
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instDecl<nodep>:
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// // Disambigurated from data_declaration based on
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// // idCell which is found as IEEE requires a later '('
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idCell parameter_value_assignmentInstE
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// // idInst which is found as IEEE requires a later '('
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idInst parameter_value_assignmentInstE
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/*mid*/ { INSTPREP($<fl>1, *$1, $2); }
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/*cont*/ instnameList ';'
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{ $$ = $4;
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@ -3358,12 +3358,12 @@ instnameList<nodep>:
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;
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instnameParen<nodep>:
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id instRangeListE '(' cellpinListE ')'
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id instRangeListE '(' instPinListE ')'
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{ $$ = GRAMMARP->createCell($<fl>1, *$1, $4, $2); }
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;
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instnameParenUdpn<nodep>: // IEEE: part of udp_instance when no name_of_instance
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'(' cellpinListE ')' // When UDP has empty name, unpacked dimensions must not be used
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'(' instPinListE ')' // When UDP has empty name, unpacked dimensions must not be used
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{ $$ = GRAMMARP->createCell($<fl>1, "", $2, nullptr); }
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;
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@ -3384,31 +3384,31 @@ instRange<nodeRangep>:
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{ $$ = new AstRange{$1, $2, $4}; }
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;
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cellparamListE<pinp>:
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{ GRAMMARP->pinPush(); } cellparamItListE { $$ = $2; GRAMMARP->pinPop(CRELINE()); }
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instParamListE<pinp>:
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{ GRAMMARP->pinPush(); } instParamItListE { $$ = $2; GRAMMARP->pinPop(CRELINE()); }
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;
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cellpinListE<pinp>:
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{ VARRESET_LIST(UNKNOWN); } cellpinItListE { $$ = $2; VARRESET_NONLIST(UNKNOWN); }
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instPinListE<pinp>:
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{ VARRESET_LIST(UNKNOWN); } instPinItListE { $$ = $2; VARRESET_NONLIST(UNKNOWN); }
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;
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cellparamItListE<pinp>: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments
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instParamItListE<pinp>: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments
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// // Empty gets a node, to track class reference of #()
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/*empty*/ { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; }
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| cellparamItList { $$ = $1; }
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| instParamItList { $$ = $1; }
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;
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cellparamItList<pinp>: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments
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cellparamItem { $$ = $1; }
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| cellparamItList ',' cellparamItem { $$ = addNextNull($1, $3); }
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instParamItList<pinp>: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments
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instParamItem { $$ = $1; }
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| instParamItList ',' instParamItem { $$ = addNextNull($1, $3); }
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;
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cellpinItListE<pinp>: // IEEE: list_of_port_connections
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cellpinItemE { $$ = $1; }
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| cellpinItListE ',' cellpinItemE { $$ = addNextNull($1, $3); }
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instPinItListE<pinp>: // IEEE: list_of_port_connections
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instPinItemE { $$ = $1; }
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| instPinItListE ',' instPinItemE { $$ = addNextNull($1, $3); }
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;
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cellparamItem<pinp>: // IEEE: named_parameter_assignment + empty
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instParamItem<pinp>: // IEEE: named_parameter_assignment + empty
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// // Note empty is not allowed in parameter lists
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yP_DOTSTAR { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; }
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| '.' idAny '(' ')'
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@ -3446,7 +3446,7 @@ cellparamItem<pinp>: // IEEE: named_parameter_assignment + empty
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//UNSUP $$ = new AstPin{FILELINE_OR_CRE($3), PINNUMINC(), "", $3}; }
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;
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cellpinItemE<pinp>: // IEEE: named_port_connection + empty
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instPinItemE<pinp>: // IEEE: named_port_connection + empty
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// // Note empty can match either () or (,); V3LinkCells cleans up ()
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/* empty: ',,' is legal */ { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; }
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| yP_DOTSTAR { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; }
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@ -4719,12 +4719,12 @@ funcId<nodeFTaskp>: // IEEE: function_data_type_or_implicit + part o
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{ $$ = $2;
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$$->fvarp($1);
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SYMP->pushNewUnderNodeOrCurrent($$, $<scp>2); }
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| packageClassScopeE idCellType packed_dimensionListE fIdScoped
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| packageClassScopeE idInstType packed_dimensionListE fIdScoped
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{ AstRefDType* const refp = new AstRefDType{$<fl>2, *$2, $1, nullptr};
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$$ = $4;
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$$->fvarp(GRAMMARP->createArray(refp, $3, true));
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SYMP->pushNewUnderNodeOrCurrent($$, $<scp>4); }
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| packageClassScopeE idCellType parameter_value_assignmentClass packed_dimensionListE fIdScoped
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| packageClassScopeE idInstType parameter_value_assignmentClass packed_dimensionListE fIdScoped
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{ AstRefDType* const refp = new AstRefDType{$<fl>2, *$2, $1, $3};
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$$ = $5;
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$$->fvarp(GRAMMARP->createArray(refp, $4, true));
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@ -5901,18 +5901,24 @@ id<strp>:
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| idRandomize { $$ = $1; $<fl>$ = $<fl>1; }
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;
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idAny<strp>: // Any kind of identifier
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idAny<strp>: // Any kind of identifier
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yaID__ETC { $$ = $1; $<fl>$ = $<fl>1; }
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| yaID__aCELL { $$ = $1; $<fl>$ = $<fl>1; }
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| yaID__aINST { $$ = $1; $<fl>$ = $<fl>1; }
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| yaID__aTYPE { $$ = $1; $<fl>$ = $<fl>1; }
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| idRandomize { $$ = $1; $<fl>$ = $<fl>1; }
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;
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idCell<strp>: // IEEE: instance_identifier or similar with another id then '('
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// // See V3ParseImp::tokenPipeScanIdCell
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idAnyAsParseRef<parseRefp>: // Any kind of identifier as a ParseRef
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idAny
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{ $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1}; }
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;
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idInst<strp>: // IEEE: instance_identifier or similar with another id then '('
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// // See V3ParseImp::tokenPipeScanIdInst
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// // [^': '@' '.'] yaID/*module_id*/ [ '#' '('...')' ] yaID/*name_of_instance*/ [ '['...']' ] '(' ...
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// // [^':' @' '.'] yaID/*module_id*/ [ '#' id|etc ] yaID/*name_of_instance*/ [ '['...']' ] '(' ...
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yaID__aCELL { $$ = $1; $<fl>$ = $<fl>1; }
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yaID__aINST { $$ = $1; $<fl>$ = $<fl>1; }
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;
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idType<strp>: // IEEE: class_identifier or other type identifier
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@ -5920,8 +5926,8 @@ idType<strp>: // IEEE: class_identifier or other type identifi
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yaID__aTYPE { $$ = $1; $<fl>$ = $<fl>1; }
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;
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idCellType<strp>: // type_identifier for functions which have a following id then '('
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yaID__aCELL { $$ = $1; $<fl>$ = $<fl>1; }
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idInstType<strp>: // type_identifier for functions which have a following id then '('
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yaID__aINST { $$ = $1; $<fl>$ = $<fl>1; }
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| yaID__aTYPE { $$ = $1; $<fl>$ = $<fl>1; }
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;
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@ -6171,8 +6177,8 @@ list_of_clocking_decl_assign<nodep>: // IEEE: list_of_clocking_decl_assign
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;
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clocking_decl_assign<nodep>: // IEEE: clocking_decl_assign
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idAny/*new-signal_identifier*/ exprEqE
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{ AstParseRef* const refp = new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr};
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idAnyAsParseRef/*new-signal_identifier*/ exprEqE
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{ AstParseRef* const refp = $1;
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$$ = refp;
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if ($2) $$ = new AstAssign{$<fl>2, refp, $2}; }
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;
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@ -6196,8 +6202,8 @@ clocking_skew<nodeExprp>: // IEEE: clocking_skew
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cycle_delay<delayp>: // IEEE: cycle_delay
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yP_POUNDPOUND yaINTNUM
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{ $$ = new AstDelay{$<fl>1, new AstConst{$<fl>2, *$2}, true}; }
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| yP_POUNDPOUND idAny
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{ $$ = new AstDelay{$<fl>1, new AstParseRef{$<fl>2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}, true}; }
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| yP_POUNDPOUND idAnyAsParseRef
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{ $$ = new AstDelay{$<fl>1, $2, true}; }
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| yP_POUNDPOUND '(' expr ')'
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{ $$ = new AstDelay{$<fl>1, $3, true}; }
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;
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@ -7295,8 +7301,8 @@ checker_generate_item<nodep>: // ==IEEE: checker_generate_item
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//UNSUPchecker_instantiation<nodep>:
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//UNSUP // // Only used for procedural_assertion_item's
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//UNSUP // // Version in concurrent_assertion_item looks like etcInst
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//UNSUP // // Thus instead of *_checker_port_connection we can use etcInst's cellpinListE
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//UNSUP id/*checker_identifier*/ id '(' cellpinListE ')' ';' { }
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//UNSUP // // Thus instead of *_checker_port_connection we can use etcInst's instPinListE
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//UNSUP id/*checker_identifier*/ id '(' instPinListE ')' ';' { }
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//UNSUP ;
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//**********************************************************************
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@ -1,3 +1,4 @@
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// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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@ -12,6 +13,10 @@ library rtllib2 *.v, *.sv;
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library rtllib3 *.v -incdir *.vh;
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library rtllib4 *.v -incdir *.vh, *.svh;
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// Note this does not start a comment
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library gatelib ./*.vg;
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// */
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config cfg;
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design t;
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endconfig
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@ -1,29 +1,32 @@
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%Error-UNSUPPORTED: t/t_config_libmap.map:8:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
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%Error-UNSUPPORTED: t/t_config_libmap.map:9:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
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: ... Suggest unless in a lib.map file, want `include instead
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8 | include ./t_config_libmap_inc.map
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9 | include ./t_config_libmap_inc.map
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| ^~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: t/t_config_libmap.map:8:9: syntax error, unexpected '.'
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8 | include ./t_config_libmap_inc.map
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%Error: t/t_config_libmap.map:9:9: syntax error, unexpected '.'
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9 | include ./t_config_libmap_inc.map
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| ^
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error-UNSUPPORTED: t/t_config_libmap.map:10:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
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10 | library rtllib *.v;
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| ^~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
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11 | library rtllib2 *.v, *.sv;
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11 | library rtllib *.v;
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| ^~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
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12 | library rtllib3 *.v -incdir *.vh;
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12 | library rtllib2 *.v, *.sv;
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| ^~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:12:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
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%Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
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13 | library rtllib4 *.v -incdir *.vh, *.svh;
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13 | library rtllib3 *.v -incdir *.vh;
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| ^~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:13:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
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13 | library rtllib4 *.v -incdir *.vh, *.svh;
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%Error-UNSUPPORTED: t/t_config_libmap.map:14:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
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14 | library rtllib4 *.v -incdir *.vh, *.svh;
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| ^~~~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:14:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
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14 | library rtllib4 *.v -incdir *.vh, *.svh;
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| ^~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_config_libmap.map:15:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config'
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%Error-UNSUPPORTED: t/t_config_libmap.map:16:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design'
|
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%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
|
||||
%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
|
||||
17 | library gatelib .
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_config_libmap.map:20:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config'
|
||||
%Error-UNSUPPORTED: t/t_config_libmap.map:21:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design'
|
||||
%Error-UNSUPPORTED: t/t_config_libmap.map:22:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
|
||||
%Error: Exiting due to
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
// -*- Verilog -*-
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or IDENTIFIER-for-cell or IDENTIFIER-for-type or randomize
|
||||
%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or IDENTIFIER-for-instance or IDENTIFIER-for-type or randomize
|
||||
9 | localparam type bad2 = 2;
|
||||
| ^
|
||||
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
|
||||
|
|
|
|||
Loading…
Reference in New Issue