Fix array bounds checking with class member selects (#5996) (#5997).

This commit is contained in:
Wilson Snyder 2025-06-07 17:20:48 -04:00
parent a044697990
commit 5b2dc52681
4 changed files with 48 additions and 1 deletions

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@ -40,6 +40,7 @@ Verilator 5.037 devel
* Fix AstAssignW conversion (#5991) (#5992). [Ryszard Rozak, Antmicro Ltd.]
* Fix const-bit-op-tree with single-bit masks (#5993) (#5998). [Yutetsu TAKATSUKASA]
* Fix arithmetic right-shift by constants over 32 bits (#5994). [Zhen Yan]
* Fix array bounds checking with class member selects (#5996) (#5997). [Krzysztof Starecki]
* Fix checking for too-wide divide and modulus (#6003) (#6006). [Zhen Yan]
* Fix folding of LteS in DfgPeephole (#6000) (#6004). [Geza Lore]
* Fix slicing of AstExprStmt nodes (#6005). [Ryszard Rozak, Antmicro Ltd.]

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@ -102,7 +102,7 @@ class UnknownVisitor final : public VNVisitor {
// Scan back to put the condlvalue above all selects (IE top of the lvalue)
while (VN_IS(prep->backp(), NodeSel) || VN_IS(prep->backp(), Sel)
|| VN_IS(prep->backp(), StructSel)) {
|| VN_IS(prep->backp(), MemberSel) || VN_IS(prep->backp(), StructSel)) {
prep = VN_AS(prep->backp(), NodeExpr);
}
FileLine* const fl = nodep->fileline();

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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

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@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2025 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
class cls;
int m_field;
endclass
module t();
cls inst[2];
initial begin
// Loop (even just 1 iteration) is needed to reproduce the error
for (int i = 0; i < 2; ++i) begin
inst[i] = new();
inst[i].m_field = i;
end
for (int i = 0; i < 2; ++i) begin
if (inst[i].m_field != i) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule