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@ -40,6 +40,7 @@ Verilator 5.037 devel
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* Fix AstAssignW conversion (#5991) (#5992). [Ryszard Rozak, Antmicro Ltd.]
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* Fix const-bit-op-tree with single-bit masks (#5993) (#5998). [Yutetsu TAKATSUKASA]
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* Fix arithmetic right-shift by constants over 32 bits (#5994). [Zhen Yan]
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* Fix array bounds checking with class member selects (#5996) (#5997). [Krzysztof Starecki]
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* Fix checking for too-wide divide and modulus (#6003) (#6006). [Zhen Yan]
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* Fix folding of LteS in DfgPeephole (#6000) (#6004). [Geza Lore]
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* Fix slicing of AstExprStmt nodes (#6005). [Ryszard Rozak, Antmicro Ltd.]
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@ -102,7 +102,7 @@ class UnknownVisitor final : public VNVisitor {
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// Scan back to put the condlvalue above all selects (IE top of the lvalue)
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while (VN_IS(prep->backp(), NodeSel) || VN_IS(prep->backp(), Sel)
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|| VN_IS(prep->backp(), StructSel)) {
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|| VN_IS(prep->backp(), MemberSel) || VN_IS(prep->backp(), StructSel)) {
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prep = VN_AS(prep->backp(), NodeExpr);
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}
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FileLine* const fl = nodep->fileline();
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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class cls;
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int m_field;
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endclass
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module t();
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cls inst[2];
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initial begin
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// Loop (even just 1 iteration) is needed to reproduce the error
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for (int i = 0; i < 2; ++i) begin
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inst[i] = new();
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inst[i].m_field = i;
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end
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for (int i = 0; i < 2; ++i) begin
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if (inst[i].m_field != i) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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