Support SystemVerilog ==? and !=? operators.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@945 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
4a9bea6980
commit
5f6d69affd
4
Changes
4
Changes
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@ -3,6 +3,10 @@ Revision history for Verilator
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The contributors that suggested a given feature are shown in []. [by ...]
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indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.65***
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**** Support SystemVerilog ==? and !=? operators.
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* Verilator 3.652 6/21/2007
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**** Report as many warning types as possible before exiting.
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@ -4,7 +4,7 @@
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#
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# This file is part of Verilator.
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#
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# Author: Wilson Snyder <wsnyder@wsnyder.org> or <wsnyder@world.std.com>
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# Author: Wilson Snyder <wsnyder@wsnyder.org>
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#
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# Code available from: http://www.veripool.com/verilator
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#
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@ -1010,12 +1010,14 @@ Verilator currently has very minimal support for SystemVerilog. As
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SystemVerilog features enter common usage they will be added. Contact the
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author if a feature you need is missing.
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Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
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Verilator implements the full SystemVerilog 1800-2005 preprocessor,
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including function call-like preprocessor defines.
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Verilator supports $bits, $countones, $error, $fatal, $info, $isunknown,
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$onehot, $onehot0, $warning, always_comb, always_ff, always_latch,
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do-while, and final. It also supports .name and .* interconnection.
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Verilator supports ==? and !=? operators, $bits, $countones, $error,
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$fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb,
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always_ff, always_latch, do-while, and final.
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It also supports .name and .* interconnection.
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Verilator partially supports assert.
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@ -2606,6 +2606,39 @@ struct AstNeqCase : public AstNodeBiCom {
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
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};
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struct AstEqWild : public AstNodeBiop {
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// Note wildcard operator rhs differs from lhs
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AstEqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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width(1,1); }
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virtual ~AstEqWild() {}
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virtual AstType type() const { return AstType::EQWILD;}
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virtual AstNode* clone() { return new AstEqWild(*this); }
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virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opWildEq(lhs,rhs); }
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virtual string emitVerilog() { return "%k(%l %k==? %r)"; }
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virtual string emitOperator() { return "VL_EQ"; } // Until have 4 state anyways
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virtual string emitSimpleOperator() { return "=="; }
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virtual bool emitWordForm() { return true; }
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virtual bool cleanOut() {return true;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
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};
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struct AstNeqWild : public AstNodeBiop {
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AstNeqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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width(1,1); }
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virtual ~AstNeqWild() {}
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virtual AstType type() const { return AstType::NEQWILD;}
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virtual AstNode* clone() { return new AstNeqWild(*this); }
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virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
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virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opWildNeq(lhs,rhs); }
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virtual string emitVerilog() { return "%k(%l %k!=? %r)"; }
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virtual string emitOperator() { return "VL_NEQ"; } // Until have 4 state anyways
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virtual string emitSimpleOperator() { return "!="; }
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virtual bool emitWordForm() { return true; }
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virtual bool cleanOut() {return true;}
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virtual bool cleanLhs() {return true;} virtual bool cleanRhs() {return true;}
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virtual bool sizeMattersLhs() {return false;} virtual bool sizeMattersRhs() {return false;}
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};
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struct AstConcat : public AstNodeBiop {
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// If you're looking for {#{}}, see AstReplicate
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AstConcat(FileLine* fl, AstNode* lhsp, AstNode* rhsp) : AstNodeBiop(fl, lhsp, rhsp) {
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@ -1110,6 +1110,10 @@ private:
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TREEOP ("AstLogNot{$lhsp.castEqCase}", "AstNeqCase{$lhsp->op1p(),$lhsp->op2p()}");
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TREEOPV("AstNot {$lhsp.castNeqCase, $lhsp.width1}","AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOP ("AstLogNot{$lhsp.castNeqCase}", "AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOPV("AstNot {$lhsp.castEqWild, $lhsp.width1}","AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
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TREEOP ("AstLogNot{$lhsp.castEqWild}", "AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
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TREEOPV("AstNot {$lhsp.castNeqWild, $lhsp.width1}","AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOP ("AstLogNot{$lhsp.castNeqWild}", "AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOPV("AstNot {$lhsp.castEq, $lhsp.width1}", "AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOP ("AstLogNot{$lhsp.castEq}", "AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
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TREEOPV("AstNot {$lhsp.castNeq, $lhsp.width1}", "AstEq {$lhsp->op1p(),$lhsp->op2p()}");
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@ -1151,6 +1155,7 @@ private:
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TREEOP("AstXor {operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstEq {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)"); // We let X==X -> 1, although in a true 4-state sim it's X.
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TREEOP("AstEqCase {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstEqWild {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstGt {operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstGtS {operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstGte {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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@ -1161,6 +1166,7 @@ private:
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TREEOP("AstLteS {operandsSame($lhsp,,$rhsp)}", "replaceNum(nodep,1)");
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TREEOP("AstNeq {operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstNeqCase{operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstNeqWild{operandsSame($lhsp,,$rhsp)}", "replaceZero(nodep)");
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TREEOP("AstLogAnd {operandsSame($lhsp,,$rhsp), $lhsp.width1}", "replaceWLhs(nodep)");
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TREEOP("AstLogOr {operandsSame($lhsp,,$rhsp), $lhsp.width1}", "replaceWLhs(nodep)");
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///=== Verilog operators
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@ -814,6 +814,28 @@ last:
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return setSingleBits(outc);
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}
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V3Number& V3Number::opWildEq (const V3Number& lhs, const V3Number& rhs) {
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char outc = 1;
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for (int bit=0; bit<max(lhs.width(),rhs.width()); bit++) {
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if (!rhs.bitIsXZ(bit)
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&& lhs.bitIs(bit) != rhs.bitIs(bit)) { outc=0; goto last; }
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if (lhs.bitIsXZ(bit)) outc='x';
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}
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last:
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return setSingleBits(outc);
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}
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V3Number& V3Number::opWildNeq (const V3Number& lhs, const V3Number& rhs) {
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char outc = 0;
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for (int bit=0; bit<max(lhs.width(),rhs.width()); bit++) {
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if (!rhs.bitIsXZ(bit)
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&& lhs.bitIs(bit) != rhs.bitIs(bit)) { outc=1; goto last; }
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if (lhs.bitIsXZ(bit)) outc='x';
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}
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last:
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return setSingleBits(outc);
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}
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V3Number& V3Number::opGt (const V3Number& lhs, const V3Number& rhs) {
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// i op j, 1 bit return, max(L(lhs),L(rhs)) calculation, careful need to X/Z extend.
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char outc = 0;
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@ -174,6 +174,8 @@ public:
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V3Number& opCond (const V3Number& lhs, const V3Number& rhs, const V3Number& ths);
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V3Number& opCaseEq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opCaseNeq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opWildEq (const V3Number& lhs, const V3Number& rhs);
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V3Number& opWildNeq (const V3Number& lhs, const V3Number& rhs);
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// "standard" math
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V3Number& opNot (const V3Number& lhs);
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V3Number& opLogNot (const V3Number& lhs);
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@ -65,7 +65,10 @@ void test(string lhss, string op, string rhss, string exps) {
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else if (op=="<<") gotnum.opShiftL (lhnum,rhnum);
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else if (op=="==") gotnum.opEq (lhnum,rhnum);
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else if (op=="===") gotnum.opCaseEq (lhnum,rhnum);
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else if (op=="==?") gotnum.opWildEq (lhnum,rhnum);
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else if (op=="!=") gotnum.opNeq (lhnum,rhnum);
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else if (op=="!==") gotnum.opCaseNeq (lhnum,rhnum);
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else if (op=="!=?") gotnum.opWildNeq (lhnum,rhnum);
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else if (op=="<=") gotnum.opLte (lhnum,rhnum);
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else if (op==">=") gotnum.opGte (lhnum,rhnum);
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else if (op=="&&") gotnum.opLogAnd (lhnum,rhnum);
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@ -98,8 +98,10 @@ private:
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// ... (Though they should match. We don't check.)
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virtual void visit(AstEq* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstEqCase* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstEqWild* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstNeq* nodep, AstNUser*) { signed_Ou_Ix(nodep); }
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virtual void visit(AstNeqCase* nodep, AstNUser*){ signed_Ou_Ix(nodep); }
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virtual void visit(AstNeqWild* nodep, AstNUser*){ signed_Ou_Ix(nodep); }
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//=======
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// Signed: Output signed iff LHS signed; unary operator
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@ -106,6 +106,42 @@ private:
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newp->iterateChildren(*this);
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}
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}
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void visitEqNeqWild(AstNodeBiop* nodep) {
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UINFO(4," N/EQWILD->EQ "<<nodep<<endl);
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V3Const::constifyTree(nodep->lhsp());
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V3Const::constifyTree(nodep->rhsp());
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if (nodep->lhsp()->castConst() && nodep->rhsp()->castConst()) {
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// Both sides are constant, node can be constant
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V3Const::constifyTree(nodep); nodep=NULL;
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return;
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} else {
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AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
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AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
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AstNode* newp;
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if (!rhsp->castConst()) {
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nodep->v3error("Unsupported: RHS of ==? or !=? must be constant to be synthesizable"); // Says spec.
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// Replace with anything that won't cause more errors
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newp = new AstEq (nodep->fileline(), lhsp, rhsp);
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} else {
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// X or Z's become mask, ala case statements.
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V3Number nummask (rhsp->fileline(), rhsp->width());
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nummask.opBitsNonX(rhsp->castConst()->num());
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V3Number numval (rhsp->fileline(), rhsp->width());
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numval.opBitsOne (rhsp->castConst()->num());
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AstNode* and1p = new AstAnd(nodep->fileline(), lhsp,
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new AstConst(nodep->fileline(), nummask));
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AstNode* and2p = new AstConst(nodep->fileline(), numval);
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if (nodep->castEqWild())
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newp = new AstEq (nodep->fileline(), and1p, and2p);
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else newp = new AstNeq (nodep->fileline(), and1p, and2p);
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rhsp->deleteTree(); rhsp=NULL;
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}
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nodep->replaceWith(newp);
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nodep->deleteTree(); nodep=NULL;
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// Iterate tree now that we may have gotten rid of the compare
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newp->iterateChildren(*this);
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}
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}
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virtual void visit(AstEqCase* nodep, AstNUser*) {
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visitEqNeqCase(nodep);
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@ -113,6 +149,12 @@ private:
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virtual void visit(AstNeqCase* nodep, AstNUser*) {
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visitEqNeqCase(nodep);
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}
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virtual void visit(AstEqWild* nodep, AstNUser*) {
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visitEqNeqWild(nodep);
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}
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virtual void visit(AstNeqWild* nodep, AstNUser*) {
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visitEqNeqWild(nodep);
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}
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virtual void visit(AstIsUnknown* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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// Ahh, we're two state, so this is easy
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@ -117,6 +117,7 @@ private:
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void width_O1_L_Rlhs(AstNode* nodep, AstNUser* vup);
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virtual void visit(AstEq* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstEqCase* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstEqWild* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstGt* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstGtS* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstGte* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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@ -127,6 +128,7 @@ private:
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virtual void visit(AstLteS* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstNeq* nodep, AstNUser* vup) { width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstNeqCase* nodep, AstNUser* vup){ width_O1_L_Rlhs(nodep,vup); }
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virtual void visit(AstNeqWild* nodep, AstNUser* vup){ width_O1_L_Rlhs(nodep,vup); }
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// Widths: out width = lhs width = rhs width
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void width_Omax_L_Rlhs(AstNode* nodep, AstNUser* vup);
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@ -4,7 +4,7 @@
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//
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// This file is part of Verilator.
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//
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// Author: Wilson Snyder <wsnyder@wsnyder.org> or <wsnyder@world.std.com>
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// Author: Wilson Snyder <wsnyder@wsnyder.org>
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//
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// Code available from: http://www.veripool.com/verilator
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//
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@ -578,6 +578,12 @@ escid \\[^ \t\f\r\n]+
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"-:" {yylval.fileline = CRELINE(); return yP_MINUSCOLON;}
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}
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/* SystemVerilog Operators */
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<S05>{
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"==?" {yylval.fileline = CRELINE(); return yP_WILDEQUAL;}
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"!=?" {yylval.fileline = CRELINE(); return yP_WILDNOTEQUAL;}
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}
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/* PSL Operators */
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<PSL>{
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"{" {yylval.fileline = CRELINE(); return yPSL_BRA;} // Avoid parser hitting concatenate.
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@ -659,7 +665,7 @@ escid \\[^ \t\f\r\n]+
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<ATTRMODE>"*)" { yy_pop_state(); }
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<ATTRMODE>. { yymore(); }
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<ATTRMODE><<EOF>> { yyerror("EOF in (*");
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yyleng = 0; }
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yyleng = 0; yy_pop_state(); }
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/************************************************************************/
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/* Attributes */
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@ -269,7 +269,7 @@ class AstSenTree;
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%left<fileline> '^'
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%left<fileline> yP_XNOR
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%left<fileline> '&' yP_NAND
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%left<fileline> yP_EQUAL yP_NOTEQUAL yP_CASEEQUAL yP_CASENOTEQUAL
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%left<fileline> yP_EQUAL yP_NOTEQUAL yP_CASEEQUAL yP_CASENOTEQUAL yP_WILDEQUAL yP_WILDNOTEQUAL
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%left<fileline> '>' '<' yP_GTE yP_LTE
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%left<fileline> yP_SLEFT yP_SRIGHT yP_SSRIGHT
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%left<fileline> '+' '-'
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@ -912,6 +912,8 @@ exprNoStr: expr yP_OROR expr { $$ = new AstLogOr ($2,$1,$3); }
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| expr yP_NOTEQUAL expr { $$ = new AstNeq ($2,$1,$3); }
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| expr yP_CASEEQUAL expr { $$ = new AstEqCase ($2,$1,$3); }
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| expr yP_CASENOTEQUAL expr { $$ = new AstNeqCase ($2,$1,$3); }
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| expr yP_WILDEQUAL expr { $$ = new AstEqWild ($2,$1,$3); }
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| expr yP_WILDNOTEQUAL expr { $$ = new AstNeqWild ($2,$1,$3); }
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| expr '>' expr { $$ = new AstGt ($2,$1,$3); }
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| expr '<' expr { $$ = new AstLt ($2,$1,$3); }
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| expr yP_GTE expr { $$ = new AstGte ($2,$1,$3); }
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@ -1104,6 +1106,7 @@ specifyJunk: dlyTerm {} /* ignored */
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| yP_ANDAND {} | yP_GTE {} | yP_LTE {}
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| yP_EQUAL {} | yP_NOTEQUAL {}
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| yP_CASEEQUAL {} | yP_CASENOTEQUAL {}
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| yP_WILDEQUAL {} | yP_WILDNOTEQUAL {}
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| yP_XNOR {} | yP_NOR {} | yP_NAND {}
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| yP_OROR {}
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| yP_SLEFT {} | yP_SRIGHT {} | yP_SSRIGHT {}
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@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# General Public License or the Perl Artistic License.
|
||||
|
||||
compile (
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
// $Id$
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2007 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [3:0] out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[3:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[31:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {60'h0, out};
|
||||
|
||||
// What checksum will we end up with
|
||||
`define EXPECTED_SUM 64'h1a0d07009b6a30d2
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [31:0] in;
|
||||
output [3:0] out;
|
||||
|
||||
assign out[0] = in[3:0] ==? 4'b1001;
|
||||
assign out[1] = in[3:0] !=? 4'b1001;
|
||||
assign out[2] = in[3:0] ==? 4'bx01x;
|
||||
assign out[3] = in[3:0] !=? 4'bx01x;
|
||||
endmodule
|
||||
Loading…
Reference in New Issue