Add --compiler flags, and break up deep functions
git-svn-id: file://localhost/svn/verilator/trunk/verilator@913 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder
parent
a216c1e7e4
commit
6a6995187e
6
Changes
6
Changes
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@ -3,7 +3,11 @@ Revision history for Verilator
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The contributors that suggested a given feature are shown in []. [by ...]
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indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.64**
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* Verilator 3.65**
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** Add --compiler msvc option. This is now required when Verilated code
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is to be run through MSVC++. This also enables fixing error C1061,
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blocks nested too deeply. [Ralf Karge]
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** Add --lint-only option.
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@ -246,6 +246,27 @@ output files.
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Specifies C++ without SystemC output mode; see also --sc and --sp.
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=item --compiler I<compiler-name>
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Enables tunings and work-arounds for the specified C++ compiler.
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=over 4
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=item gcc
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Tune for Gnu C++, although generated code should work on almost any
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compliant C++ compiler. Currently the default.
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=item msvc
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Tune for Microsoft Visual C++. This may reduce execution speed as it
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enables several workarounds to avoid silly hardcoded limits in MSVC++.
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This includes breaking deeply nested parenthesized expressions into
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sub-expressions to avoid error C1009, and breaking deep blocks into
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functions to avoid error C1061.
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=back
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=item --coverage
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Enables all forms of coverage, alias for --coverage-line, --coverage-user
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@ -691,11 +712,13 @@ fast path, mostly code that is executed every cycle. OPT_SLOW specifies
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optimizations for slow-path files (plus tracing), which execute only
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rarely, yet take a long time to compile with optimization on. OPT
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specifies overall optimization and affects all compiles, including those
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OPT_FAST and OPT_SLOW affect. For best results, use OPT="-O2". Nearly the
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same results can be had with much better compile times with OPT_FAST="-O1
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-fstrict-aliasing". Unfortunately, using the optimizer with SystemC files
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can result in compiles taking several minutes. (The SystemC libraries have
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many little inlined functions that drive the compiler nuts.)
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OPT_FAST and OPT_SLOW affect. For best results, use OPT="-O2", and link
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with "-static". Nearly the same results can be had with much better
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compile times with OPT_FAST="-O1 -fstrict-aliasing".
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Unfortunately, using the optimizer with SystemC files can result in
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compiles taking several minutes. (The SystemC libraries have many little
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inlined functions that drive the compiler nuts.)
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For best results, use GCC 3.3 or newer. GCC 3.2 and earlier have
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optimization bugs around pointer aliasing detection, which can result in 2x
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@ -118,6 +118,7 @@ RAW_OBJS = \
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V3Dead.o \
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V3Delayed.o \
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V3Depth.o \
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V3DepthBlock.o \
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V3Descope.o \
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V3EmitC.o \
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V3EmitCSyms.o \
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@ -40,7 +40,6 @@
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#include "V3Ast.h"
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//######################################################################
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// Depth state, as a visitor of each AstNode
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class DepthVisitor : public AstNVisitor {
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private:
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@ -55,11 +54,6 @@ private:
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//int debug() { return 9; }
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// MSVC++ has a limit of 100 parenthesis. We have some operator
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// defines that use 2 parens. Thus we can't have a expression deeper
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// then 50 operators. We'll add some margin though.
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enum en { MAX_EXPR_DEPTH = 40 }; // Expressions deeper then this need temp
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// METHODS
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void createDeepTemp(AstNode* nodep) {
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UINFO(6," Deep "<<nodep<<endl);
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@ -114,13 +108,15 @@ private:
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virtual void visit(AstNodeTermop* nodep, AstNUser*) {
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}
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virtual void visit(AstNodeMath* nodep, AstNUser*) {
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m_depth++;
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// We have some operator defines that use 2 parens, so += 2.
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m_depth += 2;
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if (m_depth>m_maxdepth) m_maxdepth=m_depth;
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nodep->iterateChildren(*this);
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m_depth--;
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m_depth -= 2;
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if ((m_maxdepth-m_depth) > MAX_EXPR_DEPTH
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&& m_stmtp
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if (m_stmtp
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&& (v3Global.opt.compLimitParens() >= 1) // Else compiler doesn't need it
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&& (m_maxdepth-m_depth) > v3Global.opt.compLimitParens()
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&& !nodep->backp()->castNodeStmt() // Not much point if we're about to use it
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) {
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m_maxdepth = m_depth;
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@ -173,14 +169,10 @@ public:
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virtual ~DepthVisitor() {}
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};
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//----------------------------------------------------------------------
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// Top loop
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//######################################################################
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// Depth class functions
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void V3Depth::depthAll(AstNetlist* nodep) {
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UINFO(2,__FUNCTION__<<": "<<endl);
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// We must do it in bottom-up module
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DepthVisitor visitor (nodep);
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}
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@ -0,0 +1,139 @@
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// $Id$
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//*************************************************************************
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// DESCRIPTION: Verilator: Prevent very deep expressions
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//
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// Code available from: http://www.veripool.com/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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// V3DepthBlock's Transformations:
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//
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// Each module:
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// For each deep block, create cfunc including that block.
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include <stdio.h>
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#include <stdarg.h>
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#include <unistd.h>
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#include <algorithm>
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#include "V3Global.h"
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#include "V3DepthBlock.h"
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#include "V3Ast.h"
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#include "V3EmitCBase.h"
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//######################################################################
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class DepthBlockVisitor : public AstNVisitor {
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private:
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// NODE STATE
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// STATE
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AstModule* m_modp; // Current module
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AstCFunc* m_funcp; // Current function
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int m_depth; // How deep in an expression
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int m_deepNum; // How many functions made
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//int debug() { return 9; }
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// METHODS
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AstCFunc* createDeepFunc(AstNode* nodep) {
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AstNRelinker relinkHandle;
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nodep->unlinkFrBack(&relinkHandle);
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// Create function
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string name = m_funcp->name()+"__deep"+cvtToStr(++m_deepNum);
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AstCFunc* funcp = new AstCFunc(nodep->fileline(), name, NULL);
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funcp->argTypes(EmitCBaseVisitor::symClassVar());
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funcp->symProlog(true);
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funcp->slow(m_funcp->slow());
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funcp->addStmtsp(nodep);
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m_modp->addStmtp(funcp);
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// Call it at the point where the body was removed from
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AstCCall* callp = new AstCCall(nodep->fileline(), funcp);
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callp->argTypes("vlSymsp");
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UINFO(6," New "<<callp<<endl);
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//
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relinkHandle.relink(callp);
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return funcp;
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}
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// VISITORS
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virtual void visit(AstModule* nodep, AstNUser*) {
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UINFO(4," MOD "<<nodep<<endl);
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m_modp = nodep;
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m_deepNum = 0;
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nodep->iterateChildren(*this);
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}
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virtual void visit(AstCFunc* nodep, AstNUser*) {
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// We recurse into this.
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int lastDepth = m_depth;
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AstCFunc* lastFuncp = m_funcp;
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{
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m_depth = 0;
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m_funcp = nodep;
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nodep->iterateChildren(*this);
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}
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m_depth = lastDepth;
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m_funcp = lastFuncp;
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}
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void visitStmt(AstNodeStmt* nodep) {
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m_depth++;
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if (m_depth > v3Global.opt.compLimitBlocks()
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&& !nodep->castCCall()) { // Already done
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UINFO(4, "DeepBlocks "<<m_depth<<" "<<nodep<<endl);
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AstNode* backp = nodep->backp(); // Only for debug
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if (debug()>=9) backp->dumpTree(cout,"- pre : ");
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AstCFunc* funcp = createDeepFunc(nodep);
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funcp->accept(*this);
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if (debug()>=9) backp->dumpTree(cout,"- post: ");
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if (debug()>=9) funcp->dumpTree(cout,"- func: ");
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} else {
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nodep->iterateChildren(*this);
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}
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m_depth--;
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}
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virtual void visit(AstNodeStmt* nodep, AstNUser*) {
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visitStmt(nodep);
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}
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virtual void visit(AstNodeMath* nodep, AstNUser*) {} // Accelerate
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//--------------------
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// Default: Just iterate
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virtual void visit(AstVar* nodep, AstNUser*) {} // Don't hit varrefs under vars
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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public:
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// CONSTUCTORS
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DepthBlockVisitor(AstNode* nodep) {
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m_modp=NULL;
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m_depth=0;
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//
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nodep->accept(*this);
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}
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virtual ~DepthBlockVisitor() {}
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};
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//######################################################################
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// DepthBlock class functions
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void V3DepthBlock::depthBlockAll(AstNetlist* nodep) {
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UINFO(2,__FUNCTION__<<": "<<endl);
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DepthBlockVisitor visitor (nodep);
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}
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@ -0,0 +1,36 @@
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// $Id$ //-*- C++ -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Prevent very deep expressions
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//
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// Code available from: http://www.veripool.com/verilator
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//
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// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
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//
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//*************************************************************************
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//
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// Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// General Public License or the Perl Artistic License.
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//
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// Verilator is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//*************************************************************************
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#ifndef _V3DEPTHBLOCK_H_
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#define _V3DEPTHBLOCK_H_ 1
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3Error.h"
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#include "V3Ast.h"
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//============================================================================
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class V3DepthBlock {
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public:
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static void depthBlockAll(AstNetlist* nodep);
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};
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#endif // Guard
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@ -454,18 +454,20 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
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V3Error::pretendError(code, true);
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}
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}
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else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
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shift;
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if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
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else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
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else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
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else {
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fl->v3fatal("Unknown setting for -x-assign: "<<sw);
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}
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}
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else if ( !strcmp (sw, "-bin") && (i+1)<argc ) {
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shift; m_bin = argv[i];
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}
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else if ( !strcmp (sw, "-compiler") && (i+1)<argc) {
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shift;
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if (!strcmp (argv[i], "gcc")) {
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m_compLimitParens = 0;
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} else if (!strcmp (argv[i], "msvc")) {
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m_compLimitParens = 80; // 128, but allow some room
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m_compLimitBlocks = 80; // 128, but allow some room
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} else {
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fl->v3fatal("Unknown setting for --compiler: "<<argv[i]);
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}
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}
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else if ( !strcmp (sw, "-f") && (i+1)<argc ) {
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shift;
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parseOptsFile(fl, argv[i]);
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@ -480,6 +482,15 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
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shift; m_prefix = argv[i];
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if (m_modPrefix=="") m_modPrefix = m_prefix;
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}
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else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
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shift;
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if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
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else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
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else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
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else {
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fl->v3fatal("Unknown setting for --x-assign: "<<argv[i]);
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}
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}
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else if ( !strcmp (sw, "-y")) {
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shift; addIncDir (string (argv[i]));
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}
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@ -599,6 +610,9 @@ V3Options::V3Options() {
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m_unrollCount = 64;
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m_unrollStmts = 20;
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m_compLimitParens = 0;
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m_compLimitBlocks = 0;
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m_makeDir = "obj_dir";
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m_bin = "";
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m_flags = "";
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@ -77,6 +77,9 @@ class V3Options {
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int m_unrollCount; // main switch: --unroll-count
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int m_unrollStmts; // main switch: --unroll-stmts
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int m_compLimitBlocks; // compiler selection options
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int m_compLimitParens; // compiler selection options
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string m_bin; // main switch: --bin {binary}
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string m_flags; // main switch: -f {name}
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string m_top; // main switch: Top .v file name
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@ -162,6 +165,9 @@ class V3Options {
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int unrollCount() const { return m_unrollCount; }
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int unrollStmts() const { return m_unrollStmts; }
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int compLimitBlocks() const { return m_compLimitBlocks; }
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int compLimitParens() const { return m_compLimitParens; }
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string makeDir() const { return m_makeDir; }
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string prefix() const { return m_prefix; }
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string modPrefix() const { return m_modPrefix; }
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@ -169,6 +175,7 @@ class V3Options {
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const V3StringSet& cppFiles() const { return m_cppFiles; }
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const V3StringSet& libraryFiles() const { return m_libraryFiles; }
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// ACCESSORS (optimization options)
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bool oAcycSimp() const { return m_oAcycSimp; }
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bool oCase() const { return m_oCase; }
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@ -41,6 +41,7 @@
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#include "V3Dead.h"
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#include "V3Delayed.h"
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#include "V3Depth.h"
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#include "V3DepthBlock.h"
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#include "V3Descope.h"
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#include "V3EmitC.h"
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#include "V3EmitMk.h"
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@ -379,6 +380,12 @@ void process () {
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//--MODULE OPTIMIZATIONS--------------
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// Split deep blocks to appease MSVC++. Must be before Localize.
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if (v3Global.opt.compLimitBlocks()) {
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V3DepthBlock::depthBlockAll(v3Global.rootp());
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v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("deepblock.tree"));
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}
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// Move BLOCKTEMPS from class to local variables
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if (v3Global.opt.oLocalize()) {
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V3Localize::localizeAll(v3Global.rootp());
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@ -205,6 +205,7 @@ sub new {
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# Verilator
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'v3' => 0,
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verilator_flags => [split(/\s+/,"-cc")],
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verilator_flags2 => [],
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verilator_make_gcc => 1,
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verilated_debug => $Opt_Verilated_Debug,
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stdout_filename => undef, # Redirect stdout
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@ -338,6 +339,7 @@ sub compile {
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my @v3args = ("perl","../bin/verilator",
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"--prefix ".$self->{VM_PREFIX},
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@{$param{verilator_flags}},
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@{$param{verilator_flags2}},
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@{$param{v_flags}},
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@{$param{v_flags2}},
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$param{top_filename},
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|
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@ -0,0 +1,19 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
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#
|
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# General Public License or the Perl Artistic License.
|
||||
|
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compile (
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verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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@ -0,0 +1,342 @@
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// $Id$
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2007 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [33:0] in = crc[33:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [31:0] code; // From test of Test.v
|
||||
wire [4:0] len; // From test of Test.v
|
||||
wire next; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.next (next),
|
||||
.code (code[31:0]),
|
||||
.len (len[4:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[33:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {26'h0, next, len, code};
|
||||
|
||||
// What checksum will we end up with
|
||||
`define EXPECTED_SUM 64'h5537fa30d49bf865
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
next, code, len,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [33:0] in;
|
||||
output next;
|
||||
output [31:0] code;
|
||||
output [4:0] len;
|
||||
|
||||
/*AUTOREG*/
|
||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||
reg [31:0] code;
|
||||
reg [4:0] len;
|
||||
reg next;
|
||||
// End of automatics
|
||||
|
||||
/*
|
||||
#!/usr/bin/perl -w
|
||||
srand(5);
|
||||
my @used;
|
||||
pat:
|
||||
for (my $pat=0; 1; ) {
|
||||
last if $pat > 196;
|
||||
my $len = int($pat / (6 + $pat/50)) + 4; $len=20 if $len>20;
|
||||
my ($try, $val, $mask);
|
||||
try:
|
||||
for ($try=0; ; $try++) {
|
||||
next pat if $try>50;
|
||||
$val = 0;
|
||||
for (my $bit=23; $bit>(23-$len); $bit--) {
|
||||
my $b = int(rand()*2);
|
||||
$val |= (1<<$bit) if $b;
|
||||
}
|
||||
$mask = (1<<(23-$len+1))-1;
|
||||
for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
|
||||
next try if $used[$testval];
|
||||
}
|
||||
last;
|
||||
}
|
||||
my $bits = "";
|
||||
my $val2 = 0;
|
||||
for (my $bit=23; $bit>(23-$len); $bit--) {
|
||||
my $b = ($val & (1<<$bit));
|
||||
$bits .= $b?'1':'0';
|
||||
}
|
||||
for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
|
||||
$used[$testval]= 1; #printf "U%08x\n", $testval;
|
||||
}
|
||||
if ($try<90) {
|
||||
printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
|
||||
,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
|
||||
$pat++;
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
always @* begin
|
||||
next = 1'b0;
|
||||
code = 32'd0;
|
||||
len = 5'b11111;
|
||||
casez (in[31:8])
|
||||
24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
|
||||
24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
|
||||
24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
|
||||
24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
|
||||
24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
|
||||
24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
|
||||
24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
|
||||
24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
|
||||
24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
|
||||
24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
|
||||
24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
|
||||
24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
|
||||
24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
|
||||
24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
|
||||
24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
|
||||
24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
|
||||
24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
|
||||
24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
|
||||
24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
|
||||
24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
|
||||
24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
|
||||
24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
|
||||
24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
|
||||
24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
|
||||
24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
|
||||
24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
|
||||
24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
|
||||
24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
|
||||
24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
|
||||
24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
|
||||
24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
|
||||
24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
|
||||
24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
|
||||
24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
|
||||
24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
|
||||
24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
|
||||
24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
|
||||
24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
|
||||
24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
|
||||
24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
|
||||
24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
|
||||
24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
|
||||
24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
|
||||
24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
|
||||
24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
|
||||
24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
|
||||
24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
|
||||
24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
|
||||
24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
|
||||
24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
|
||||
24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
|
||||
24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
|
||||
24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
|
||||
24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
|
||||
24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
|
||||
24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
|
||||
24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
|
||||
24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
|
||||
24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
|
||||
24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
|
||||
24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
|
||||
24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
|
||||
24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
|
||||
24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
|
||||
24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
|
||||
24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
|
||||
24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
|
||||
24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
|
||||
24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
|
||||
24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
|
||||
24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
|
||||
24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
|
||||
24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
|
||||
24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
|
||||
24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
|
||||
24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
|
||||
24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
|
||||
24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
|
||||
24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
|
||||
24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
|
||||
24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
|
||||
24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
|
||||
24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
|
||||
24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
|
||||
24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
|
||||
24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
|
||||
24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
|
||||
24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
|
||||
24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
|
||||
24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
|
||||
24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
|
||||
24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
|
||||
24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
|
||||
24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
|
||||
24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
|
||||
24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
|
||||
24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
|
||||
24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
|
||||
24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
|
||||
24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
|
||||
24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
|
||||
24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
|
||||
24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
|
||||
24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
|
||||
24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
|
||||
24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
|
||||
24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
|
||||
24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
|
||||
24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
|
||||
24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
|
||||
24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
|
||||
24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
|
||||
24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
|
||||
24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
|
||||
24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
|
||||
24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
|
||||
24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
|
||||
24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
|
||||
24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
|
||||
24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
|
||||
24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
|
||||
24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
|
||||
24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
|
||||
24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
|
||||
24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
|
||||
24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
|
||||
24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
|
||||
24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
|
||||
24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
|
||||
24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
|
||||
24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
|
||||
24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
|
||||
24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
|
||||
24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
|
||||
24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
|
||||
24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
|
||||
24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
|
||||
24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
|
||||
24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
|
||||
24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
|
||||
24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
|
||||
24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
|
||||
24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
|
||||
24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
|
||||
24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
|
||||
24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
|
||||
24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
|
||||
24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
|
||||
24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
|
||||
24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
|
||||
24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
|
||||
24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
|
||||
24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
|
||||
24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
|
||||
24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
|
||||
24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
|
||||
24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
|
||||
24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
|
||||
24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
|
||||
24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
|
||||
24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
|
||||
24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
|
||||
24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
|
||||
24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
|
||||
24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
|
||||
24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
|
||||
24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
|
||||
24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
|
||||
24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
|
||||
24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
|
||||
24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
|
||||
24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
|
||||
24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
|
||||
24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
|
||||
24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
|
||||
24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
|
||||
24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
|
||||
24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
|
||||
24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
|
||||
24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
|
||||
24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
|
||||
24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
|
||||
24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
|
||||
24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
|
||||
24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
|
||||
24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
|
||||
24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
|
||||
24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
|
||||
24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
|
||||
24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
|
||||
24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
|
||||
24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
|
||||
24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
|
||||
24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
|
||||
24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
|
||||
24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
|
||||
24'b000000??????????????????: begin
|
||||
casez (in[33:32])
|
||||
2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197};
|
||||
2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198};
|
||||
2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199};
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
|
|||
# General Public License or the Perl Artistic License.
|
||||
|
||||
compile (
|
||||
verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test
|
||||
);
|
||||
|
||||
execute (
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
|
||||
# $Id$
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# General Public License or the Perl Artistic License.
|
||||
|
||||
compile (
|
||||
verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
// $Id$
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2007 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc=0;
|
||||
reg [63:0] crc;
|
||||
reg [63:0] sum;
|
||||
|
||||
// Take CRC data and apply to testblock inputs
|
||||
wire [31:0] in = crc[31:0];
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire [31:0] out; // From test of Test.v
|
||||
// End of automatics
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.out (out[31:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.in (in[31:0]));
|
||||
|
||||
// Aggregate outputs into a single result vector
|
||||
wire [63:0] result = {32'h0, out};
|
||||
|
||||
// What checksum will we end up with
|
||||
`define EXPECTED_SUM 64'h966e272fd829e672
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
||||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
crc <= 64'h5aef0c8d_d70a4497;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
sum <= 64'h0;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
||||
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
||||
if (sum !== `EXPECTED_SUM) $stop;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Test (/*AUTOARG*/
|
||||
// Outputs
|
||||
out,
|
||||
// Inputs
|
||||
clk, in
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [31:0] in;
|
||||
output [31:0] out;
|
||||
|
||||
/*AUTOREG*/
|
||||
// Beginning of automatic regs (for this module's undeclared outputs)
|
||||
reg [31:0] out;
|
||||
// End of automatics
|
||||
|
||||
`ifdef verilator
|
||||
`define dontOptimize $c1("1")
|
||||
`else
|
||||
`define dontOptimize 1'b1
|
||||
`endif
|
||||
|
||||
always @(posedge clk) begin
|
||||
out <= in;
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
|
||||
if (in[0])
|
||||
out <= ~in;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
|
|||
# General Public License or the Perl Artistic License.
|
||||
|
||||
compile (
|
||||
verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test
|
||||
);
|
||||
|
||||
execute (
|
||||
|
|
|
|||
Loading…
Reference in New Issue