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Change --l2-name default to remove 'v' naming.

This commit is contained in:
Wilson Snyder 2016-05-07 14:10:33 -04:00
parent 691de22ae3
commit 6b32bb635d
46 changed files with 105 additions and 105 deletions
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5
Changes
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@ -10,7 +10,10 @@ indicates the contributor was also the author of the fix; Thanks!
** Support command-line -G/+pvalue param overrides, bug1045. [Stefan Wallentowitz] ** Support command-line -G/+pvalue param overrides, bug1045. [Stefan Wallentowitz]
*** Add --l2-name option for controlling "v" naming, bug1050. *** The default l2 scope name is now the same as the top-level module, bug1050.
Use "--l2-name v" for the historical behavior.
*** Add --l2-name option for controlling "v" naming.
* Verilator 3.882 2016-03-01 * Verilator 3.882 2016-03-01

9
bin/verilator
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@ -789,11 +789,12 @@ in the Make variable LDLIBS, not LDFLAGS.)
=item --l2-name I<value> =item --l2-name I<value>
Instead of using the module name when showing Verilog scope, use the name Instead of using the module name when showing Verilog scope, use the name
provided. Default is "--l2-name v" and is used to standardize some wrapping provided. This allows simplifying some Verilator-embedded modeling
methodologies. methodologies. Default is an l2-name matching the top module. The default
before 3.884 was "--l2-name v"
The program "module t; initial $display("= %m"); endmodule" will show by For example, the program "module t; initial $display("%m"); endmodule" will
default "= t". With "--l2-name v" it will print "= v". show by default "t". With "--l2-name v" it will print "v".
=item --language I<value> =item --language I<value>

2
src/V3Options.cpp
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@ -1250,7 +1250,7 @@ V3Options::V3Options() {
m_makeDir = "obj_dir"; m_makeDir = "obj_dir";
m_bin = ""; m_bin = "";
m_flags = ""; m_flags = "";
m_l2Name = "v"; m_l2Name = "";
m_unusedRegexp = "*unused*"; m_unusedRegexp = "*unused*";
m_xAssign = "fast"; m_xAssign = "fast";

2
test_regress/t/t_assert_synth_full.pl
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@ -19,7 +19,7 @@ execute (
check_finished=>0, check_finished=>0,
fails=> $Self->{vlt}, fails=> $Self->{vlt},
expect=> expect=>
'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis full_case' '%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis full_case'
); );
ok(1); ok(1);

2
test_regress/t/t_assert_synth_parallel.pl
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@ -19,7 +19,7 @@ execute (
check_finished=>0, check_finished=>0,
fails => $Self->{v3}, fails => $Self->{v3},
expect=> expect=>
'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis parallel_case' '%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case'
); );
ok(1); ok(1);

6
test_regress/t/t_cdc_async_bad.pl
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@ -12,11 +12,11 @@ compile (
verilator_make_gcc => 0, verilator_make_gcc => 0,
fails => 1, fails => 1,
expect=> expect=>
'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst2_bad_n '%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst2_bad_n
%Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message.
%Warning-CDCRSTLOGIC: See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6a_bad_n %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6a_bad_n
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6b_bad_n %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6b_bad_n
%Error: Exiting due to.*', %Error: Exiting due to.*',
); );

12
test_regress/t/t_cover_line.out
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@ -77,7 +77,7 @@
input toggle; input toggle;
always @ (posedge clk) begin always @ (posedge clk) begin
%000002 if (toggle) begin %000002 if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2) // CHECK_COVER(-1,"top.t.a*",2)
// t.a1 and t.a2 collapse to a count of 2 // t.a1 and t.a2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -100,11 +100,11 @@
always @ (posedge clk) begin always @ (posedge clk) begin
%000000 if (0) begin %000000 if (0) begin
// CHECK_COVER(-1,"top.v.b*",0) // CHECK_COVER(-1,"top.t.b*",0)
// Make sure that we don't optimize away zero buckets // Make sure that we don't optimize away zero buckets
end end
%000002 if (toggle) begin %000002 if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2) // CHECK_COVER(-1,"top.t.b*",2)
// t.b1 and t.b2 collapse to a count of 2 // t.b1 and t.b2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -133,10 +133,10 @@
input external; input external;
begin begin
%000001 if (toggle) begin %000001 if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1) // CHECK_COVER(-1,"top.t.t1",1)
end end
%000001 if (external) begin %000001 if (external) begin
// CHECK_COVER(-1,"top.v.t1",1) // CHECK_COVER(-1,"top.t.t1",1)
$write("[%0t] Got external pulse\n", $time); $write("[%0t] Got external pulse\n", $time);
end end
end end
@ -161,7 +161,7 @@
// verilator coverage_on // verilator coverage_on
always @ (posedge clk) begin always @ (posedge clk) begin
%000001 if (toggle) begin %000001 if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1) // CHECK_COVER(-1,"top.t.o1",1)
// because under coverage_module_off // because under coverage_module_off
end end
end end

12
test_regress/t/t_cover_line.v
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@ -76,7 +76,7 @@ module alpha (/*AUTOARG*/
input toggle; input toggle;
always @ (posedge clk) begin always @ (posedge clk) begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2) // CHECK_COVER(-1,"top.t.a*",2)
// t.a1 and t.a2 collapse to a count of 2 // t.a1 and t.a2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -99,11 +99,11 @@ module beta (/*AUTOARG*/
always @ (posedge clk) begin always @ (posedge clk) begin
if (0) begin if (0) begin
// CHECK_COVER(-1,"top.v.b*",0) // CHECK_COVER(-1,"top.t.b*",0)
// Make sure that we don't optimize away zero buckets // Make sure that we don't optimize away zero buckets
end end
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2) // CHECK_COVER(-1,"top.t.b*",2)
// t.b1 and t.b2 collapse to a count of 2 // t.b1 and t.b2 collapse to a count of 2
end end
if (toggle) begin if (toggle) begin
@ -132,10 +132,10 @@ module tsk (/*AUTOARG*/
input external; input external;
begin begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1) // CHECK_COVER(-1,"top.t.t1",1)
end end
if (external) begin if (external) begin
// CHECK_COVER(-1,"top.v.t1",1) // CHECK_COVER(-1,"top.t.t1",1)
$write("[%0t] Got external pulse\n", $time); $write("[%0t] Got external pulse\n", $time);
end end
end end
@ -160,7 +160,7 @@ module off (/*AUTOARG*/
// verilator coverage_on // verilator coverage_on
always @ (posedge clk) begin always @ (posedge clk) begin
if (toggle) begin if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1) // CHECK_COVER(-1,"top.t.o1",1)
// because under coverage_module_off // because under coverage_module_off
end end
end end

2
test_regress/t/t_cover_sva_notflat.pl
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@ -20,7 +20,7 @@ execute (
# Allow old Perl format dump, or new binary dump # Allow old Perl format dump, or new binary dump
# Check that the hierarchy doesn't include __PVT__ # Check that the hierarchy doesn't include __PVT__
# Otherwise our coverage reports would look really ugly # Otherwise our coverage reports would look really ugly
file_grep ($Self->{coverage_filename}, qr/(top\.v\.sub.*.cyc_eq_5)/) file_grep ($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/)
if $Self->{vlt}; if $Self->{vlt};
ok(1); ok(1);

26
test_regress/t/t_cover_toggle.v
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@ -95,25 +95,25 @@ module alpha (/*AUTOARG*/
input clk; input clk;
input toggle; input toggle;
// CHECK_COVER(-1,"top.v.a*",4) // CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
input [7:0] cyc_copy; input [7:0] cyc_copy;
// CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22) // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
// CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10) // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
// CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4) // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
// CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2) // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
// CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0) // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
// CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0) // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
// CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0) // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
// CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0) // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
reg toggle_internal; reg toggle_internal;
// CHECK_COVER(-1,"top.v.a*",4) // CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
output reg toggle_up; output reg toggle_up;
// CHECK_COVER(-1,"top.v.a*",4) // CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2) // 2 edges * (t.a1 and t.a2)
always @ (posedge clk) begin always @ (posedge clk) begin
@ -130,7 +130,7 @@ module beta (/*AUTOARG*/
input clk; input clk;
input toggle_up; input toggle_up;
// CHECK_COVER(-1,"top.v.b1","toggle_up",2) // CHECK_COVER(-1,"top.t.b1","toggle_up",2)
/* verilator public_module */ /* verilator public_module */
@ -150,6 +150,6 @@ module off (/*AUTOARG*/
// verilator coverage_on // verilator coverage_on
input toggle; input toggle;
// CHECK_COVER(-1,"top.v.o1","toggle",2) // CHECK_COVER(-1,"top.t.o1","toggle",2)
endmodule endmodule

10
test_regress/t/t_display.pl
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@ -13,11 +13,11 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=>dequote( expect=>dequote(
q{[0] In top.v: Hi q{[0] In top.t: Hi
[0] In top.v.sub (sub) [0] In top.t.sub (sub)
[0] In top.v.sub.subblock (sub) [0] In top.t.sub.subblock (sub)
[0] In top.v.sub2 (sub2) [0] In top.t.sub2 (sub2)
[0] In top.v.sub2.subblock2 (sub2) [0] In top.t.sub2.subblock2 (sub2)
[0] Back \ Quote " [0] Back \ Quote "
[0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000
[0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000

10
test_regress/t/t_display_noopt.pl
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@ -16,11 +16,11 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=>dequote( expect=>dequote(
q{[0] In top.v: Hi q{[0] In top.t: Hi
[0] In top.v.sub (sub) [0] In top.t.sub (sub)
[0] In top.v.sub.subblock (sub) [0] In top.t.sub.subblock (sub)
[0] In top.v.sub2 (sub2) [0] In top.t.sub2 (sub2)
[0] In top.v.sub2.subblock2 (sub2) [0] In top.t.sub2.subblock2 (sub2)
[0] Back \ Quote " [0] Back \ Quote "
[0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000
[0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000

2
test_regress/t/t_dpi_accessors.cpp
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@ -90,7 +90,7 @@ checkResult (bool p,
int main () int main ()
{ {
Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut"); Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut");
svSetScope (svGetScopeFromName ("dut.v")); svSetScope (svGetScopeFromName ("dut.t"));
// evaluate the model with no signal changes to get the initial blocks // evaluate the model with no signal changes to get the initial blocks
// executed. // executed.

4
test_regress/t/t_dpi_display.pl
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@ -22,8 +22,8 @@ dpii_display_call: constant
dpii_display_call: constant_value dpii_display_call: constant_value
one10=0000000a one10=0000000a
dpii_display_call: one10=0000000a dpii_display_call: one10=0000000a
Mod=top.v 16= 10 10=0000000a Mod=top.t 16= 10 10=0000000a
dpii_display_call: Mod=top.v 16= 10 10=0000000a dpii_display_call: Mod=top.t 16= 10 10=0000000a
*-* All Finished *-* *-* All Finished *-*
}), }),
); );

2
test_regress/t/t_dpi_dup_bad.pl
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@ -11,7 +11,7 @@ compile (
v_flags2 => ["--lint-only"], v_flags2 => ["--lint-only"],
fails=>$Self->{v3}, fails=>$Self->{v3},
expect=> expect=>
'%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: v.oth_f_int2 '%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: t.oth_f_int2
%Error: t/t_dpi_dup_bad.v:\d+: ... New prototype: pure int dpii_fa_bit \(int, int\) %Error: t/t_dpi_dup_bad.v:\d+: ... New prototype: pure int dpii_fa_bit \(int, int\)
%Error: t/t_dpi_dup_bad.v:\d+: ... Original prototype: int dpii_fa_bit \(int\) %Error: t/t_dpi_dup_bad.v:\d+: ... Original prototype: int dpii_fa_bit \(int\)
%Error: Exiting due to .*' %Error: Exiting due to .*'

22
test_regress/t/t_gen_upscope.pl
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@ -13,17 +13,17 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=>quotemeta( expect=>quotemeta(
q{created tag with scope = top.v.b.gen[0].tag q{created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.v.b.gen[1].tag created tag with scope = top.t.b.gen[1].tag
created tag with scope = top.v.tag created tag with scope = top.t.tag
mod a has scope = top.v mod a has scope = top.t
mod a has tag = top.v.tag mod a has tag = top.t.tag
mod b has scope = top.v.b mod b has scope = top.t.b
mod b has tag = top.v.tag mod b has tag = top.t.tag
mod c has scope = top.v.b.gen[0].c mod c has scope = top.t.b.gen[0].c
mod c has tag = top.v.b.gen[0].tag mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.v.b.gen[1].c mod c has scope = top.t.b.gen[1].c
mod c has tag = top.v.b.gen[1].tag mod c has tag = top.t.b.gen[1].tag
*-* All Finished *-*}), *-* All Finished *-*}),
); );

2
test_regress/t/t_inst_tree_inl0_pub0.pl
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@ -16,7 +16,7 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=> expect=>
'\] (%m|.*v\.ps): Clocked '\] (%m|.*t\.ps): Clocked
', ',
); );

2
test_regress/t/t_inst_tree_inl0_pub1.pl
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@ -20,7 +20,7 @@ if ($Self->{vlt}) {
execute ( execute (
check_finished=>1, check_finished=>1,
expect=> expect=>
'\] (%m|.*v\.ps): Clocked '\] (%m|.*t\.ps): Clocked
', ',
); );

2
test_regress/t/t_inst_tree_inl1_pub0.pl
View File

@ -16,7 +16,7 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=> expect=>
'\] (%m|.*v\.ps): Clocked '\] (%m|.*t\.ps): Clocked
', ',
); );

2
test_regress/t/t_inst_tree_inl1_pub1.pl
View File

@ -16,7 +16,7 @@ compile (
execute ( execute (
check_finished=>1, check_finished=>1,
expect=> expect=>
'\] (%m|.*v\.ps): Clocked '\] (%m|.*t\.ps): Clocked
', ',
); );

2
test_regress/t/t_lint_multidriven_bad.pl
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@ -16,7 +16,7 @@ compile (
make_top_shell => 0, make_top_shell => 0,
make_main => 0, make_main => 0,
expect=> expect=>
'%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: v.mem '%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: t.mem
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of first driving block %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of first driving block
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of other driving block %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of other driving block
%Warning-MULTIDRIVEN: Use ".*" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: Use ".*" and lint_on around source to disable this message.

2
test_regress/t/t_order_loop_bad.pl
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@ -16,7 +16,7 @@ compile (
expect=> expect=>
'%Error: Circular logic when ordering code .* '%Error: Circular logic when ordering code .*
%Error: Example path: t/t_order_loop_bad.v:\d+: ALWAYS %Error: Example path: t/t_order_loop_bad.v:\d+: ALWAYS
%Error: Example path: t/t_order_loop_bad.v:\d+: v.ready %Error: Example path: t/t_order_loop_bad.v:\d+: t.ready
%Error: Example path: t/t_order_loop_bad.v:\d+: ACTIVE %Error: Example path: t/t_order_loop_bad.v:\d+: ACTIVE
.*', .*',
); );

4
test_regress/t/t_sys_sformat.v
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@ -49,11 +49,7 @@ module t;
$swrite(str2, "mod=%m"); $swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator
if (str2 !== "mod=top.v") $stop;
`else
if (str2 !== "mod=top.t") $stop; if (str2 !== "mod=top.t") $stop;
`endif
$swrite(str2, "lib=%l"); $swrite(str2, "lib=%l");
`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif `ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif

2
test_regress/t/t_trace_cat.out
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@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_renew.out
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@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_renew_0000.out
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@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_renew_0100.out
View File

@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_reopen.out
View File

@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_reopen_0000.out
View File

@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_cat_reopen_0100.out
View File

@ -5,7 +5,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$scope module v $end $scope module t $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$var wire 32 # cyc [31:0] $end $var wire 32 # cyc [31:0] $end
$upscope $end $upscope $end

2
test_regress/t/t_trace_complex.out
View File

@ -8,7 +8,7 @@ $timescale 1ns $end
$scope module $unit $end $scope module $unit $end
$var wire 1 # global_bit $end $var wire 1 # global_bit $end
$upscope $end $upscope $end
$scope module v $end $scope module t $end
$var wire 1 9 clk $end $var wire 1 9 clk $end
$var wire 32 $ cyc [31:0] $end $var wire 32 $ cyc [31:0] $end
$var real 64 3 v_arr_real(0) $end $var real 64 3 v_arr_real(0) $end

2
test_regress/t/t_trace_complex_params.out
View File

@ -8,7 +8,7 @@ $timescale 1ns $end
$scope module $unit $end $scope module $unit $end
$var wire 1 # global_bit $end $var wire 1 # global_bit $end
$upscope $end $upscope $end
$scope module v $end $scope module t $end
$var wire 1 9 clk $end $var wire 1 9 clk $end
$var wire 32 $ cyc [31:0] $end $var wire 32 $ cyc [31:0] $end
$var real 64 3 v_arr_real(0) $end $var real 64 3 v_arr_real(0) $end

2
test_regress/t/t_trace_complex_structs.out
View File

@ -8,7 +8,7 @@ $timescale 1ns $end
$scope module $unit $end $scope module $unit $end
$var wire 1 # global_bit $end $var wire 1 # global_bit $end
$upscope $end $upscope $end
$scope module v $end $scope module t $end
$var wire 1 D clk $end $var wire 1 D clk $end
$var wire 32 $ cyc [31:0] $end $var wire 32 $ cyc [31:0] $end
$var real 64 > v_arr_real(0) $end $var real 64 > v_arr_real(0) $end

2
test_regress/t/t_trace_public.out
View File

@ -6,7 +6,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 6 CLK $end $var wire 1 6 CLK $end
$var wire 1 7 RESET $end $var wire 1 7 RESET $end
$scope module v $end $scope module t $end
$var wire 1 6 CLK $end $var wire 1 6 CLK $end
$var wire 1 # RESET $end $var wire 1 # RESET $end
$var wire 32 $ val [31:0] $end $var wire 32 $ val [31:0] $end

2
test_regress/t/t_trace_public_func.cpp
View File

@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) {
top->CLK = (main_time/dt_2)%2; top->CLK = (main_time/dt_2)%2;
top->eval(); top->eval();
top->v->glbl->setGSR(main_time < 7); top->t->glbl->setGSR(main_time < 7);
tfp->dump((unsigned int)(main_time)); tfp->dump((unsigned int)(main_time));
++main_time; ++main_time;

2
test_regress/t/t_trace_public_sig.cpp
View File

@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) {
top->CLK = (main_time/dt_2)%2; top->CLK = (main_time/dt_2)%2;
top->eval(); top->eval();
top->v->glbl->GSR = (main_time < 7); top->t->glbl->GSR = (main_time < 7);
tfp->dump((unsigned int)(main_time)); tfp->dump((unsigned int)(main_time));
++main_time; ++main_time;

2
test_regress/t/t_uniqueif_fail1.pl
View File

@ -19,7 +19,7 @@ compile (
execute ( execute (
fails => $Self->{vlt}, fails => $Self->{vlt},
expect=> expect=>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop %Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*', .*',
); );

2
test_regress/t/t_uniqueif_fail2.pl
View File

@ -19,7 +19,7 @@ compile (
execute ( execute (
fails => $Self->{vlt}, fails => $Self->{vlt},
expect=> expect=>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop %Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*', .*',
); );

2
test_regress/t/t_uniqueif_fail3.pl
View File

@ -19,7 +19,7 @@ compile (
execute ( execute (
fails => $Self->{vlt}, fails => $Self->{vlt},
expect=> expect=>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop %Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*', .*',
); );

2
test_regress/t/t_uniqueif_fail4.pl
View File

@ -19,7 +19,7 @@ compile (
execute ( execute (
fails => $Self->{vlt}, fails => $Self->{vlt},
expect=> expect=>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop %Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*', .*',
); );

8
test_regress/t/t_unopt_combo_bad.pl
View File

@ -12,13 +12,13 @@ top_filename("t/t_unopt_combo.v");
compile ( compile (
fails=>$Self->{vlt}, fails=>$Self->{vlt},
expect=> expect=>
'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: v.c '%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: t.c
%Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message. %Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.b %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.b
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c
%Error: Exiting due to ' %Error: Exiting due to '
); );

2
test_regress/t/t_unoptflat_simple_2_bad.pl
View File

@ -16,7 +16,7 @@ compile (
fails => 1, fails => 1,
expect=> expect=>
'.*%Warning-UNOPTFLAT: Widest candidate vars to split: '.*%Warning-UNOPTFLAT: Widest candidate vars to split:
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: v.x, width 3, fanout \d+ %Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: t.x, width 3, fanout \d+
.*%Error: Exiting due to ', .*%Error: Exiting due to ',
); );

2
test_regress/t/t_var_escape.out
View File

@ -9,7 +9,7 @@ $timescale 1ns $end
$var wire 1 ' clk $end $var wire 1 ' clk $end
$var wire 1 ) double__underscore $end $var wire 1 ) double__underscore $end
$var wire 1 ( escaped_normal $end $var wire 1 ( escaped_normal $end
$scope module v $end $scope module t $end
$var wire 1 * 9num $end $var wire 1 * 9num $end
$var wire 32 & a0.cyc [31:0] $end $var wire 32 & a0.cyc [31:0] $end
$var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end

2
test_regress/t/t_var_nonamebegin.out
View File

@ -6,7 +6,7 @@ $timescale 1ns $end
$scope module top $end $scope module top $end
$var wire 1 # clk $end $var wire 1 # clk $end
$var wire 1 $ reset_l $end $var wire 1 $ reset_l $end
$scope module v $end $scope module t $end
$var wire 1 # clk $end $var wire 1 # clk $end
$var wire 1 % inmod $end $var wire 1 % inmod $end
$var wire 32 & rawmod [31:0] $end $var wire 32 & rawmod [31:0] $end

16
test_regress/t/t_var_nonamebegin.pl
View File

@ -13,14 +13,14 @@ compile (
execute ( execute (
expect=>quotemeta( expect=>quotemeta(
'ingen: {mod}.genblk1 top.v.genblk1 'ingen: {mod}.genblk1 top.t.genblk1
d3a: {mod}.d3nameda top.v.d3nameda d3a: {mod}.d3nameda top.t.d3nameda
b2: {mod} top.v b2: {mod} top.t
b3n: {mod}.b3named: top.v.b3named b3n: {mod}.b3named: top.t.b3named
b3: {mod} top.v b3: {mod} top.t
b4: {mod} top.v b4: {mod} top.t
t1 {mod}.tsk top.v t1 {mod}.tsk top.t
t2 {mod}.tsk top.v t2 {mod}.tsk top.t
*-* All Finished *-*'), *-* All Finished *-*'),
); );

2
test_verilated/sim_main.cpp
View File

@ -29,7 +29,7 @@ int main(int argc, char **argv, char **env) {
#define CYCTIME 10 #define CYCTIME 10
// Cycle the interpreter // Cycle the interpreter
while (main_time < CYCTIME*top->v->CYCLES) { while (main_time < CYCTIME*top->vgen->CYCLES) {
top->eval(); top->eval();
main_time += CYCTIME/2; main_time += CYCTIME/2;
top->clk = !top->clk; top->clk = !top->clk;