Tests: Rename t_extend_c_class
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@ -9,7 +9,7 @@
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import vltest_bootstrap
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test.scenarios('simulator')
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test.scenarios('vlt')
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test.compile()
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@ -9,7 +9,7 @@
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.scenarios('vlt')
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test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir])
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@ -14,7 +14,7 @@ module t (/*AUTOARG*/
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reg [31:0] in;
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wire [31:0] out;
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t_extend_class_v sub (.in(in), .out(out));
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t_extend_c_class_v sub (.in(in), .out(out));
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always @ (posedge clk) begin
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cyc <= cyc + 8'd1;
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@ -31,7 +31,7 @@ module t (/*AUTOARG*/
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end
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endmodule
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module t_extend_class_v (/*AUTOARG*/
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module t_extend_c_class_v (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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@ -47,11 +47,11 @@ module t_extend_class_v (/*AUTOARG*/
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end
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`systemc_header
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#include "t_extend_class_c.h" // Header for contained object
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#include "t_extend_c_class_c.h" // Header for contained object
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`systemc_interface
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t_extend_class_c* m_myobjp; // Pointer to object we are embedding
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t_extend_c_class_c* m_myobjp; // Pointer to object we are embedding
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`systemc_ctor
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m_myobjp = new t_extend_class_c(); // Construct contained object
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m_myobjp = new t_extend_c_class_c(); // Construct contained object
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`systemc_dtor
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delete m_myobjp; // Destruct contained object
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`verilog
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@ -6,11 +6,11 @@
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// any use, without warranty, 2006-2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class t_extend_class_c {
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class t_extend_c_class_c {
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public:
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// CONSTRUCTORS
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t_extend_class_c() = default;
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~t_extend_class_c() = default;
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t_extend_c_class_c() = default;
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~t_extend_c_class_c() = default;
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// METHODS
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// This function will be called from an instance created in Verilog
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uint32_t my_math(uint32_t in) { return in + 1; }
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