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Fix skipped genblocks in toggle coverage (#6010) 

Signed-off-by: Ryszard Rozak <rrozak@antmicro.com>
Co-authored-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
This commit is contained in:
Ryszard Rozak 2025-05-16 14:24:57 +02:00 committed by GitHub
parent 6b42d789af
commit 73b3648262
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
5 changed files with 155 additions and 6 deletions
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12
src/V3Coverage.cpp
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@ -351,7 +351,7 @@ class CoverageVisitor final : public VNVisitor {
// We'll do this, and make the if(...) coverinc later.
// Add signal to hold the old value
const string newvarname = "__Vtogcov__"s + nodep->shortName();
const string newvarname = "__Vtogcov__"s + m_beginHier + nodep->shortName();
FileLine* const fl_nowarn = new FileLine{nodep->fileline()};
fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
AstVar* const chgVarp
@ -371,10 +371,12 @@ class CoverageVisitor final : public VNVisitor {
}
void toggleVarBottom(const ToggleEnt& above, const AstVar* varp) {
const std::string hierPrefix
= (m_beginHier != "") ? AstNode::prettyName(m_beginHier) + "." : "";
AstCoverToggle* const newp = new AstCoverToggle{
varp->fileline(),
newCoverInc(varp->fileline(), "", "v_toggle", varp->name() + above.m_comment, "", 0,
""),
newCoverInc(varp->fileline(), "", "v_toggle",
hierPrefix + varp->name() + above.m_comment, "", 0, ""),
above.m_varRefp->cloneTree(true), above.m_chgRefp->cloneTree(true)};
m_modp->addStmtsp(newp);
}
@ -627,9 +629,9 @@ class CoverageVisitor final : public VNVisitor {
// covers the code in that line.)
VL_RESTORER(m_beginHier);
VL_RESTORER(m_inToggleOff);
m_inToggleOff = true;
if (!nodep->generate()) m_inToggleOff = true;
if (nodep->name() != "") {
m_beginHier = m_beginHier + (m_beginHier != "" ? "." : "") + nodep->name();
m_beginHier = m_beginHier + (m_beginHier != "" ? "__DOT__" : "") + nodep->name();
}
iterateChildren(nodep);
lineTrack(nodep);

37
test_regress/t/t_cover_toggle.out
View File

@ -70,6 +70,16 @@
.clk (clk),
.toggle (toggle));
param#(1) p1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
param#() p2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
%000001 reg [1:0] memory[121:110];
wire [1023:0] largeish = {992'h0, cyc};
@ -172,3 +182,30 @@
endmodule
module param #(parameter P = 2) (/*AUTOARG*/
// Inputs
clk, toggle
);
000019 input clk;
%000002 input toggle;
%000001 logic z;
for (genvar i = 0; i < P; i++) begin
%000002 logic x;
always @ (posedge clk) begin
x <= toggle;
end
for (genvar j = 0; j < 3; j++) begin
%000003 logic [2:0] y;
always @ (negedge clk) begin
y <= {toggle, ~toggle, 1'b1};
end
end
end
if (P > 1) begin : gen_1
assign z = 1;
end
endmodule

2
test_regress/t/t_cover_toggle.py
View File

@ -21,7 +21,7 @@ test.inline_checks()
test.file_grep_not(test.obj_dir + "/coverage.dat", "largeish")
if test.vlt_all:
test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 23)
test.file_grep(test.stats, r'Coverage, Toggle points joined\s+(\d+)', 27)
test.run(cmd=[
os.environ["VERILATOR_ROOT"] + "/bin/verilator_coverage",

37
test_regress/t/t_cover_toggle.v
View File

@ -69,6 +69,16 @@ module t (/*AUTOARG*/
.clk (clk),
.toggle (toggle));
param#(1) p1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
param#() p2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
reg [1:0] memory[121:110];
wire [1023:0] largeish = {992'h0, cyc};
@ -170,3 +180,30 @@ module off (/*AUTOARG*/
// CHECK_COVER(-1,"top.t.o1","toggle",2)
endmodule
module param #(parameter P = 2) (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
logic z;
for (genvar i = 0; i < P; i++) begin
logic x;
always @ (posedge clk) begin
x <= toggle;
end
for (genvar j = 0; j < 3; j++) begin
logic [2:0] y;
always @ (negedge clk) begin
y <= {toggle, ~toggle, 1'b1};
end
end
end
if (P > 1) begin : gen_1
assign z = 1;
end
endmodule

73
test_regress/t/t_cover_toggle__points.out
View File

@ -87,6 +87,16 @@
.clk (clk),
.toggle (toggle));
param#(1) p1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
param#() p2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
%000001 reg [1:0] memory[121:110];
-000001 point: comment=memory[110][0] hier=top.t
-000000 point: comment=memory[110][1] hier=top.t
@ -228,3 +238,66 @@
endmodule
module param #(parameter P = 2) (/*AUTOARG*/
// Inputs
clk, toggle
);
000019 input clk;
+000019 point: comment=clk hier=top.t.p2
+000019 point: comment=clk hier=top.t.p1
%000002 input toggle;
-000002 point: comment=toggle hier=top.t.p2
-000002 point: comment=toggle hier=top.t.p1
%000001 logic z;
-000001 point: comment=z hier=top.t.p2
-000000 point: comment=z hier=top.t.p1
for (genvar i = 0; i < P; i++) begin
%000002 logic x;
-000002 point: comment=genblk1[0].x hier=top.t.p2
-000002 point: comment=genblk1[1].x hier=top.t.p2
-000002 point: comment=genblk1[0].x hier=top.t.p1
always @ (posedge clk) begin
x <= toggle;
end
for (genvar j = 0; j < 3; j++) begin
%000003 logic [2:0] y;
-000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p2
-000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p2
-000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p2
-000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p2
-000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p2
-000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p2
-000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p2
-000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p2
-000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p2
-000001 point: comment=genblk1[1].genblk1[0].y[0] hier=top.t.p2
-000003 point: comment=genblk1[1].genblk1[0].y[1] hier=top.t.p2
-000002 point: comment=genblk1[1].genblk1[0].y[2] hier=top.t.p2
-000001 point: comment=genblk1[1].genblk1[1].y[0] hier=top.t.p2
-000003 point: comment=genblk1[1].genblk1[1].y[1] hier=top.t.p2
-000002 point: comment=genblk1[1].genblk1[1].y[2] hier=top.t.p2
-000001 point: comment=genblk1[1].genblk1[2].y[0] hier=top.t.p2
-000003 point: comment=genblk1[1].genblk1[2].y[1] hier=top.t.p2
-000002 point: comment=genblk1[1].genblk1[2].y[2] hier=top.t.p2
-000001 point: comment=genblk1[0].genblk1[0].y[0] hier=top.t.p1
-000003 point: comment=genblk1[0].genblk1[0].y[1] hier=top.t.p1
-000002 point: comment=genblk1[0].genblk1[0].y[2] hier=top.t.p1
-000001 point: comment=genblk1[0].genblk1[1].y[0] hier=top.t.p1
-000003 point: comment=genblk1[0].genblk1[1].y[1] hier=top.t.p1
-000002 point: comment=genblk1[0].genblk1[1].y[2] hier=top.t.p1
-000001 point: comment=genblk1[0].genblk1[2].y[0] hier=top.t.p1
-000003 point: comment=genblk1[0].genblk1[2].y[1] hier=top.t.p1
-000002 point: comment=genblk1[0].genblk1[2].y[2] hier=top.t.p1
always @ (negedge clk) begin
y <= {toggle, ~toggle, 1'b1};
end
end
end
if (P > 1) begin : gen_1
assign z = 1;
end
endmodule