Merge 7260711d6b into fa62cd3486

test_regress/t/t_covergroup_unsup.py

@@ -9,10 +9,14 @@
 
 import vltest_bootstrap
 
-test.scenarios('vlt')
+test.scenarios('simulator')
 
-test.lint(expect_filename=test.golden_filename,
-          verilator_flags2=['--assert --error-limit 1000'],
-          fails=True)
+if test.vlt_all:
+    test.lint(expect_filename=test.golden_filename,
+              verilator_flags2=['--assert --error-limit 1000'],
+              fails=True)
+else:
+    test.compile()
+    test.execute()
 
 test.passes()

test_regress/t/t_covergroup_unsup.v

@@ -10,6 +10,7 @@ module t (/*AUTOARG*/
    );
 
    input clk;
+   logic rst;
    int   a;
    int   b;
    logic c;
@@ -22,6 +23,12 @@ module t (/*AUTOARG*/
    // NOTE this grammar hasn't been checked with other simulators,
    // is here just to avoid uncovered code lines in the grammar.
 
+   function automatic void funca();
+   endfunction
+
+   function automatic void funcb();
+   endfunction
+
    covergroup cg_empty;
    endgroup
 
@@ -31,7 +38,7 @@ module t (/*AUTOARG*/
       type_option.comment = "type_option_comment";  // cg, cp, cross
       type_option.strobe = 0;  // cg
       type_option.merge_instances = 1;  // cg
-      type_option.distribuge_first = 1;  // cg
+      type_option.distribute_first = 1;  // cg
       option.name = "the_name";  // cg
       option.weight = 1;  // cg, cp, cross
       option.goal = 98;  // cg, cp, cross
@@ -143,7 +150,7 @@ module t (/*AUTOARG*/
          bins bin_nd = ! binsof(a) intersect { b };
 
          bins bin_e = with (a);
-         bins bin_e = ! with (a);
+         bins bin_not_e = ! with (a);
 
          bins bin_par = (binsof(a));
          bins bin_and = binsof(a) && binsof(b);