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Fix parsing module #(parameter x,y) declarations. 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@954 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-09-11 13:35:02 +00:00
parent fb2cb3c49d
commit 7990e5d4b1
3 changed files with 25 additions and 19 deletions
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2
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@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Don't exit early if many warnings but no errors are found. [Stan Mayer]
**** Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov]
* Verilator 3.653 8/1/2007
**** Support SystemVerilog ==? and !=? operators.

20
src/verilog.y
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@ -290,7 +290,7 @@ class AstSenTree;
%type<nodep> modPortsE portList port
%type<nodep> portV2kArgs portV2kList portV2kSecond portV2kSig
%type<nodep> portV2kDecl ioDecl varDecl
%type<nodep> modParDecl modParList modParE
%type<nodep> modParArgs modParSecond modParDecl modParList modParE
%type<nodep> modItem modItemList modItemListE modOrGenItem
%type<nodep> genItem genItemList genItemBegin genItemBlock genTopBlock genCaseListE genCaseList
%type<nodep> dlyTerm
@ -375,12 +375,20 @@ modHdr: yMODULE { V3Parse::s_trace=v3Global.opt.trace();}
modParE: /* empty */ { $$ = NULL; }
| '#' '(' ')' { $$ = NULL; }
| '#' '(' modParList ')' { $$ = $3; }
| '#' '(' modParList ';' ')' { $$ = $3; }
| '#' '(' modParArgs ')' { $$ = $3; }
;
modParList: modParDecl { $$ = $1; }
| modParList ';' modParDecl { $$ = $1->addNext($3); }
modParArgs: modParDecl { $$ = $1; }
| modParDecl ',' modParList { $$ = $1->addNext($3); }
;
modParList: modParSecond { $$ = $1; }
| modParList ',' modParSecond { $$ = $1->addNext($3); }
;
// Called only after a comma in a v2k list, to allow parsing "parameter a,b, parameter x"
modParSecond: modParDecl { $$ = $1; }
| param { $$ = $1; }
;
modPortsE: /* empty */ { $$ = NULL; }
@ -440,7 +448,7 @@ varDecl: varRESET varReg varSignedE regrangeE regsigList ';' { $$ = $5; }
| varRESET varGenVar varSignedE regsigList ';' { $$ = $4; }
;
modParDecl: varRESET varGParam varSignedE regrangeE paramList { $$ = $5; } /* No semicolon*/
modParDecl: varRESET varGParam varSignedE regrangeE param { $$ = $5; }
;
varRESET: /* empty */ { VARRESET(); }

22
test_regress/t/t_param_named.v
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@ -1,4 +1,4 @@
// $Id:$
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
@ -11,7 +11,10 @@ module t (/*AUTOARG*/
parameter PAR = 3;
input clk;
`ifdef verilator
// Else it becomes a localparam, per IEEE 4.10.1, but we don't check it
defparam m3.FROMDEFP = 19;
`endif
m3 #(.P3(PAR),
.P2(2))
@ -29,14 +32,12 @@ module t (/*AUTOARG*/
endmodule
module m3
`ifdef verilator
#(
parameter UNCH = 99;
parameter P1 = 10;
parameter UNCH = 99,
parameter P1 = 10,
parameter P2 = 20,
P3 = 30;
P3 = 30
)
`endif
(/*AUTOARG*/
// Inputs
clk
@ -44,13 +45,6 @@ module m3
input clk;
localparam LOC = 13;
`ifndef verilator // Vcs not compliant yet
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
`endif
parameter FROMDEFP = 11;
initial begin
@ -61,6 +55,8 @@ module m3
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
`ifdef verilator
if (FROMDEFP !== 19) $stop;
`endif
end
endmodule