Add check for `let` misused in statement context (#5733).

Changes

@@ -15,6 +15,7 @@ Verilator 5.035 devel
 
 * Change `--output-groups` to default to value of `--build-jobs` (#5751).
   Those using build farms may need to now use `--output-groups 0` or otherwise.
+* Add check for `let` misused in statement context (#5733).
 * Add used language to `--preproc-resolve` output (#5795). [Kamil Rakoczy, Antmicro Ltd.]
 * Fix reset of automatic function variables (#5747). [Augustin Fabre]
 

src/V3AstNodeOther.h

@@ -2306,7 +2306,7 @@ public:
 class AstLet final : public AstNodeFTask {
     // Verilog "let" statement
     // Parents: MODULE
-    // stmtp is always a StmtExpr as Let always returns AstNodeExpr
+    // stmtp list first item is returned StmtExpr, as Let always returns AstNodeExpr
 public:
     AstLet(FileLine* fl, const string& name)
         : ASTGEN_SUPER_Let(fl, name, nullptr) {}

src/V3LinkResolve.cpp

@@ -189,6 +189,9 @@ class LinkResolveVisitor final : public VNVisitor {
                 return;
             }
             letp->user2(true);
+            if (VN_IS(nodep->backp(), StmtExpr)) {
+                nodep->v3error("Expected statement, not let substitution " << letp->prettyNameQ());
+            }
             // letp->dumpTree("-let-let ");
             // nodep->dumpTree("-let-ref ");
             AstStmtExpr* const letStmtp = VN_AS(letp->stmtsp(), StmtExpr);

test_regress/t/t_let_stmt_bad.out

@@ -0,0 +1,4 @@
+%Error: t/t_let_stmt_bad.v:15:14: Expected statement, not let substitution 'letf'
+   15 |           0: letf(0);  
+      |              ^~~~
+%Error: Exiting due to

test_regress/t/t_let_stmt_bad.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()

test_regress/t/t_let_stmt_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+    wire clk;
+
+    let letf(x) = (x << 1);
+
+    always @(posedge clk) begin
+        case (0)
+          0: letf(0); // Bad, need a statement
+        endcase
+    end
+
+endmodule