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Add `systemc_header_post

This commit is contained in:
Wilson Snyder 2025-03-28 22:24:39 -04:00
parent b4ef6ce860
commit 844448655e
8 changed files with 32 additions and 5 deletions
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9
docs/guide/extensions.rst
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@ -111,6 +111,15 @@ or "`ifdef`"'s may break other tools.
class/endclass pair. Despite the name of this macro, this also works in
pure C++ code.
.. option:: `systemc_header_post
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the output .h file's header after the class definition.
Must be placed as a module or class item, e.g., directly inside a
module/endmodule or class/endclass pair. Despite the name of this macro,
this also works in pure C++ code.
.. option:: `systemc_class_name
Inside one of the :option:`\`systemc_... <\`systemc_header>` text

4
docs/guide/languages.rst
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@ -396,8 +396,8 @@ This section describes specific limitations for each language keyword.
\`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords,
\`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef,
\`ifndef, \`include, \`line, \`systemc_ctor, \`systemc_dtor,
\`systemc_header, \`systemc_imp_header, \`systemc_implementation,
\`systemc_interface, \`undef, \`verilog
\`systemc_header, \`systemc_header_post, \`systemc_imp_header,
\`systemc_implementation, \`systemc_interface, \`undef, \`verilog
|cmdslong1|
Fully supported.

8
src/V3AstNodeOther.h
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@ -3898,6 +3898,14 @@ public:
bool isPure() override { return false; } // SPECIAL: User may order w/other sigs
bool isOutputter() override { return true; }
};
class AstScHdrPost final : public AstNodeText {
public:
AstScHdrPost(FileLine* fl, const string& textp)
: ASTGEN_SUPER_ScHdrPost(fl, textp) {}
ASTGEN_MEMBERS_AstScHdrPost;
bool isPure() override { return false; } // SPECIAL: User may order w/other sigs
bool isOutputter() override { return true; }
};
class AstScImp final : public AstNodeText {
public:
AstScImp(FileLine* fl, const string& textp)

1
src/V3EmitCHeaders.cpp
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@ -595,6 +595,7 @@ class EmitCHeader final : public EmitCConstInit {
// Emit out of class function declarations
puts("\n");
emitFuncDecls(modp, /* inClassBody: */ false);
emitTextSection(modp, VNType::atScHdrPost);
}
explicit EmitCHeader(const AstNodeModule* modp) {

1
src/V3LanguageWords.h
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@ -238,6 +238,7 @@ inline void V3LanguageWords::Singleton::init() {
addKwd("`systemc_ctor", "Verilator preprocessor directive");
addKwd("`systemc_dtor", "Verilator preprocessor directive");
addKwd("`systemc_header", "Verilator preprocessor directive");
addKwd("`systemc_header_post", "Verilator preprocessor directive");
addKwd("`systemc_imp_header", "Verilator preprocessor directive");
addKwd("`systemc_implementation", "Verilator preprocessor directive");
addKwd("`systemc_interface", "Verilator preprocessor directive");

8
src/verilog.l
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@ -81,7 +81,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
%s V95 V01NC V01C V05 S05 S09 S12 S17 S23
%s ATTRMODE QQQ STRING TABLE
%s VA5 SAX VLT
%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
%s SYSCHDR SYSCHDRP SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
ws [ \t\f\r]+
wsnr [ \t\f]+
@ -1028,7 +1028,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Common for all SYSC header states */
/* OPTIMIZE: we return one per line, make it one for the entire block */
/* If add to this list also add to V3LanguageWords.h */
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{
<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,S23,SAX,VLT,SYSCHDR,SYSCHDRP,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{
"`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
"`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; }
@ -1100,6 +1100,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"`systemc_ctor" { FL_FWD; BEGIN SYSCCTOR; FL_BRK; }
"`systemc_dtor" { FL_FWD; BEGIN SYSCDTOR; FL_BRK; }
"`systemc_header" { FL_FWD; BEGIN SYSCHDR; FL_BRK; }
"`systemc_header_post" { FL_FWD; BEGIN SYSCHDRP; FL_BRK; }
"`systemc_imp_header" { FL_FWD; BEGIN SYSCIMPH; FL_BRK; }
"`systemc_implementation" { FL_FWD; BEGIN SYSCIMP; FL_BRK; }
"`systemc_interface" { FL_FWD; BEGIN SYSCINT; FL_BRK; }
@ -1115,6 +1116,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
}
<SYSCHDR>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCHDR; }
<SYSCHDRP>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCHDRP; }
<SYSCINT>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCINT; }
<SYSCIMP>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMP; }
<SYSCIMPH>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMPH; }
@ -1122,7 +1124,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
<SYSCDTOR>[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCDTOR; }
/* Pick up text-type data */
<SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{
<SYSCHDR,SYSCHDRP,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR>{
{wsnr}* { yymore(); }
{crnl} { yymore(); }
}

2
src/verilog.y
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@ -453,6 +453,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<strp> yaSCCTOR "`systemc_ctor block"
%token<strp> yaSCDTOR "`systemc_dtor block"
%token<strp> yaSCHDR "`systemc_header block"
%token<strp> yaSCHDRP "`systemc_header_post block"
%token<strp> yaSCIMP "`systemc_implementation block"
%token<strp> yaSCIMPH "`systemc_imp_header block"
%token<strp> yaSCINT "`systemc_interface block"
@ -2738,6 +2739,7 @@ non_port_module_item<nodep>: // ==IEEE: non_port_module_item
vlScBlock<nodep>: // Verilator-specific `systemc_* blocks
yaSCHDR { $$ = new AstScHdr{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
| yaSCHDRP { $$ = new AstScHdrPost{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
| yaSCINT { $$ = new AstScInt{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
| yaSCIMP { $$ = new AstScImp{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
| yaSCIMPH { $$ = new AstScImpHdr{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }

4
test_regress/t/t_extend_class.v
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@ -12,6 +12,8 @@ class Cls;
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_header_post
inline void `systemc_class_name::my_inline_function() {}
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
@ -22,6 +24,7 @@ class Cls;
return 1;
}
static void my_imp_function();
static void my_inline_function();
`systemc_imp_header
#define DID_IMP_HEADER 1
@ -49,6 +52,7 @@ module t (/*AUTOARG*/);
c = new;
i = $c(c, "->my_function()");
$c(c, "->my_imp_function();");
$c(c, "->my_inline_function();");
c = null; // Causes destruction and All Finished
$finish;
end