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Update src/verilog.y, fix formatting 

Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Artur Bieniek 2025-07-15 11:28:40 +02:00 committed by GitHub
parent 8d487f828a
commit 86f36c95c7
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1 changed files with 5 additions and 5 deletions
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@ -7528,11 +7528,11 @@ class_item<nodep>: // ==IEEE: class_item
| timeunits_declaration { $$ = $1; }
| covergroup_declaration
{
const string cgName = $1->name();
$1->name("__vlAnonCG_" + cgName);
AstVar* const newp = new AstVar{$<fl>1, VVarType::VAR, cgName, VFlagChildDType{}, new AstRefDType($<fl>1, $1->name())};
$$ = addNextNull($1, newp);
}
const string cgName = $1->name();
$1->name("__vlAnonCG_" + cgName);
AstVar* const newp = new AstVar{$<fl>1, VVarType::VAR, cgName, VFlagChildDType{}, new AstRefDType($<fl>1, $1->name())};
$$ = addNextNull($1, newp);
}
// // local_parameter_declaration under parameter_declaration
| parameter_declaration ';' { $$ = $1; }
| ';' { $$ = nullptr; }