parent
e171463fa2
commit
87d856339f
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@ -159,6 +159,7 @@ Nandu Raj
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Nathan Graybeal
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Nathan Kohagen
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Nathan Myers
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Nick Brereton
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Nolan Poe
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Oleh Maksymenko
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Patrick Stewart
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@ -893,6 +893,13 @@ class LinkParseVisitor final : public VNVisitor {
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}
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iterateChildren(nodep);
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}
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void visit(AstPackageImport* nodep) override {
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cleanFileline(nodep);
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if (m_modp && !m_ftaskp && VN_IS(m_modp, Class)) {
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nodep->v3error("Import statement directly within a class scope is illegal");
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}
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iterateChildren(nodep);
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}
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void visit(AstNode* nodep) override {
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// Default: Just iterate
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@ -0,0 +1,4 @@
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%Error: t/t_class_scope_import.v:11:14: Import statement directly within a class scope is illegal
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11 | import pkg::*;
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| ^~
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%Error: Exiting due to
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@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=True, expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,15 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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endpackage
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class genericClass;
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import pkg::*;
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endclass
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module tb_top();
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endmodule
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@ -262,23 +262,22 @@ interface z_if;
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);
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endinterface
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class z_txn_class;
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import z_pkg::*;
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rand txn_type_t req_txn_type;
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rand cid_t cid;
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rand sid_t sid;
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rand ctag_t ctag;
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rand stag_t stag;
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rand size_t size;
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rand address_t address;
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rand state_t state1;
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rand state_t state2;
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rand state_t state3;
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rand z_pkg::txn_type_t req_txn_type;
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rand z_pkg::cid_t cid;
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rand z_pkg::sid_t sid;
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rand z_pkg::ctag_t ctag;
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rand z_pkg::stag_t stag;
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rand z_pkg::size_t size;
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rand z_pkg::address_t address;
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rand z_pkg::state_t state1;
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rand z_pkg::state_t state2;
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rand z_pkg::state_t state3;
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rand logic f1;
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rand logic f2;
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rand logic f3;
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rand logic f4;
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data_t data[];
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mask_t mask[];
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z_pkg::data_t data[];
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z_pkg::mask_t mask[];
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bit corrupt[];
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logic [2:0] req_opcode;
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endclass
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