Add `--trace-saif` for SAIF power traces (#5812)

bin/verilator

@@ -480,6 +480,7 @@ detailed descriptions of these arguments.
     --trace-max-array <depth>   Maximum array depth for tracing
     --trace-max-width <width>   Maximum bit width for tracing
     --trace-params              Enable tracing of parameters
+    --trace-saif                Enable SAIF file creation
     --trace-structs             Enable tracing structure names
     --trace-threads <threads>   Enable FST waveform creation on separate threads
     --no-trace-top              Do not emit traces for signals in the top module generated by verilator

ci/ci-script.bash

@@ -98,6 +98,8 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
      export VERILATOR_ROOT="$RELOC_DIR/relocated-install/share/verilator"
      TEST_REGRESS="$RELOC_DIR/test_regress"
      mv test_regress "$TEST_REGRESS"
+     NODIST="$RELOC_DIR/nodist"
+     mv nodist "$NODIST"
      # Feeling brave?
      find . -delete
      ls -la .

docs/CONTRIBUTORS

@@ -148,6 +148,7 @@ Marlon James
 Marshal Qiao
 Martin Schmidt
 Martin Stadler
+Mateusz Gancarz
 Matthew Ballance
 Michael Bikovitsky
 Michael Killough

docs/guide/exe_verilator.rst

@@ -1626,6 +1626,11 @@ Summary:
 
    Disable tracing of parameters.
 
+.. option:: --trace-saif
+
+   Enable SAIF tracing in the model. This overrides :vlopt:`--trace`.
+   Specification of this format can be found in `IEEE 1801-2018<https://ieeexplore.ieee.org/document/8686430>`_ (see Annex I).
+
 .. option:: --trace-structs
 
    Enable tracing to show the name of packed structure, union, and packed

docs/guide/verilating.rst

@@ -462,6 +462,11 @@ SystemC include directories and link to the SystemC libraries.
    Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS
    --trace-fst".
 
+.. describe:: TRACE_SAIF
+
+   Optional. Enables SAIF tracing if present, equivalent to "VERILATOR_ARGS
+   --trace-saif".
+
 .. describe:: VERILATOR_ARGS
 
    Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`

include/verilated.mk.in

@@ -90,6 +90,7 @@ VK_CPPFLAGS_ALWAYS += \
 		-DVM_TRACE=$(VM_TRACE) \
 		-DVM_TRACE_FST=$(VM_TRACE_FST) \
 		-DVM_TRACE_VCD=$(VM_TRACE_VCD) \
+		-DVM_TRACE_SAIF=$(VM_TRACE_SAIF) \
 		$(CFG_CXXFLAGS_NO_UNUSED) \
 
 ifeq ($(CFG_WITH_CCWARN),yes)  # Local... Else don't burden users

include/verilated_saif_c.cpp

@@ -0,0 +1,650 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//=============================================================================
+//
+// Code available from: https://verilator.org
+//
+// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=============================================================================
+///
+/// \file
+/// \brief Verilated C++ tracing in SAIF format implementation code
+///
+/// This file must be compiled and linked against all Verilated objects
+/// that use --trace.
+///
+/// Use "verilator --trace" to add this to the Makefile for the linker.
+///
+//=============================================================================
+
+// clang-format off
+
+#include "verilatedos.h"
+#include "verilated.h"
+#include "verilated_saif_c.h"
+
+#include <algorithm>
+#include <cerrno>
+#include <fcntl.h>
+#include <string>
+
+#if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__)
+# include <io.h>
+#else
+# include <unistd.h>
+#endif
+
+#ifndef O_LARGEFILE  // WIN32 headers omit this
+# define O_LARGEFILE 0
+#endif
+#ifndef O_NONBLOCK  // WIN32 headers omit this
+# define O_NONBLOCK 0
+#endif
+#ifndef O_CLOEXEC  // WIN32 headers omit this
+# define O_CLOEXEC 0
+#endif
+
+// clang-format on
+
+//=============================================================================
+// Specialization of the generics for this trace format
+
+#define VL_SUB_T VerilatedSaif
+#define VL_BUF_T VerilatedSaifBuffer
+#include "verilated_trace_imp.h"
+#undef VL_SUB_T
+#undef VL_BUF_T
+
+//=============================================================================
+// VerilatedSaifActivityBit
+
+class VerilatedSaifActivityBit final {
+    // MEMBERS
+    bool m_lastVal = false;  // Last emitted activity bit value
+    uint64_t m_highTime = 0;  // Total time when bit was high
+    size_t m_transitions = 0;  // Total number of bit transitions
+
+public:
+    // METHODS
+    VL_ATTR_ALWINLINE
+    void aggregateVal(uint64_t dt, bool newVal) {
+        m_transitions += newVal != m_lastVal ? 1 : 0;
+        m_highTime += m_lastVal ? dt : 0;
+        m_lastVal = newVal;
+    }
+
+    // ACCESSORS
+    VL_ATTR_ALWINLINE bool bitValue() const { return m_lastVal; }
+    VL_ATTR_ALWINLINE uint64_t highTime() const { return m_highTime; }
+    VL_ATTR_ALWINLINE uint64_t toggleCount() const { return m_transitions; }
+};
+
+//=============================================================================
+// VerilatedSaifActivityVar
+
+class VerilatedSaifActivityVar final {
+    // MEMBERS
+    uint64_t m_lastTime = 0;  // Last time when variable value was updated
+    VerilatedSaifActivityBit* m_bits;  // Pointer to variable bits objects
+    uint32_t m_width;  // Width of variable (in bits)
+
+public:
+    // CONSTRUCTORS
+    VerilatedSaifActivityVar(uint32_t width, VerilatedSaifActivityBit* bits)
+        : m_bits{bits}
+        , m_width{width} {}
+
+    VerilatedSaifActivityVar(VerilatedSaifActivityVar&&) = default;
+    VerilatedSaifActivityVar& operator=(VerilatedSaifActivityVar&&) = default;
+
+    // METHODS
+    VL_ATTR_ALWINLINE void emitBit(uint64_t time, CData newval);
+
+    template <typename DataType>
+    VL_ATTR_ALWINLINE void emitData(uint64_t time, DataType newval, uint32_t bits) {
+        static_assert(std::is_integral<DataType>::value,
+                      "The emitted value must be of integral type");
+
+        const uint64_t dt = time - m_lastTime;
+        for (size_t i = 0; i < std::min(m_width, bits); i++) {
+            m_bits[i].aggregateVal(dt, (newval >> i) & 1);
+        }
+        updateLastTime(time);
+    }
+
+    VL_ATTR_ALWINLINE void emitWData(uint64_t time, const WData* newvalp, uint32_t bits);
+    VL_ATTR_ALWINLINE void updateLastTime(uint64_t val) { m_lastTime = val; }
+
+    // ACCESSORS
+    VL_ATTR_ALWINLINE uint32_t width() const { return m_width; }
+    VL_ATTR_ALWINLINE VerilatedSaifActivityBit& bit(std::size_t index);
+    VL_ATTR_ALWINLINE uint64_t lastUpdateTime() const { return m_lastTime; }
+
+private:
+    // CONSTRUCTORS
+    VL_UNCOPYABLE(VerilatedSaifActivityVar);
+};
+
+//=============================================================================
+// VerilatedSaifActivityScope
+
+class VerilatedSaifActivityScope final {
+    // MEMBERS
+    // Absolute path to the scope
+    std::string m_scopePath;
+    // Name of the activity scope
+    std::string m_scopeName;
+    // Array indices of child scopes
+    std::vector<std::unique_ptr<VerilatedSaifActivityScope>> m_childScopes{};
+    // Children signals codes mapped to their names in the current scope
+    std::vector<std::pair<uint32_t, std::string>> m_childActivities{};
+    // Parent scope pointer
+    VerilatedSaifActivityScope* m_parentScope = nullptr;
+
+public:
+    // CONSTRUCTORS
+    VerilatedSaifActivityScope(std::string scopePath, std::string name,
+                               VerilatedSaifActivityScope* parentScope = nullptr)
+        : m_scopePath{std::move(scopePath)}
+        , m_scopeName{std::move(name)}
+        , m_parentScope{parentScope} {}
+
+    VerilatedSaifActivityScope(VerilatedSaifActivityScope&&) = default;
+    VerilatedSaifActivityScope& operator=(VerilatedSaifActivityScope&&) = default;
+
+    // METHODS
+    VL_ATTR_ALWINLINE void addChildScope(std::unique_ptr<VerilatedSaifActivityScope> childScope) {
+        m_childScopes.emplace_back(std::move(childScope));
+    }
+    VL_ATTR_ALWINLINE void addActivityVar(uint32_t code, std::string name) {
+        m_childActivities.emplace_back(code, std::move(name));
+    }
+    VL_ATTR_ALWINLINE bool hasParent() const { return m_parentScope; }
+
+    // ACCESSORS
+    VL_ATTR_ALWINLINE const std::string& path() const { return m_scopePath; }
+    VL_ATTR_ALWINLINE const std::string& name() const { return m_scopeName; }
+    VL_ATTR_ALWINLINE const std::vector<std::unique_ptr<VerilatedSaifActivityScope>>&
+    childScopes() const {
+        return m_childScopes;
+    }
+    VL_ATTR_ALWINLINE
+    const std::vector<std::pair<uint32_t, std::string>>& childActivities() const {
+        return m_childActivities;
+    }
+    VL_ATTR_ALWINLINE VerilatedSaifActivityScope* parentScope() const { return m_parentScope; }
+
+private:
+    // CONSTRUCTORS
+    VL_UNCOPYABLE(VerilatedSaifActivityScope);
+};
+
+//=============================================================================
+// VerilatedSaifActivityAccumulator
+
+class VerilatedSaifActivityAccumulator final {
+    // Give access to the private activities
+    friend class VerilatedSaifBuffer;
+    friend class VerilatedSaif;
+
+    // MEMBERS
+    // Map of scopes paths to codes of activities inside
+    std::unordered_map<std::string, std::vector<std::pair<uint32_t, std::string>>>
+        m_scopeToActivities;
+    // Map of variables codes mapped to their activity objects
+    std::unordered_map<uint32_t, VerilatedSaifActivityVar> m_activity;
+    // Memory pool for signals bits objects
+    std::vector<std::vector<VerilatedSaifActivityBit>> m_activityArena;
+
+public:
+    // METHODS
+    void declare(uint32_t code, const std::string& absoluteScopePath, std::string variableName,
+                 int bits, bool array, int arraynum);
+
+    // CONSTRUCTORS
+    VerilatedSaifActivityAccumulator() = default;
+
+    VerilatedSaifActivityAccumulator(VerilatedSaifActivityAccumulator&&) = default;
+    VerilatedSaifActivityAccumulator& operator=(VerilatedSaifActivityAccumulator&&) = default;
+
+private:
+    VL_UNCOPYABLE(VerilatedSaifActivityAccumulator);
+};
+
+//=============================================================================
+//=============================================================================
+//=============================================================================
+// VerilatedSaifActivityVar implementation
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifActivityVar::emitBit(const uint64_t time, const CData newval) {
+    assert(m_lastTime <= time);
+    m_bits[0].aggregateVal(time - m_lastTime, newval);
+    updateLastTime(time);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifActivityVar::emitWData(const uint64_t time, const WData* newvalp,
+                                         const uint32_t bits) {
+    assert(m_lastTime <= time);
+    const uint64_t dt = time - m_lastTime;
+    for (std::size_t i = 0; i < std::min(m_width, bits); ++i) {
+        const size_t wordIndex = i / VL_EDATASIZE;
+        m_bits[i].aggregateVal(dt, (newvalp[wordIndex] >> VL_BITBIT_E(i)) & 1);
+    }
+
+    updateLastTime(time);
+}
+
+VerilatedSaifActivityBit& VerilatedSaifActivityVar::bit(const std::size_t index) {
+    assert(index < m_width);
+    return m_bits[index];
+}
+
+//=============================================================================
+//=============================================================================
+//=============================================================================
+// VerilatedSaifActivityAccumulator implementation
+
+void VerilatedSaifActivityAccumulator::declare(uint32_t code, const std::string& absoluteScopePath,
+                                               std::string variableName, int bits, bool array,
+                                               int arraynum) {
+    const size_t block_size = 1024;
+    if (m_activityArena.empty()
+        || m_activityArena.back().size() + bits > m_activityArena.back().capacity()) {
+        m_activityArena.emplace_back();
+        m_activityArena.back().reserve(block_size);
+    }
+    const size_t bitsIdx = m_activityArena.back().size();
+    m_activityArena.back().resize(m_activityArena.back().size() + bits);
+
+    if (array) {
+        variableName += '[';
+        variableName += std::to_string(arraynum);
+        variableName += ']';
+    }
+    m_scopeToActivities[absoluteScopePath].emplace_back(code, variableName);
+    m_activity.emplace(code, VerilatedSaifActivityVar{static_cast<uint32_t>(bits),
+                                                      m_activityArena.back().data() + bitsIdx});
+}
+
+//=============================================================================
+//=============================================================================
+//=============================================================================
+// VerilatedSaif implementation
+
+VerilatedSaif::VerilatedSaif(void* filep) {
+    m_activityAccumulators.emplace_back(std::make_unique<VerilatedSaifActivityAccumulator>());
+}
+
+void VerilatedSaif::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
+    const VerilatedLockGuard lock{m_mutex};
+    if (isOpen()) return;
+
+    m_filename = filename;  // "" is ok, as someone may overload open
+    m_filep = ::open(m_filename.c_str(),
+                     O_CREAT | O_WRONLY | O_TRUNC | O_LARGEFILE | O_NONBLOCK | O_CLOEXEC, 0666);
+    m_isOpen = true;
+
+    initializeSaifFileContents();
+
+    Super::traceInit();
+}
+
+void VerilatedSaif::initializeSaifFileContents() {
+    printStr("// Generated by verilated_saif\n");
+    printStr("(SAIFILE\n");
+    printStr("(SAIFVERSION \"2.0\")\n");
+    printStr("(DIRECTION \"backward\")\n");
+    printStr("(PROGRAM_NAME \"Verilator\")\n");
+    printStr("(DIVIDER / )\n");
+    printStr("(TIMESCALE ");
+    printStr(timeResStr());
+    printStr(")\n");
+}
+
+void VerilatedSaif::emitTimeChange(uint64_t timeui) { m_time = timeui; }
+
+VerilatedSaif::~VerilatedSaif() { close(); }
+
+void VerilatedSaif::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
+    // This function is on the flush() call path
+    const VerilatedLockGuard lock{m_mutex};
+    if (!isOpen()) return;
+
+    finalizeSaifFileContents();
+    clearCurrentlyCollectedData();
+
+    ::close(m_filep);
+    m_isOpen = false;
+
+    Super::closeBase();
+}
+
+void VerilatedSaif::finalizeSaifFileContents() {
+    printStr("(DURATION ");
+    printStr(std::to_string(currentTime()));
+    printStr(")\n");
+
+    incrementIndent();
+    for (const auto& topScope : m_scopes) recursivelyPrintScopes(*topScope);
+    decrementIndent();
+
+    printStr(")\n");  // SAIFILE
+}
+
+void VerilatedSaif::recursivelyPrintScopes(const VerilatedSaifActivityScope& scope) {
+    openInstanceScope(scope.name());
+    printScopeActivities(scope);
+    for (const auto& childScope : scope.childScopes()) { recursivelyPrintScopes(*childScope); }
+    closeInstanceScope();
+}
+
+void VerilatedSaif::openInstanceScope(const std::string& instanceName) {
+    printIndent();
+    printStr("(INSTANCE ");
+    printStr(instanceName);
+    printStr("\n");
+    incrementIndent();
+}
+
+void VerilatedSaif::closeInstanceScope() {
+    decrementIndent();
+    printIndent();
+    printStr(")\n");  // INSTANCE
+}
+
+void VerilatedSaif::printScopeActivities(const VerilatedSaifActivityScope& scope) {
+    bool anyNetWritten = false;
+
+    for (auto& accumulator : m_activityAccumulators) {
+        anyNetWritten |= printScopeActivitiesFromAccumulatorIfPresent(scope.path(), *accumulator,
+                                                                      anyNetWritten);
+    }
+
+    if (anyNetWritten) closeNetScope();
+}
+
+bool VerilatedSaif::printScopeActivitiesFromAccumulatorIfPresent(
+    const std::string& absoluteScopePath, VerilatedSaifActivityAccumulator& accumulator,
+    bool anyNetWritten) {
+    if (accumulator.m_scopeToActivities.count(absoluteScopePath) == 0) return false;
+
+    for (const auto& childSignal : accumulator.m_scopeToActivities.at(absoluteScopePath)) {
+        VerilatedSaifActivityVar& activityVariable = accumulator.m_activity.at(childSignal.first);
+        anyNetWritten
+            = printActivityStats(activityVariable, childSignal.second.c_str(), anyNetWritten);
+    }
+
+    return anyNetWritten;
+}
+
+void VerilatedSaif::openNetScope() {
+    printIndent();
+    printStr("(NET\n");
+    incrementIndent();
+}
+
+void VerilatedSaif::closeNetScope() {
+    decrementIndent();
+    printIndent();
+    printStr(")\n");  // NET
+}
+
+bool VerilatedSaif::printActivityStats(VerilatedSaifActivityVar& activity,
+                                       const std::string& activityName, bool anyNetWritten) {
+    for (size_t i = 0; i < activity.width(); ++i) {
+        VerilatedSaifActivityBit& bit = activity.bit(i);
+
+        if (bit.toggleCount() <= 0) {
+            // Skip bits with no toggles
+            continue;
+        }
+
+        bit.aggregateVal(currentTime() - activity.lastUpdateTime(), bit.bitValue());
+
+        if (!anyNetWritten) {
+            openNetScope();
+            anyNetWritten = true;
+        }
+
+        printIndent();
+        printStr("(");
+        printStr(activityName);
+        if (activity.width() > 1) {
+            printStr("\\[");
+            printStr(std::to_string(i));
+            printStr("\\]");
+        }
+
+        // We only have two-value logic so TZ, TX and TB will always be 0
+        printStr(" (T0 ");
+        printStr(std::to_string(currentTime() - bit.highTime()));
+        printStr(") (T1 ");
+        printStr(std::to_string(bit.highTime()));
+        printStr(") (TZ 0) (TX 0) (TB 0) (TC ");
+        printStr(std::to_string(bit.toggleCount()));
+        printStr("))\n");
+    }
+
+    activity.updateLastTime(currentTime());
+
+    return anyNetWritten;
+}
+
+void VerilatedSaif::clearCurrentlyCollectedData() {
+    m_currentScope = nullptr;
+    m_scopes.clear();
+    m_activityAccumulators.clear();
+}
+
+void VerilatedSaif::printStr(const char* str) { ::write(m_filep, str, strlen(str)); }
+
+void VerilatedSaif::printStr(const std::string& str) { ::write(m_filep, str.c_str(), str.size()); }
+
+//=============================================================================
+// Definitions
+
+void VerilatedSaif::flush() VL_MT_SAFE_EXCLUDES(m_mutex) {
+    const VerilatedLockGuard lock{m_mutex};
+    Super::flushBase();
+}
+
+void VerilatedSaif::incrementIndent() { m_indent += 1; }
+
+void VerilatedSaif::decrementIndent() { m_indent -= 1; }
+
+void VerilatedSaif::printIndent() {
+    for (int i = 0; i < m_indent; ++i) printStr(" ");
+}
+
+void VerilatedSaif::pushPrefix(const std::string& name, VerilatedTracePrefixType type) {
+    std::string pname = name;
+
+    if (m_prefixStack.back().second == VerilatedTracePrefixType::ROOTIO_MODULE) popPrefix();
+    if (pname.empty()) {
+        pname = "$rootio";
+        type = VerilatedTracePrefixType::ROOTIO_MODULE;
+    }
+
+    if (type != VerilatedTracePrefixType::ARRAY_UNPACKED
+        && type != VerilatedTracePrefixType::ARRAY_PACKED) {
+
+        std::string scopePath = m_prefixStack.back().first + pname;
+        std::string scopeName = lastWord(scopePath);
+
+        auto newScope = std::make_unique<VerilatedSaifActivityScope>(
+            std::move(scopePath), std::move(scopeName), m_currentScope);
+        VerilatedSaifActivityScope* newScopePtr = newScope.get();
+
+        if (m_currentScope) {
+            m_currentScope->addChildScope(std::move(newScope));
+        } else {
+            m_scopes.emplace_back(std::move(newScope));
+        }
+
+        m_currentScope = newScopePtr;
+    }
+
+    std::string newPrefix = m_prefixStack.back().first + pname;
+    if (type != VerilatedTracePrefixType::ARRAY_UNPACKED
+        && type != VerilatedTracePrefixType::ARRAY_PACKED) {
+        newPrefix += ' ';
+    }
+
+    m_prefixStack.emplace_back(newPrefix, type);
+}
+
+void VerilatedSaif::popPrefix() {
+    if (m_prefixStack.back().second != VerilatedTracePrefixType::ARRAY_UNPACKED
+        && m_prefixStack.back().second != VerilatedTracePrefixType::ARRAY_PACKED
+        && m_currentScope != nullptr) {
+        m_currentScope = m_currentScope->parentScope();
+    }
+
+    m_prefixStack.pop_back();
+}
+
+void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name,
+                            const char* wirep, const bool array, const int arraynum,
+                            const bool bussed, const int msb, const int lsb) {
+    assert(m_activityAccumulators.size() > fidx);
+    VerilatedSaifActivityAccumulator& accumulator = *m_activityAccumulators.at(fidx);
+
+    const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
+
+    const std::string hierarchicalName = m_prefixStack.back().first + name;
+
+    if (!Super::declCode(code, hierarchicalName, bits)) return;
+
+    std::string variableName = lastWord(hierarchicalName);
+    m_currentScope->addActivityVar(code, variableName);
+
+    accumulator.declare(code, m_currentScope->path(), std::move(variableName), bits, array,
+                        arraynum);
+}
+
+void VerilatedSaif::declEvent(const uint32_t code, const uint32_t fidx, const char* name,
+                              const int dtypenum, const VerilatedTraceSigDirection,
+                              const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                              const bool array, const int arraynum) {
+    declare(code, fidx, name, "event", array, arraynum, false, 0, 0);
+}
+
+void VerilatedSaif::declBit(const uint32_t code, const uint32_t fidx, const char* name,
+                            const int dtypenum, const VerilatedTraceSigDirection,
+                            const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                            const bool array, const int arraynum) {
+    declare(code, fidx, name, "wire", array, arraynum, false, 0, 0);
+}
+void VerilatedSaif::declBus(const uint32_t code, const uint32_t fidx, const char* name,
+                            const int dtypenum, const VerilatedTraceSigDirection,
+                            const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                            const bool array, const int arraynum, const int msb, const int lsb) {
+    declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb);
+}
+void VerilatedSaif::declQuad(const uint32_t code, const uint32_t fidx, const char* name,
+                             const int dtypenum, const VerilatedTraceSigDirection,
+                             const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                             const bool array, const int arraynum, const int msb, const int lsb) {
+    declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb);
+}
+void VerilatedSaif::declArray(const uint32_t code, const uint32_t fidx, const char* name,
+                              const int dtypenum, const VerilatedTraceSigDirection,
+                              const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                              const bool array, const int arraynum, const int msb, const int lsb) {
+    declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb);
+}
+void VerilatedSaif::declDouble(const uint32_t code, const uint32_t fidx, const char* name,
+                               const int dtypenum, const VerilatedTraceSigDirection,
+                               const VerilatedTraceSigKind, const VerilatedTraceSigType,
+                               const bool array, const int arraynum) {
+    declare(code, fidx, name, "real", array, arraynum, false, 63, 0);
+}
+
+//=============================================================================
+// Get/commit trace buffer
+
+VerilatedSaif::Buffer* VerilatedSaif::getTraceBuffer(uint32_t fidx) { return new Buffer{*this}; }
+
+void VerilatedSaif::commitTraceBuffer(VerilatedSaif::Buffer* bufp) { delete bufp; }
+
+//=============================================================================
+//=============================================================================
+//=============================================================================
+// VerilatedSaifBuffer implementation
+
+//=============================================================================
+// emit* trace routines
+
+// Note: emit* are only ever called from one place (full* in
+// verilated_trace_imp.h, which is included in this file at the top),
+// so always inline them.
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitEvent(const uint32_t code) {
+    // NOP
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitBit(const uint32_t code, const CData newval) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitBit(m_owner.currentTime(), newval);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitCData(const uint32_t code, const CData newval, const int bits) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitData<CData>(m_owner.currentTime(), newval, bits);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitSData(const uint32_t code, const SData newval, const int bits) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitData<SData>(m_owner.currentTime(), newval, bits);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitIData(const uint32_t code, const IData newval, const int bits) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitData<IData>(m_owner.currentTime(), newval, bits);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitQData(const uint32_t code, const QData newval, const int bits) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitData<QData>(m_owner.currentTime(), newval, bits);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitWData(const uint32_t code, const WData* newvalp, const int bits) {
+    assert(m_owner.m_activityAccumulators.at(m_fidx)->m_activity.count(code)
+           && "Activity must be declared earlier");
+    VerilatedSaifActivityVar& activity
+        = m_owner.m_activityAccumulators.at(m_fidx)->m_activity.at(code);
+    activity.emitWData(m_owner.currentTime(), newvalp, bits);
+}
+
+VL_ATTR_ALWINLINE
+void VerilatedSaifBuffer::emitDouble(const uint32_t code, const double newval) {
+    // NOP
+}

include/verilated_saif_c.h

@@ -0,0 +1,289 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//=============================================================================
+//
+// Code available from: https://verilator.org
+//
+// Copyright 2001-2025 by Wilson Snyder. This program is free software; you
+// can redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=============================================================================
+///
+/// \file
+/// \brief Verilated tracing in SAIF format header
+///
+/// User wrapper code should use this header when creating SAIF traces.
+///
+//=============================================================================
+
+#ifndef VERILATOR_VERILATED_SAIF_C_H_
+#define VERILATOR_VERILATED_SAIF_C_H_
+
+#include "verilated.h"
+#include "verilated_trace.h"
+
+#include <string>
+#include <unordered_map>
+#include <vector>
+
+class VerilatedSaifBuffer;
+class VerilatedSaifActivityAccumulator;
+class VerilatedSaifActivityScope;
+class VerilatedSaifActivityVar;
+class VerilatedSaifActivityBit;
+
+//=============================================================================
+// VerilatedSaif
+// Base class to create a Verilator SAIF dump
+// This is an internally used class - see VerilatedSaifC for what to call from applications
+
+class VerilatedSaif VL_NOT_FINAL : public VerilatedTrace<VerilatedSaif, VerilatedSaifBuffer> {
+public:
+    using Super = VerilatedTrace<VerilatedSaif, VerilatedSaifBuffer>;
+
+private:
+    friend VerilatedSaifBuffer;  // Give the buffer access to the private bits
+
+    //=========================================================================
+    // SAIF-specific internals
+
+    int m_filep = 0;  // File we're writing to
+    bool m_isOpen = false;  // True indicates open file
+    std::string m_filename;  // Filename we're writing to (if open)
+
+    int m_indent = 0;  // Indentation size in spaces
+
+    // Currently active scope
+    VerilatedSaifActivityScope* m_currentScope = nullptr;
+    // Array of declared scopes
+    std::vector<std::unique_ptr<VerilatedSaifActivityScope>> m_scopes{};
+    // Activity accumulators used to store variables statistics over simulation time
+    std::vector<std::unique_ptr<VerilatedSaifActivityAccumulator>> m_activityAccumulators{};
+    // Total time of the currently traced simulation
+    uint64_t m_time = 0;
+
+    // Stack of declared scopes combined names
+    std::vector<std::pair<std::string, VerilatedTracePrefixType>> m_prefixStack{
+        {"", VerilatedTracePrefixType::SCOPE_MODULE}};
+
+    // METHODS
+    VL_ATTR_ALWINLINE uint64_t currentTime() const { return m_time; }
+
+    void initializeSaifFileContents();
+    void finalizeSaifFileContents();
+    void recursivelyPrintScopes(const VerilatedSaifActivityScope& scope);
+    void openInstanceScope(const std::string& instanceName);
+    void closeInstanceScope();
+    void printScopeActivities(const VerilatedSaifActivityScope& scope);
+    bool
+    printScopeActivitiesFromAccumulatorIfPresent(const std::string& absoluteScopePath,
+                                                 VerilatedSaifActivityAccumulator& accumulator,
+                                                 bool anyNetWritten);
+    void openNetScope();
+    void closeNetScope();
+    bool printActivityStats(VerilatedSaifActivityVar& activity, const std::string& activityName,
+                            bool anyNetWritten);
+
+    void incrementIndent();
+    void decrementIndent();
+    void printIndent();
+
+    void printStr(const char* str);
+    void printStr(const std::string& str);
+
+    void clearCurrentlyCollectedData();
+
+    void declare(uint32_t code, uint32_t fidx, const char* name, const char* wirep, bool array,
+                 int arraynum, bool bussed, int msb, int lsb);
+
+    // CONSTRUCTORS
+    VL_UNCOPYABLE(VerilatedSaif);
+
+protected:
+    //=========================================================================
+    // Implementation of VerilatedTrace interface
+
+    // Called when the trace moves forward to a new time point
+    void emitTimeChange(uint64_t timeui) override;
+
+    // Hooks called from VerilatedTrace
+    bool preFullDump() override { return isOpen(); }
+    bool preChangeDump() override { return isOpen(); }
+
+    // Trace buffer management
+    Buffer* getTraceBuffer(uint32_t fidx) override;
+    void commitTraceBuffer(Buffer*) override;
+
+    // Configure sub-class
+    void configure(const VerilatedTraceConfig&) override {}
+
+public:
+    //=========================================================================
+    // External interface to client code
+
+    // CONSTRUCTOR
+    explicit VerilatedSaif(void* filep = nullptr);
+    ~VerilatedSaif();
+
+    // METHODS - All must be thread safe
+    // Open the file; call isOpen() to see if errors
+    void open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex);
+    // Close the file
+    void close() VL_MT_SAFE_EXCLUDES(m_mutex);
+    // Flush any remaining data to this file
+    void flush() VL_MT_SAFE_EXCLUDES(m_mutex);
+    // Return if file is open
+    bool isOpen() const VL_MT_SAFE { return m_isOpen; }
+
+    //=========================================================================
+    // Internal interface to Verilator generated code
+
+    void pushPrefix(const std::string&, VerilatedTracePrefixType);
+    void popPrefix();
+
+    void declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                   VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                   bool array, int arraynum);
+    void declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                 VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                 bool array, int arraynum);
+    void declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                 VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                 bool array, int arraynum, int msb, int lsb);
+    void declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                  VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                  bool array, int arraynum, int msb, int lsb);
+    void declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                   VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                   bool array, int arraynum, int msb, int lsb);
+    void declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum,
+                    VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType,
+                    bool array, int arraynum);
+};
+
+#ifndef DOXYGEN
+// Declare specialization here as it's used in VerilatedSaifC just below
+template <>
+void VerilatedSaif::Super::dump(uint64_t time);
+template <>
+void VerilatedSaif::Super::set_time_unit(const char* unitp);
+template <>
+void VerilatedSaif::Super::set_time_unit(const std::string& unit);
+template <>
+void VerilatedSaif::Super::set_time_resolution(const char* unitp);
+template <>
+void VerilatedSaif::Super::set_time_resolution(const std::string& unit);
+template <>
+void VerilatedSaif::Super::dumpvars(int level, const std::string& hier);
+#endif  // DOXYGEN
+
+//=============================================================================
+// VerilatedSaifBuffer
+
+class VerilatedSaifBuffer VL_NOT_FINAL {
+    // Give the trace file and sub-classes access to the private bits
+    friend VerilatedSaif;
+    friend VerilatedSaif::Super;
+    friend VerilatedSaif::Buffer;
+    friend VerilatedSaif::OffloadBuffer;
+
+    VerilatedSaif& m_owner;  // Trace file owning this buffer. Required by subclasses.
+    uint32_t m_fidx;  // Index of target activity accumulator
+
+    // CONSTRUCTORS
+    explicit VerilatedSaifBuffer(VerilatedSaif& owner)
+        : m_owner{owner}
+        , m_fidx{0} {}
+    explicit VerilatedSaifBuffer(VerilatedSaif& owner, uint32_t fidx)
+        : m_owner{owner}
+        , m_fidx{fidx} {}
+    virtual ~VerilatedSaifBuffer() = default;
+
+    //=========================================================================
+    // Implementation of VerilatedTraceBuffer interface
+    // Implementations of duck-typed methods for VerilatedTraceBuffer. These are
+    // called from only one place (the full* methods), so always inline them.
+    VL_ATTR_ALWINLINE void emitEvent(uint32_t code);
+    VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval);
+    VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits);
+    VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits);
+    VL_ATTR_ALWINLINE void emitIData(uint32_t code, IData newval, int bits);
+    VL_ATTR_ALWINLINE void emitQData(uint32_t code, QData newval, int bits);
+    VL_ATTR_ALWINLINE void emitWData(uint32_t code, const WData* newvalp, int bits);
+    VL_ATTR_ALWINLINE void emitDouble(uint32_t code, double newval);
+};
+
+//=============================================================================
+// VerilatedSaifC
+// Class representing a SAIF dump file in C standalone (no SystemC)
+// simulations. Also derived for use in SystemC simulations.
+
+class VerilatedSaifC VL_NOT_FINAL : public VerilatedTraceBaseC {
+    VerilatedSaif m_sptrace;  // Trace file being created
+
+    // CONSTRUCTORS
+    VL_UNCOPYABLE(VerilatedSaifC);
+
+public:
+    // Construct the dump. Optional argument is ignored
+    explicit VerilatedSaifC(void* filep = nullptr)
+        : m_sptrace{filep} {}
+    // Destruct, flush, and close the dump
+    virtual ~VerilatedSaifC() { close(); }
+
+    // METHODS - User called
+
+    // Return if file is open
+    bool isOpen() const override VL_MT_SAFE { return m_sptrace.isOpen(); }
+    // Open a new SAIF file
+    // This includes a complete header dump each time it is called,
+    // just as if this object was deleted and reconstructed.
+    virtual void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); }
+
+    void rolloverSize(size_t size) VL_MT_SAFE {}  // NOP
+
+    // Close dump
+    void close() VL_MT_SAFE {
+        m_sptrace.close();
+        modelConnected(false);
+    }
+    // Flush dump
+    void flush() VL_MT_SAFE { m_sptrace.flush(); }
+    // Write one cycle of dump data
+    // Call with the current context's time just after eval'ed,
+    // e.g. ->dump(contextp->time())
+    void dump(uint64_t timeui) VL_MT_SAFE { m_sptrace.dump(timeui); }
+    // Write one cycle of dump data - backward compatible and to reduce
+    // conversion warnings.  It's better to use a uint64_t time instead.
+    void dump(double timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(uint32_t timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+    void dump(int timestamp) { dump(static_cast<uint64_t>(timestamp)); }
+
+    // METHODS - Internal/backward compatible
+    // \protectedsection
+
+    // Set time units (s/ms, defaults to ns)
+    // Users should not need to call this, as for Verilated models, these
+    // propagate from the Verilated default timeunit
+    void set_time_unit(const char* unit) VL_MT_SAFE { m_sptrace.set_time_unit(unit); }
+    void set_time_unit(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_unit(unit); }
+    // Set time resolution (s/ms, defaults to ns)
+    // Users should not need to call this, as for Verilated models, these
+    // propagate from the Verilated default timeprecision
+    void set_time_resolution(const char* unit) VL_MT_SAFE { m_sptrace.set_time_resolution(unit); }
+    void set_time_resolution(const std::string& unit) VL_MT_SAFE {
+        m_sptrace.set_time_resolution(unit);
+    }
+    // Set variables to dump, using $dumpvars format
+    // If level = 0, dump everything and hier is then ignored
+    void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
+        m_sptrace.dumpvars(level, hier);
+    }
+
+    // Internal class access
+    VerilatedSaif* spTrace() { return &m_sptrace; }
+};
+
+#endif  // guard

include/verilated_saif_sc.h

@@ -0,0 +1,56 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//=============================================================================
+//
+// Copyright 2001-2025 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=============================================================================
+///
+/// \file
+/// \brief Verilated tracing in SAIF format for SystemC header
+///
+/// User wrapper code should use this header when creating SAIF SystemC traces.
+///
+/// This class is not threadsafe, as the SystemC kernel is not threadsafe.
+///
+//=============================================================================
+
+#ifndef VERILATOR_VERILATED_SAIF_SC_H_
+#define VERILATOR_VERILATED_SAIF_SC_H_
+
+#include "verilatedos.h"
+
+#include "verilated_saif_c.h"
+#include "verilated_sc_trace.h"
+
+//=============================================================================
+// VerilatedSaifSc
+/// Trace file used to create SAIF dump for SystemC version of Verilated models. It's very similar
+/// to its C version (see the class VerilatedSaifC)
+
+class VerilatedSaifSc final : VerilatedScTraceBase, public VerilatedSaifC {
+    // CONSTRUCTORS
+    VL_UNCOPYABLE(VerilatedSaifSc);
+
+public:
+    VerilatedSaifSc() {
+        spTrace()->set_time_unit(VerilatedScTraceBase::getScTimeUnit());
+        spTrace()->set_time_resolution(VerilatedScTraceBase::getScTimeResolution());
+    }
+
+    // METHODS
+    // Override VerilatedSaifC. Must be called after starting simulation.
+    void open(const char* filename) override VL_MT_SAFE {
+        VerilatedScTraceBase::checkScElaborationDone();
+        VerilatedSaifC::open(filename);
+    }
+
+    // METHODS - for SC kernel
+    // Called from SystemC kernel
+    void cycle() override { VerilatedSaifC::dump(sc_core::sc_time_stamp().to_double()); }
+};
+
+#endif  // Guard

nodist/verilator_saif_diff

@@ -0,0 +1,241 @@
+#!/usr/bin/env python3
+# pylint: disable=C0114,C0115,C0116,R0902,R0903,R0912,R0915,W0719,W0718
+######################################################################
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import argparse
+import re
+
+SUCCESS_CODE = 0
+FAILURE_CODE = 1
+INSTANCE_TYPE = "INSTANCE"
+NET_LIST_TYPE = "NET"
+SIGNAL_TYPE = "SIGNAL"
+EOF_ERROR = "Unexpected EOF"
+
+
+def saif_assert(expression, message):
+    if not expression:
+        raise Exception(message)
+
+
+def saif_error(message):
+    raise Exception(message)
+
+
+class SAIFSignalBit:
+    name: str
+    high_time: int
+    low_time: int
+    transitions: int
+
+    def __init__(self, name):
+        self.name = name
+        self.high_time = 0
+        self.low_time = 0
+        self.transitions = 0
+
+
+class SAIFInstance:
+
+    def __init__(self, scope_name):
+        self.scope_name = scope_name
+        self.parent_instance = None
+        self.nets = {}
+        self.child_instances = {}
+
+
+class SAIFToken:
+
+    def __init__(self, token):
+        self.token = token
+        self.type = ''
+        self.value = ''
+
+
+class SAIFParser:
+
+    def __init__(self):
+        self.token_stack = []
+        # For parsing simplicity
+        self.token_stack.append(SAIFToken('saif_root'))
+        self.current_instance = None
+        self.has_saifile_header = False
+        self.direction = ''
+        self.saif_version = ''
+        self.top_instances = {}
+        self.duration = 0
+        self.divider = ''
+        self.timescale = ''
+
+    def parse(self, saif_filename):
+        file_contents = ''
+        with open(saif_filename, 'r', encoding="utf8") as saif_file:
+            content = saif_file.readlines()
+            filtered_lines = [line for line in content if not line.strip().startswith('//')]
+            file_contents = ''.join(filtered_lines)
+        tokens = file_contents.replace('(', ' ( ').replace(')', ' ) ').split()
+        num_of_tokens = len(tokens)
+        index = 0
+        while index < num_of_tokens:
+            token = tokens[index]
+            index += 1
+            if token == '(':
+                self.token_stack.append(SAIFToken(token))
+                self.token_stack[-1].type = self.token_stack[-2].type
+                self.token_stack[-1].value = self.token_stack[-2].value
+                continue
+            if token == ')':
+                if self.token_stack[-1].type == INSTANCE_TYPE:
+                    self.current_instance = self.current_instance.parent_instance
+                self.token_stack.pop()
+                continue
+            if re.match(r'SAIFILE', token):
+                self.has_saifile_header = True
+                continue
+            if re.match(r'DIRECTION', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.direction = tokens[index].replace('\"', '')
+                index += 1
+                continue
+            if re.match(r'SAIFVERSION', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.saif_version = tokens[index].replace('\"', '')
+                index += 1
+                continue
+            if re.match(r'DESIGN|DATE|VENDOR|PROGRAM_NAME|VERSION', token):
+                # NOP, only skip value
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                index += 1
+                continue
+            if re.match(r'DIVIDER', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.divider = tokens[index]
+                index += 1
+                continue
+            if re.match(r'TIMESCALE', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.timescale = tokens[index]
+                index += 1
+                continue
+            if re.match(r'DURATION', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.duration = tokens[index]
+                index += 1
+                continue
+            if re.match(r'INSTANCE', token):
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                instance_name = tokens[index]
+                index += 1
+                self.token_stack[-1].type = INSTANCE_TYPE
+                self.token_stack[-1].value = instance_name
+                instance = SAIFInstance(instance_name)
+                if self.current_instance is None:
+                    self.top_instances[instance_name] = instance
+                else:
+                    self.current_instance.child_instances[instance_name] = instance
+                instance.parent_instance = self.current_instance
+                self.current_instance = instance
+                continue
+            if re.match(r'NET', token):
+                self.token_stack[-1].type = NET_LIST_TYPE
+                continue
+            if re.match(r'T1', token):
+                net_name = self.token_stack[-1].value
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.current_instance.nets[net_name].high_time = tokens[index]
+                index += 1
+                continue
+            if re.match(r'T0', token):
+                net_name = self.token_stack[-1].value
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.current_instance.nets[net_name].low_time = tokens[index]
+                index += 1
+                continue
+            if re.match(r'TC', token):
+                net_name = self.token_stack[-1].value
+                saif_assert(index < num_of_tokens, EOF_ERROR)
+                self.current_instance.nets[net_name].transitions = tokens[index]
+                index += 1
+                continue
+            if re.match(r'TZ|TX|TB|TG|IG|IK', token):
+                # NOP, only skip value
+                index += 1
+                continue
+            if self.token_stack[-2].type == NET_LIST_TYPE:
+                self.token_stack[-1].type = SIGNAL_TYPE
+                self.token_stack[-1].value = token
+                self.current_instance.nets[token] = SAIFSignalBit(token)
+        saif_assert(self.has_saifile_header, "SAIF file doesn't contain a SAIFILE keyword")
+        saif_assert(self.direction == "backward",
+                    f"SAIF file doesn't have a valid/compatible direction: {self.direction}")
+        saif_assert(self.saif_version == "2.0",
+                    f"SAIF file doesn't have a valid/compatible version: {self.saif_version}")
+        # Only 'saif_root' token should be left
+        saif_assert(len(self.token_stack) == 1, "Incorrect nesting of scopes")
+
+
+def compare_saif_instances(first: SAIFInstance, second: SAIFInstance):
+    if len(first.nets) != len(second.nets):
+        saif_error(f"Number of nets doesn't match in {first.scope_name}: "
+                   f"{len(first.nets)} != {len(second.nets)}")
+    for signal_name, saif_signal in first.nets.items():
+        if signal_name not in second.nets:
+            saif_error(f"Signal {signal_name} doesn't exist in the second object\n")
+        other_signal = second.nets[signal_name]
+        if (saif_signal.high_time != other_signal.high_time
+                or saif_signal.low_time != other_signal.low_time
+                or saif_signal.transitions != other_signal.transitions):
+            saif_error("Incompatible signal bit parameters in "
+                       f"{signal_name}\n")
+    if len(first.child_instances) != len(second.child_instances):
+        saif_error(f"Number of child instances doesn't match in {first.scope_name}: "
+                   f"{len(first.child_instances)} != {len(second.child_instances)}")
+    for instance_name, instance in first.child_instances.items():
+        if instance_name not in second.child_instances:
+            saif_error(f"Instance {instance_name} doesn't exist in the second object\n")
+        compare_saif_instances(instance, second.child_instances[instance_name])
+
+
+def compare_saif_contents(first_file: str, second_file: str):
+    """Test if second SAIF file has the same values as the first"""
+    first_saif = SAIFParser()
+    first_saif.parse(first_file)
+    second_saif = SAIFParser()
+    second_saif.parse(second_file)
+    if first_saif.duration != second_saif.duration:
+        saif_error("Duration of trace doesn't match: "
+                   f"{first_saif.duration} != {second_saif.duration}")
+    if first_saif.divider != second_saif.divider:
+        saif_error(f"Dividers don't match: {first_saif.divider} != {second_saif.divider}")
+    if first_saif.timescale != second_saif.timescale:
+        saif_error(f"Timescale doesn't match: {first_saif.timescale} != {second_saif.timescale}")
+    if len(first_saif.top_instances) != len(second_saif.top_instances):
+        saif_error("Number of top instances doesn't match: "
+                   f"{len(first_saif.top_instances)} != {len(second_saif.top_instances)}")
+    for top_instance_name, top_instance in first_saif.top_instances.items():
+        if top_instance_name not in second_saif.top_instances:
+            saif_error(f"Top instance {top_instance_name} missing in other SAIF")
+        compare_saif_instances(top_instance, second_saif.top_instances[top_instance_name])
+    return SUCCESS_CODE
+
+
+parser = argparse.ArgumentParser(allow_abbrev=False,
+                                 formatter_class=argparse.RawDescriptionHelpFormatter,
+                                 description="""verilator_saif_diff checks if two SAIF files are logically-identical. It returns first encountered difference as output.
+Run as:
+  cd $VERILATOR_ROOT
+  nodist/code_coverage --first example.saif --second other.saif""")
+parser.add_argument('--first', action='store', help='First SAIF file')
+parser.add_argument('--second', action='store', help='Second SAIF file')
+parser.set_defaults(stop=True)
+args = parser.parse_args()
+try:
+    compare_saif_contents(args.first, args.second)
+except Exception as error:
+    print(error)

src/V3EmitCMake.cpp

@@ -116,6 +116,9 @@ class CMakeEmitter final {
         *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n";
         cmake_set_raw(*of, name + "_TRACE_FST",
                       (v3Global.opt.trace() && v3Global.opt.traceFormat().fst()) ? "1" : "0");
+        *of << "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n";
+        cmake_set_raw(*of, name + "_TRACE_SAIF",
+                      (v3Global.opt.trace() && v3Global.opt.traceFormat().saif()) ? "1" : "0");
 
         *of << "\n### Sources...\n";
         std::vector<string> classes_fast;

src/V3EmitMk.cpp

@@ -551,7 +551,7 @@ public:
         of.puts("VM_PARALLEL_BUILDS = ");
         of.puts(v3Global.useParallelBuild() ? "1" : "0");
         of.puts("\n");
-        of.puts("# Tracing output mode?  0/1 (from --trace/--trace-fst)\n");
+        of.puts("# Tracing output mode?  0/1 (from --trace/--trace-fst/--trace-saif)\n");
         of.puts("VM_TRACE = ");
         of.puts(v3Global.opt.trace() ? "1" : "0");
         of.puts("\n");
@@ -563,6 +563,10 @@ public:
         of.puts("VM_TRACE_FST = ");
         of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().fst() ? "1" : "0");
         of.puts("\n");
+        of.puts("# Tracing output mode in SAIF format?  0/1 (from --trace-saif)\n");
+        of.puts("VM_TRACE_SAIF = ");
+        of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().saif() ? "1" : "0");
+        of.puts("\n");
 
         of.puts("\n### Object file lists...\n");
         for (int support = 0; support < 3; ++support) {

src/V3Options.cpp

@@ -1640,6 +1640,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
     DECL_OPTION("-top", Set, &m_topModule);
     DECL_OPTION("-top-module", Set, &m_topModule);
     DECL_OPTION("-trace", OnOff, &m_trace);
+    DECL_OPTION("-trace-saif", CbCall, [this]() {
+        m_trace = true;
+        m_traceFormat = TraceFormat::SAIF;
+    });
     DECL_OPTION("-trace-coverage", OnOff, &m_traceCoverage);
     DECL_OPTION("-trace-depth", Set, &m_traceDepth);
     DECL_OPTION("-trace-fst", CbCall, [this]() {

src/V3Options.h

@@ -133,7 +133,7 @@ inline std::ostream& operator<<(std::ostream& os, const VTimescale& rhs) {
 
 class TraceFormat final {
 public:
-    enum en : uint8_t { VCD = 0, FST } m_e;
+    enum en : uint8_t { VCD = 0, FST, SAIF } m_e;
     // cppcheck-suppress noExplicitConstructor
     constexpr TraceFormat(en _e = VCD)
         : m_e{_e} {}
@@ -141,13 +141,14 @@ public:
         : m_e(static_cast<en>(_e)) {}  // Need () or GCC 4.8 false warning
     constexpr operator en() const { return m_e; }
     bool fst() const { return m_e == FST; }
+    bool saif() const { return m_e == SAIF; }
     bool vcd() const { return m_e == VCD; }
     string classBase() const VL_MT_SAFE {
-        static const char* const names[] = {"VerilatedVcd", "VerilatedFst"};
+        static const char* const names[] = {"VerilatedVcd", "VerilatedFst", "VerilatedSaif"};
         return names[m_e];
     }
     string sourceName() const VL_MT_SAFE {
-        static const char* const names[] = {"verilated_vcd", "verilated_fst"};
+        static const char* const names[] = {"verilated_vcd", "verilated_fst", "verilated_saif"};
         return names[m_e];
     }
 };

test_regress/driver.py

@@ -52,6 +52,7 @@ Quitting = False
 Vltmt_Threads = 3
 forker = None
 Start = None
+nodist_directory = "../nodist"
 
 # So an 'import vltest_bootstrap' inside test files will do nothing
 sys.modules['vltest_bootstrap'] = {}
@@ -1009,6 +1010,11 @@ class VlTest:
                 self.trace_format = 'fst-sc'  # pylint: disable=attribute-defined-outside-init
             else:
                 self.trace_format = 'fst-c'  # pylint: disable=attribute-defined-outside-init
+        elif re.search(r'-trace-saif', checkflags):
+            if self.sc:
+                self.trace_format = 'saif-sc'  # pylint: disable=attribute-defined-outside-init
+            else:
+                self.trace_format = 'saif-c'  # pylint: disable=attribute-defined-outside-init
         elif self.sc:
             self.trace_format = 'vcd-sc'  # pylint: disable=attribute-defined-outside-init
         else:
@@ -1563,6 +1569,8 @@ class VlTest:
     def trace_filename(self) -> str:
         if re.match(r'^fst', self.trace_format):
             return self.obj_dir + "/simx.fst"
+        if re.match(r'^saif', self.trace_format):
+            return self.obj_dir + "/simx.saif"
         return self.obj_dir + "/simx.vcd"
 
     def skip_if_too_few_cores(self) -> None:
@@ -1865,6 +1873,10 @@ class VlTest:
                 fh.write("#include \"verilated_vcd_c.h\"\n")
             if self.trace and self.trace_format == 'vcd-sc':
                 fh.write("#include \"verilated_vcd_sc.h\"\n")
+            if self.trace and self.trace_format == 'saif-c':
+                fh.write("#include \"verilated_saif_c.h\"\n")
+            if self.trace and self.trace_format == 'saif-sc':
+                fh.write("#include \"verilated_saif_sc.h\"\n")
             if self.savable:
                 fh.write("#include \"verilated_save.h\"\n")
 
@@ -1948,6 +1960,10 @@ class VlTest:
                     fh.write("    std::unique_ptr<VerilatedVcdC> tfp{new VerilatedVcdC};\n")
                 if self.trace_format == 'vcd-sc':
                     fh.write("    std::unique_ptr<VerilatedVcdSc> tfp{new VerilatedVcdSc};\n")
+                if self.trace_format == 'saif-c':
+                    fh.write("    std::unique_ptr<VerilatedSaifC> tfp{new VerilatedSaifC};\n")
+                if self.trace_format == 'saif-sc':
+                    fh.write("    std::unique_ptr<VerilatedSaifSc> tfp{new VerilatedSaifSc};\n")
                 if self.sc:
                     fh.write("    sc_core::sc_start(sc_core::SC_ZERO_TIME);" +
                              "  // Finish elaboration before trace and open\n")
@@ -2353,6 +2369,16 @@ class VlTest:
         self.fst2vcd(fn1, tmp)
         self.vcd_identical(tmp, fn2)
 
+    def saif_identical(self, fn1: str, fn2: str) -> None:
+        """Test if two SAIF files have logically-identical contents"""
+
+        cmd = nodist_directory + '/verilator_saif_diff --first "' + fn1 + '" --second "' + fn2 + '"'
+        print("\t " + cmd + "\n")
+        out = test.run_capture(cmd, check=True)
+        if out != '':
+            print(out)
+            self.error("SAIF files don't match!")
+
     def _vcd_read(self, filename: str) -> str:
         data = {}
         with open(filename, 'r', encoding='latin-1') as fh:

test_regress/t/t_hier_block_trace_saif.py

@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_hier_block.v"
+test.golden_filename = "t/t_hier_block_trace_saif.out"
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# So use 6 threads here though it's not optimal in performance, but ok.
+
+test.compile(
+    v_flags2=['t/t_hier_block.cpp'],
+    verilator_flags2=[
+        '--hierarchical',
+        '--Wno-TIMESCALEMOD',
+        '--trace-saif',
+        '--no-trace-underscore',  # To avoid handle mismatches
+    ],
+    threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_interface_ref_trace_saif.out

@@ -0,0 +1,940 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 210)
+ (INSTANCE top
+  (NET
+   (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+    (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+    (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+    (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE intf_1
+    (NET
+     (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+     (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+     (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+     (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE the_struct
+     (NET
+      (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+      (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+      (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE inner
+     (NET
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+   (INSTANCE intf_2
+    (NET
+     (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+     (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+     (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+     (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE the_struct
+     (NET
+      (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE inner
+     (NET
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+   (INSTANCE a
+    (INSTANCE intf_one
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+      (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+    (INSTANCE intf_two
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
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+        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+    )
+   )
+   (INSTANCE c1
+    (INSTANCE intf_for_check
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+      (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+   )
+   (INSTANCE c2
+    (INSTANCE intf_for_check
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+   )
+   (INSTANCE s1
+    (INSTANCE intf_for_struct
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+      (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+   )
+   (INSTANCE s2
+    (INSTANCE intf_for_struct
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_interface_ref_trace_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_interface_ref_trace.v"
+test.golden_filename = "t/t_interface_ref_trace_saif.out"
+
+test.compile(verilator_flags2=['--trace-structs --trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_timing_trace_saif.out

@@ -0,0 +1,23 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 100)
+ (INSTANCE $rootio
+ )
+ (INSTANCE t
+  (NET
+   (CLK_PERIOD\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (CLK_PERIOD\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (CLK_HALF_PERIOD\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (CLK_HALF_PERIOD\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (rst (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (clk (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 20))
+   (b (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+   (c (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+  )
+ )
+)

test_regress/t/t_timing_trace_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_timing_trace.v"
+
+test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_abort_saif.out

@@ -0,0 +1,22 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 75)
+ (INSTANCE top
+  (NET
+   (clk (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 14))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 14))
+    (cyc\[0\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (cyc\[1\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 35) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+ )
+)

test_regress/t/t_trace_abort_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_abort.v"
+test.golden_filename = "t/t_trace_abort_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif'])
+
+test.execute(fails=True)
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_array_saif.out

@@ -0,0 +1,62 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 60)
+ (INSTANCE top
+  (NET
+   (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE biggie
+    (NET
+     (d\[1\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[4\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[5\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[6\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[7\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[8\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[9\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (d\[10\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (d\[11\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (d\[12\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (d\[13\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (d\[14\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[15\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[16\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[17\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[18\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[19\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[20\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[21\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (d\[22\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (d\[23\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[24\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[25\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (d\[26\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[27\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[28\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (d\[29\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (d\[30\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[31\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[32\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[33\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[35\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (d\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_array_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_array_saif_portable.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_array_saif_threads_1.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_array_saif_threads_2.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_ascendingrange_saif.py

@@ -0,0 +1,26 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_ascendingrange.v"
+test.golden_filename = "t/t_trace_ascendingrange_saif.out"
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# Strangely, asking for more threads makes it go away.
+test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'],
+             threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_complex_params_saif.out

@@ -0,0 +1,107 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 60)
+ (INSTANCE top
+  (NET
+   (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+  )
+  (INSTANCE $unit
+   (NET
+    (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_unip_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_unip_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_str32x2\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[32\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_str32x2\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_enumb2_str\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (v_enumb2_str\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb2_str\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (v_enumb2_str\[4\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb2_str\[5\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+   )
+   (INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed
+    (NET
+     (PARAM\[2\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE p2
+    (NET
+     (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE p3
+    (NET
+     (PARAM\[0\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE unnamedblk1
+    (NET
+     (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE unnamedblk2
+     (NET
+      (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_complex_params_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_params_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_complex_saif.out

@@ -0,0 +1,107 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 60)
+ (INSTANCE top
+  (NET
+   (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+  )
+  (INSTANCE $unit
+   (NET
+    (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_unip_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_unip_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_str32x2\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_str32x2\[32\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_str32x2\[34\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_enumb2_str\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (v_enumb2_str\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb2_str\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (v_enumb2_str\[4\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb2_str\[5\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+   )
+   (INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed
+    (NET
+     (PARAM\[2\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE p2
+    (NET
+     (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE p3
+    (NET
+     (PARAM\[0\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (PARAM\[1\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE unnamedblk1
+    (NET
+     (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE unnamedblk2
+     (NET
+      (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_complex_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_complex_saif_threads_1.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_complex_saif_threads_2.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_complex_structs_saif.out

@@ -0,0 +1,145 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 60)
+ (INSTANCE top
+  (NET
+   (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+  )
+  (INSTANCE $unit
+   (NET
+    (global_bit (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+   )
+   (INSTANCE v_strp
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_strp_strp
+    (INSTANCE x1
+     (NET
+      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     )
+    )
+    (INSTANCE x0
+     (NET
+      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     )
+    )
+   )
+   (INSTANCE v_unip_strp
+    (INSTANCE x1
+     (NET
+      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     )
+    )
+    (INSTANCE x0
+     (NET
+      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     )
+    )
+   )
+   (INSTANCE v_arrp_strp[3]
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_arrp_strp[4]
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_arru_strp[3]
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_arru_strp[4]
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_str32x2[0]
+    (NET
+     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (data\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (data\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE v_str32x2[1]
+    (NET
+     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE v_enumb2_str
+    (NET
+     (a\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (a\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (a\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (b\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (b\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (b\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    )
+   )
+   (INSTANCE unnamedblk1
+    (NET
+     (b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE unnamedblk2
+     (NET
+      (a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_complex_structs_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_structs_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_dumpvars_dyn.cpp

@@ -15,6 +15,10 @@
 #include <verilated_vcd_c.h>
 #define TRACE_FILE_NAME "simx.vcd"
 #define TRACE_CLASS VerilatedVcdC
+#elif VM_TRACE_SAIF
+#include <verilated_saif_c.h>
+#define TRACE_FILE_NAME "simx.saif"
+#define TRACE_CLASS VerilatedSaifC
 #endif
 
 #include <memory>
@@ -35,9 +39,11 @@ int main(int argc, char** argv) {
 
     std::unique_ptr<TRACE_CLASS> tfp{new TRACE_CLASS};
 
-#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0)
+#if defined(T_TRACE_DUMPVARS_DYN_VCD_0) || defined(T_TRACE_DUMPVARS_DYN_FST_0) \
+    || defined(T_TRACE_DUMPVARS_DYN_SAIF_0)
     tfp->dumpvars(0, "");
-#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1)
+#elif defined(T_TRACE_DUMPVARS_DYN_VCD_1) || defined(T_TRACE_DUMPVARS_DYN_FST_1) \
+    || defined(T_TRACE_DUMPVARS_DYN_SAIF_1)
     tfp->dumpvars(99, "t");  // This should not match "top."
     tfp->dumpvars(1, "top.t.cyc");  // A signal
     tfp->dumpvars(1, "top.t.sub1a");  // Scope

test_regress/t/t_trace_dumpvars_dyn_saif_0.out

@@ -0,0 +1,151 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+ (INSTANCE top
+  (NET
+   (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))
+    (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+    (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE sub1a
+    (NET
+     (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE sub2a
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (value\[3\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2b
+     (NET
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (value\[3\] (T0 13) (T1 7) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2c
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (value\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+   (INSTANCE sub1b
+    (NET
+     (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE sub2a
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
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+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2b
+     (NET
+      (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2c
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_dumpvars_dyn_saif_0.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_dumpvars_dyn_saif_1.out

@@ -0,0 +1,106 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+ (INSTANCE top
+  (INSTANCE t
+   (NET
+    (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+    (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE sub1a
+    (NET
+     (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE sub2a
+    )
+    (INSTANCE sub2b
+    )
+    (INSTANCE sub2c
+    )
+   )
+   (INSTANCE sub1b
+    (NET
+     (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+    (INSTANCE sub2a
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2b
+     (NET
+      (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE sub2c
+     (NET
+      (ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_dumpvars_dyn_saif_1.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_enum_saif.out

@@ -0,0 +1,21 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 10)
+ (INSTANCE top
+  (NET
+   (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE sink
+   )
+  )
+ )
+)

test_regress/t/t_trace_enum_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_enum.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_jumps_do_while_saif.out

@@ -0,0 +1,35 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 10)
+ (INSTANCE top
+  (NET
+   (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE unnamedblk1
+    (NET
+     (results\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[2\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[3\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[4\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[5\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[6\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[7\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[8\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[9\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[10\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (results\[11\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_jumps_do_while_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_jumps_do_while.v"
+
+test.compile(verilator_flags2=['--trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_no_top_name2.cpp

@@ -15,6 +15,10 @@
 #include <verilated_vcd_c.h>
 #define TRACE_FILE_NAME "simx.vcd"
 #define TRACE_CLASS VerilatedVcdC
+#elif VM_TRACE_SAIF
+#include <verilated_saif_c.h>
+#define TRACE_FILE_NAME "simx.saif"
+#define TRACE_CLASS VerilatedSaifC
 #endif
 
 #include <memory>

test_regress/t/t_trace_no_top_name2_saif.out

@@ -0,0 +1,33 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 20)
+ (INSTANCE $rootio
+  (NET
+   (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))
+  )
+ )
+ (INSTANCE t
+  (NET
+   (clk (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 20))
+   (cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
+   (cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
+   (cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
+   (cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
+  )
+  (INSTANCE sub
+   (NET
+    (a\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a\[5\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a\[7\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a\[10\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+ )
+)

test_regress/t/t_trace_no_top_name2_saif.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.pli_filename = "t/t_trace_no_top_name2.cpp"
+test.top_filename = "t/t_trace_no_top_name2.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_packed_struct_saif.out

@@ -0,0 +1,39 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 40)
+ (INSTANCE top
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[0]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[1]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[1]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[1]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[1]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[1]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[2]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[2]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[2]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[2]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (v[2]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+ )
+)

test_regress/t/t_trace_packed_struct_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_packed_struct.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_param_saif.out

@@ -0,0 +1,21 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 0)
+ (INSTANCE top
+  (INSTANCE my_module_types
+   (NET
+    (MY_PARAM\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (MY_PARAM\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (MY_PARAM2\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (MY_PARAM2\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+  )
+  (INSTANCE t
+  )
+ )
+)

test_regress/t/t_trace_param_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_param.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_primitive_saif.out

@@ -0,0 +1,33 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 120)
+ (INSTANCE top
+  (NET
+   (clk (T0 65) (T1 55) (TZ 0) (TX 0) (TB 0) (TC 23))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 65) (T1 55) (TZ 0) (TX 0) (TB 0) (TC 23))
+    (cyc\[0\] (T0 60) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 12))
+    (cyc\[1\] (T0 60) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[2\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[3\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (a (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (b (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (z (T0 100) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+   )
+   (INSTANCE sub_t_i
+    (NET
+     (x (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (y (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (z (T0 100) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_primitive_saif.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_primitive.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_saif.out

@@ -0,0 +1,91 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 1000)
+ (INSTANCE top
+  (NET
+   (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+   (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+   (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+   (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+   (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+   (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+    (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
+    (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
+    (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
+    (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
+    (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+    (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+    (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+    (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+    (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+    (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE test
+    (NET
+     (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+     (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+     (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
+     (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
+     (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+     (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47))
+     (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
+     (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
+    )
+    (INSTANCE unnamedblk1
+     (NET
+      (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE unnamedblk2
+     (NET
+      (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_saif.py

@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.top_filename = "t/t_trace_fst.v"
+test.golden_filename = "t/t_trace_saif.out"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_saif_cmake.out

@@ -0,0 +1,91 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 1000)
+ (INSTANCE top
+  (NET
+   (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+   (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+   (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+   (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+   (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+   (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+    (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
+    (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
+    (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25))
+    (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
+    (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+    (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+    (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+    (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+    (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+    (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE test
+    (NET
+     (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199))
+     (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+     (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
+     (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
+     (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
+     (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47))
+     (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
+     (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
+     (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
+     (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47))
+    )
+    (INSTANCE unnamedblk1
+     (NET
+      (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+    (INSTANCE unnamedblk2
+     (NET
+      (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+    )
+   )
+  )
+ )
+)

test_regress/t/t_trace_saif_cmake.py

@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.top_filename = "t/t_trace_fst_cmake.v"
+
+test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=True)
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_trace_saif_sc.out

@@ -0,0 +1,83 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 1004)
+(INSTANCE top
+  (INSTANCE t
+    (NET
+      (clk (T0 505) (T1 499) (TX 0) (TC 199))
+      (cyc\[0\] (T0 504) (T1 500) (TX 0) (TC 100))
+      (cyc\[1\] (T0 504) (T1 500) (TX 0) (TC 50))
+      (cyc\[2\] (T0 520) (T1 484) (TX 0) (TC 25))
+      (cyc\[3\] (T0 524) (T1 480) (TX 0) (TC 12))
+      (cyc\[4\] (T0 524) (T1 480) (TX 0) (TC 6))
+      (cyc\[5\] (T0 640) (T1 364) (TX 0) (TC 3))
+      (cyc\[6\] (T0 640) (T1 364) (TX 0) (TC 1))
+      (rstn (T0 110) (T1 894) (TX 0) (TC 1))
+      (fst_parameter\[0\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_parameter\[1\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_parameter\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_parameter\[4\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_parameter\[5\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_parameter\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_lparam\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_lparam\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_lparam\[7\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_lparam\[8\] (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_supply1 (T0 0) (T1 1004) (TX 0) (TC 1))
+      (fst_tri1 (T0 0) (T1 1004) (TX 0) (TC 1))
+      (state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
+      (state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
+      (state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
+      (state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
+      (state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
+    )
+    (INSTANCE test
+      (NET
+        (clk (T0 505) (T1 499) (TX 0) (TC 199))
+        (rstn (T0 110) (T1 894) (TX 0) (TC 1))
+        (state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
+        (state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
+        (state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
+        (state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
+        (state_w\[0\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_w\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_w\[2\] (T0 434) (T1 570) (TX 0) (TC 46))
+        (state_w\[3\] (T0 530) (T1 474) (TX 0) (TC 47))
+        (state_w\[4\] (T0 424) (T1 580) (TX 0) (TC 48))
+        (state_array[0]\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
+        (state_array[0]\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
+        (state_array[0]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[0]\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
+        (state_array[0]\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
+        (state_array[1]\[0\] (T0 420) (T1 584) (TX 0) (TC 47))
+        (state_array[1]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[1]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[1]\[3\] (T0 540) (T1 464) (TX 0) (TC 45))
+        (state_array[1]\[4\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[2]\[0\] (T0 424) (T1 580) (TX 0) (TC 48))
+        (state_array[2]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[2]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[2]\[3\] (T0 534) (T1 470) (TX 0) (TC 46))
+        (state_array[2]\[4\] (T0 530) (T1 474) (TX 0) (TC 47))
+      )
+      (INSTANCE unnamedblk1
+        (NET
+          (i\[0\] (T0 10) (T1 994) (TX 0) (TC 1))
+          (i\[1\] (T0 10) (T1 994) (TX 0) (TC 1))
+        )
+      )
+      (INSTANCE unnamedblk2
+        (NET
+          (i\[1\] (T0 120) (T1 884) (TX 0) (TC 1))
+        )
+      )
+    )
+  )
+)
+)

test_regress/t/t_trace_saif_sc.py

@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.top_filename = "t/t_trace_fst_sc.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=["--trace-saif --sc"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()

test_regress/t/t_verilated_all.py

@@ -46,7 +46,7 @@ for dfile in test.glob_some(test.obj_dir + "/*.d"):
 
 for filename in sorted(hit.keys()):
     if (not hit[filename] and not re.search(r'_sc', filename) and not re.search(r'_fst', filename)
-            and not re.search(r'_thread', filename)
+            and not re.search(r'_saif', filename) and not re.search(r'_thread', filename)
             and (not re.search(r'_timing', filename) or test.have_coroutines)):
         test.error("Include file not covered by t_verilated_all test: ", filename)
 

verilator-config.cmake.in

@@ -142,6 +142,13 @@ define_property(
     FULL_DOCS "Verilator FST trace enabled"
 )
 
+define_property(
+    TARGET
+    PROPERTY VERILATOR_TRACE_SAIF
+    BRIEF_DOCS "Verilator SAIF trace enabled"
+    FULL_DOCS "Verilator SAIF trace enabled"
+)
+
 define_property(
     TARGET
     PROPERTY VERILATOR_SYSTEMC
@@ -206,6 +213,10 @@ function(verilate TARGET)
         list(APPEND VERILATOR_ARGS --trace-fst)
     endif()
 
+    if(VERILATE_TRACE_SAIF)
+        list(APPEND VERILATOR_ARGS --trace-saif)
+    endif()
+
     if(VERILATE_SYSTEMC)
         list(APPEND VERILATOR_ARGS --sc)
     else()
@@ -377,6 +388,12 @@ function(verilate TARGET)
         set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON)
     endif()
 
+    if(${VERILATE_PREFIX}_TRACE_SAIF)
+        # If any verilate() call specifies TRACE_SAIF, define VM_TRACE_SAIF in the final build
+        set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON)
+        set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_SAIF ON)
+    endif()
+
     if(${VERILATE_PREFIX}_SC)
         # If any verilate() call specifies SYSTEMC, define VM_SC in the final build
         set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON)
@@ -455,6 +472,7 @@ function(verilate TARGET)
             VM_TRACE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE>>
             VM_TRACE_VCD=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_VCD>>
             VM_TRACE_FST=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_FST>>
+            VM_TRACE_SAIF=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_SAIF>>
     )
 
     target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS})