test extensions

test_regress/t/t_dfg_break_cycles.py

@@ -112,6 +112,9 @@ if coveredLines != expectedLines:
     for n in sorted(coveredLines - expectedLines):
         test.error_keep_going(f"V3DfgBreakCycles.cpp line {n} covered but not expected")
 
+test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt",
+                   r'DFG.*non-representable.*\s[1-9]\d*$')
+
 # Execute test to check equivalence
 test.execute(executable=test.obj_dir + "/obj_opt/Vopt")
 

test_regress/t/t_dfg_peephole.cpp

@@ -29,8 +29,10 @@ int main(int, char**) {
 
     uint64_t rand_a = 0x5aef0c8dd70a4497;
     uint64_t rand_b = 0xf0c0a8dd75ae4497;
-    uint64_t srand_a = 0x00fa8dcc7ae4957;
-    uint64_t srand_b = 0x0fa8dc7ae3c9574;
+    uint64_t srand_a = 0x000fa8dcc7ae4957;
+    uint64_t srand_b = 0x00fa8dc7ae3c9574;
+    uint64_t arand_a = 0x758c168d16c93a0f;
+    uint64_t arand_b = 0xbe01de017d87355d;
 
     for (size_t n = 0; n < 200000; ++n) {
         // Update rngs
@@ -38,12 +40,16 @@ int main(int, char**) {
         rngUpdate(rand_b);
         rngUpdate(srand_a);
         rngUpdate(srand_b);
+        rngUpdate(arand_a);
+        rngUpdate(arand_b);
 
         // Assign inputs
         ref.rand_a = opt.rand_a = rand_a;
         ref.rand_b = opt.rand_b = rand_b;
         ref.srand_a = opt.srand_a = srand_a;
         ref.srand_b = opt.srand_b = srand_b;
+        ref.arand_a = opt.arand_a = arand_a;
+        ref.arand_b = opt.arand_b = arand_b;
 
         // Evaluate both models
         ref.eval();

test_regress/t/t_dfg_peephole.py

@@ -88,9 +88,6 @@ test.compile(verilator_flags2=[
     "../../t/" + test.name + ".cpp"
 ])  # yapf:disable
 
-# Execute test to check equivalence
-test.execute(executable=test.obj_dir + "/obj_opt/Vopt")
-
 
 def check(name):
     name = name.lower()
@@ -103,4 +100,10 @@ def check(name):
 for opt in optimizations:
     check(opt)
 
+test.file_grep_not(test.obj_dir + "/obj_opt/Vopt__stats.txt",
+                   r'DFG.*non-representable.*\s[1-9]\d*$')
+
+# Execute test to check equivalence
+test.execute(executable=test.obj_dir + "/obj_opt/Vopt")
+
 test.passes()

test_regress/t/t_dfg_peephole.v

@@ -8,7 +8,7 @@
 
 module t (
 `include "portlist.vh" // Boilerplate generated by t_dfg_peephole.py
-          rand_a, rand_b, srand_a, srand_b
+          rand_a, rand_b, srand_a, srand_b, arand_a, arand_b
           );
 
 `include "portdecl.vh" // Boilerplate generated by t_dfg_peephole.py
@@ -17,10 +17,16 @@ module t (
    input rand_b;
    input srand_a;
    input srand_b;
+   input arand_a;
+   input arand_b;
    wire logic        [63:0] rand_a;
    wire logic        [63:0] rand_b;
    wire logic signed [63:0] srand_a;
    wire logic signed [63:0] srand_b;
+   // verilator lint_off ASCRANGE
+   wire logic        [0:63] arand_a;
+   wire logic        [0:63] arand_b;
+   // verilator lint_on ASCRANGE
 
    wire        logic randbit_a = rand_a[0];
    wire        logic [127:0] rand_ba = {rand_b, rand_a};
@@ -228,6 +234,15 @@ module t (
    `signal(PUSH_SEL_THROUGH_SHIFTL, sel_from_shiftl[20:0]);
    `signal(REPLACE_SEL_FROM_SEL, sel_from_sel[4:3]);
 
+   // Asscending ranges
+   `signal(ASCENDNG_SEL, arand_a[0:4]);
+   // verilator lint_off ASCRANGE
+   wire [0:7] ascending_assign;
+   // verilator lint_on ASCRANGE
+   assign ascending_assign[0:3] = arand_a[4:7];
+   assign ascending_assign[4:7] = arand_b[0:3];
+   `signal(ASCENDING_ASSIGN, ascending_assign);
+
    // Sel from not requires the operand to have a sinle sink, so can't use
    // the chekc due to the raw expression referencing the operand
    wire [63:0] sel_from_not_tmp = ~(rand_a >> rand_b[2:0] << rand_a[3:0]);