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verilator
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This commit is contained in:
Wilson Snyder 2017-08-31 19:45:53 -04:00
parent 5f26b9ec66
commit a221278c05
1 changed files with 2 additions and 2 deletions
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@ -483,7 +483,7 @@ interest in adding more traditional CDC checks, please contact the authors.
Sometimes it is quite difficult for Verilator to distinguish clock signals from Sometimes it is quite difficult for Verilator to distinguish clock signals from
other data signals. Occasionally the clock signals can end up in the checking other data signals. Occasionally the clock signals can end up in the checking
list of signals which determines if further evaluation is needed. This will list of signals which determines if further evaluation is needed. This will
heavily degrade the performance of verilated model. heavily degrade the performance of a Verilated model.
With --clk <signal-name>, user can specified root clock into the model, then With --clk <signal-name>, user can specified root clock into the model, then
Verilator will mark the signal as clocker and propagate the clocker attribute Verilator will mark the signal as clocker and propagate the clocker attribute
@ -513,7 +513,7 @@ breaking deep structures as for msvc as described below.
=item gcc =item gcc
Tune for Gnu C++, although generated code should work on almost any Tune for GNU C++, although generated code should work on almost any
compliant C++ compiler. Currently the default. compliant C++ compiler. Currently the default.
=item msvc =item msvc