Fix no-module include files on command line. [Stefan Thiede]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1009 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.66***
+
+**** Fix no-module include files on command line.  [Stefan Thiede]
+
 * Verilator 3.660 2008/03/23
 
 ***  Add support for hard-coding VERILATOR_ROOT etc in the executables,

src/V3LinkDot.cpp

@@ -379,17 +379,20 @@ private:
 	// This may not be the module with isTop() set, as early in the steps,
 	// wrapTop may have not been created yet.
 	AstModule* topmodp = nodep->modulesp();
-	if (!topmodp) nodep->v3fatalSrc("No top level module");
-	UINFO(8,"Top Module: "<<topmodp<<endl);
-	m_scope = "TOP";
-	m_cellVxp = m_statep->insertTopCell(topmodp, m_scope);
-	m_inlineVxp = m_cellVxp;
-	{
-	    topmodp->accept(*this);
+	if (!topmodp) {
+	    nodep->v3error("No top level module found");
+	} else {
+	    UINFO(8,"Top Module: "<<topmodp<<endl);
+	    m_scope = "TOP";
+	    m_cellVxp = m_statep->insertTopCell(topmodp, m_scope);
+	    m_inlineVxp = m_cellVxp;
+	    {
+		topmodp->accept(*this);
+	    }
+	    m_scope = "";
+	    m_cellVxp = NULL;
+	    m_inlineVxp = m_cellVxp;
 	}
-	m_scope = "";
-	m_cellVxp = NULL;
-	m_inlineVxp = m_cellVxp;
     }
     virtual void visit(AstModule* nodep, AstNUser*) {
 	UINFO(8,"   "<<nodep<<endl);

src/verilog.y

@@ -429,7 +429,7 @@ class AstSenTree;
 %type<nodep>	pslDecl
 %type<nodep>	pslSequence pslSere pslExpr
 
-%start file
+%start fileE
 
 %%
 //**********************************************************************
@@ -445,8 +445,12 @@ statePop:	/* empty */			 	{ V3Read::statePop(); }
 //**********************************************************************
 // Files
 
-file:		description 				{ }
-	|	file description 			{ }
+fileE:		/* empty */				{ }
+	|	file					{ }
+	;
+
+file:		description				{ }
+	|	file description			{ }
 	;
 
 // IEEE: description

test_regress/t/t_flag_nomod_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>$Last_Self->{v3},
+	 expect=>
+'%Error: No top level module found
+%Error: Exiting due to',
+	 ) if $Last_Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_flag_nomod_bad.v

@@ -0,0 +1,7 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+`define EMPTY 1