Support generated classes (#5665).
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@ -13,6 +13,7 @@ Verilator 5.033 devel
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**Minor:**
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* Support generated classes (#5665). [Shou-Li Hsu]
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* Fix error message when call task as a function (#3089). [Matthew Ballance]
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* Fix V3Simulate constant reuse (#5709). [Geza Lore]
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* Fix man pages what-is section (#5710). [Ahmed El-Mahmoudy]
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@ -148,6 +148,18 @@ class BeginVisitor final : public VNVisitor {
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void visit(AstNodeModule* nodep) override {
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VL_RESTORER(m_modp);
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m_modp = nodep;
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// Rename it (e.g. class under a generate)
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if (m_unnamedScope != "") {
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nodep->name(dot(m_unnamedScope, nodep->name()));
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UINFO(8, " rename to " << nodep->name() << endl);
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m_statep->userMarkChanged(nodep);
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}
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VL_RESTORER(m_displayScope);
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VL_RESTORER(m_namedScope);
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VL_RESTORER(m_unnamedScope);
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m_displayScope = "";
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m_namedScope = "";
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m_unnamedScope = "";
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iterateChildren(nodep);
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}
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void visit(AstNodeFTask* nodep) override {
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@ -17,7 +17,8 @@
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/
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// Inputs
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@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2025 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=['--binary'])
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test.execute()
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test.passes()
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@ -0,0 +1,67 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module Child;
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int ch_value;
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endmodule
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module Parent;
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for (genvar i = 0; i < 10; i++) begin : gen_child
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Child child();
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end
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endmodule
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module t;
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Parent parent();
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virtual class ChildAgentBase;
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pure virtual task preload(int value);
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pure virtual function string name();
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endclass
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ChildAgentBase child_agents[10];
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for (genvar i = 0; i < 10; i++) begin : gfor
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class ChildAgent extends ChildAgentBase;
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task automatic preload(int value);
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parent.gen_child[i].child.ch_value = value;
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endtask
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function string name();
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return $sformatf("%m");
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endfunction
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endclass
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ChildAgent agent = new();
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initial child_agents[i] = agent;
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end
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task automatic preload_children;
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for (int i = 0; i < 10; i++) begin
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child_agents[i].preload(i);
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end
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endtask
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string s;
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initial begin
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#1; // Ensure all class instances are initialized
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preload_children();
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`checkh(parent.gen_child[3].child.ch_value, 3);
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`checkh(parent.gen_child[8].child.ch_value, 8);
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`ifdef VERILATOR
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// Some legal examples "t.gfor[4].\ChildAgent::name", "t.gfor[4].ChildAgent.name"
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`checks(child_agents[4].name(), "t.gfor[4].ChildAgent.name");
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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