Fix LATCH warning for automatic variables (#5918)

src/V3Active.cpp

@@ -314,7 +314,7 @@ class ActiveLatchCheckVisitor final : public VNVisitorConst {
     void visit(AstVarRef* nodep) override {
         const AstVar* const varp = nodep->varp();
         if (nodep->access().isWriteOrRW() && varp->isSignal() && !varp->isUsedLoopIdx()
-            && !varp->isFuncLocalSticky()) {
+            && !varp->isFuncLocalSticky() && !varp->lifetime().isAutomatic()) {
             m_graph.addAssignment(nodep);
         }
     }

test_regress/t/t_lint_latch_8.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint()
+
+test.passes()

test_regress/t/t_lint_latch_8.v

@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Yutetsu TAKATSUKASA
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module t(input wire clk);
+
+   logic [2:0] v = 3'd0;
+   logic [2:0] v_plus_1;
+
+   always_comb begin : blk_comb
+      if (v[0]) begin : blk_if
+          automatic logic [2:0] tmp0;  // This automatic variable cannot be a latch
+          tmp0 = v + 3'd1;
+          v_plus_1 = tmp0;
+      end else begin : blk_else
+          v_plus_1 = v | 3'd1;
+      end
+   end
+
+   always @(posedge clk) begin : blk_ff
+      automatic logic [2:0] tmp_auto;
+      tmp_auto = v_plus_1;
+      v <= tmp_auto;
+      $display("v:%d", v);
+  end
+
+endmodule