Tests: Add t_param_type_bad3
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@ -3341,8 +3341,8 @@ class LinkDotResolveVisitor final : public VNVisitor {
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nodep->replaceWith(newp);
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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}
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} else if (AstConstraint* const consp = VN_CAST(foundp->nodep(), Constraint)) {
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AstNode* const newp = new AstConstraintRef{nodep->fileline(), nullptr, consp};
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} else if (AstConstraint* const defp = VN_CAST(foundp->nodep(), Constraint)) {
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AstNode* const newp = new AstConstraintRef{nodep->fileline(), nullptr, defp};
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nodep->replaceWith(newp);
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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ok = true;
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@ -928,7 +928,7 @@ class ParamProcessor final {
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for (auto* stmtp = srcModpr->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
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if (AstParamTypeDType* dtypep = VN_CAST(stmtp, ParamTypeDType)) {
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if (VN_IS(dtypep->subDTypep(), VoidDType)) {
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if (VN_IS(dtypep->skipRefp(), VoidDType)) {
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nodep->v3error(
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"Class parameter type without default value is never given value"
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<< " (IEEE 1800-2023 6.20.1): " << dtypep->prettyNameQ());
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@ -1217,7 +1217,7 @@ class ParamVisitor final : public VNVisitor {
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}
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void visit(AstParamTypeDType* nodep) override {
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iterateChildren(nodep);
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if (VN_IS(nodep->subDTypep(), VoidDType)) {
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if (VN_IS(nodep->skipRefp(), VoidDType)) {
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nodep->v3error("Parameter type without default value is never given value"
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<< " (IEEE 1800-2023 6.20.1): " << nodep->prettyNameQ());
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}
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@ -0,0 +1,5 @@
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%Error: t/t_param_type_bad3.v:9:26: Expecting a data type: 'PI'
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9 | localparam type P_T = PI;
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| ^~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: Exiting due to
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@ -0,0 +1,20 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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test.lint(
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# Bug1575 required trace to crash
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verilator_flags2=["--trace-vcd"],
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fails=True,
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expect_filename=test.golden_filename)
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test.passes()
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@ -0,0 +1,10 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam int PI = 6;
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localparam type P_T = PI; // Bad
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endmodule
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