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Tests/examples: Remove some legacy Verilator:: calls.

This commit is contained in:
Wilson Snyder 2022-07-09 09:50:50 -04:00
parent 5f3316d3dc
commit d8ea989eda
21 changed files with 258 additions and 285 deletions
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69
docs/guide/connecting.rst
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@ -86,61 +86,17 @@ Connecting to C++
In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
simple C++ class. The user must write a C++ wrapper and main loop for the simple C++ class. The user must write a C++ wrapper and main loop for the
simulation, which instantiates the model class, and link with the Verilated simulation, which instantiates the model class, and link with the Verilated
model. Here is a simple example: model.
.. code-block:: C++ Refer to ``examples/make_tracing_c`` in the distribution for a detailed
commented example.
#include <verilated.h> // Defines common routines Top level IO signals are read and written as members of the model. You
#include <iostream> // Need std::cout call the model's :code:`eval()` method to evaluate the model. When the
#include "Vtop.h" // From Verilating "top.v" simulation is complete call the model's :code:`final()` method to execute
any SystemVerilog final blocks, and complete any assertions. See
:ref:`Evaluation Loop`.
Vtop *top; // Instantiation of model
uint64_t main_time = 0; // Current simulation time
// This is a 64-bit integer to reduce wrap over issues and
// allow modulus. This is in units of the timeprecision
// used in Verilog (or from --timescale-override)
double sc_time_stamp() { // Called by $time in Verilog
return main_time; // converts to double, to match
// what SystemC does
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
top = new Vtop; // Create model
// Do not instead make Vtop as a file-scope static
// variable, as the "C++ static initialization order fiasco"
// may cause a crash
top->reset_l = 0; // Set some inputs
while (!Verilated::gotFinish()) {
if (main_time > 10) {
top->reset_l = 1; // Deassert reset
}
if ((main_time % 10) == 1) {
top->clk = 1; // Toggle clock
}
if ((main_time % 10) == 6) {
top->clk = 0;
}
top->eval(); // Evaluate model
cout << top->out << endl; // Read a output
main_time++; // Time passes...
}
top->final(); // Done simulating
// // (Though this example doesn't get here)
delete top;
}
Note top level IO signals are read and written as members of the model. You
call the :code:`eval()` method to evaluate the model. When the simulation is
complete call the :code:`final()` method to execute any SystemVerilog final
blocks, and complete any assertions. See :ref:`Evaluation Loop`.
Connecting to SystemC Connecting to SystemC
@ -449,14 +405,15 @@ accesses the above signal "readme" would be:
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
Vour* top = new Vour; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::internalsDump(); // See scopes to help debug const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
while (!Verilated::gotFinish()) {
contextp->internalsDump(); // See scopes to help debug
while (!contextp->gotFinish()) {
top->eval(); top->eval();
VerilatedVpi::callValueCbs(); // For signal callbacks VerilatedVpi::callValueCbs(); // For signal callbacks
read_and_check(); read_and_check();
} }
delete top;
return 0; return 0;
} }
EOF EOF

4
docs/guide/exe_sim.rst
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@ -8,7 +8,7 @@ Simulation Runtime Arguments
The following are the arguments that may be passed to a Verilated The following are the arguments that may be passed to a Verilated
executable, provided that executable calls executable, provided that executable calls
:code:`Verilated::commandArgs()`. :code:`VerilatedContext*->commandArgs(argc, argv)`.
All simulation runtime arguments begin with "+verilator", so that the All simulation runtime arguments begin with "+verilator", so that the
user's executable may skip over all "+verilator" arguments when parsing its user's executable may skip over all "+verilator" arguments when parsing its
@ -96,7 +96,7 @@ Summary:
.. option:: +verilator+noassert .. option:: +verilator+noassert
Disable assert checking per runtime argument. This is the same as Disable assert checking per runtime argument. This is the same as
calling :code:`Verilated::assertOn(false)` in the model. calling :code:`VerilatedContext*->assertOn(false)` in the model.
.. option:: +verilator+V .. option:: +verilator+V

2
docs/guide/languages.rst
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@ -489,7 +489,7 @@ $test$plusargs, $value$plusargs
.. code-block:: C++ .. code-block:: C++
Verilated::commandArgs(argc, argv); {VerilatedContext*} ->commandArgs(argc, argv);
to register the command line before calling $test$plusargs or to register the command line before calling $test$plusargs or
$value$plusargs. $value$plusargs.

7
examples/make_hello_c/sim_main.cpp
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@ -21,11 +21,14 @@ int main(int argc, char** argv, char** env) {
// Prevent unused variable warnings // Prevent unused variable warnings
if (false && argc && argv && env) {} if (false && argc && argv && env) {}
// Construct a VerilatedContext to hold simulation time, etc.
VerilatedContext* contextp = new VerilatedContext;
// Construct the Verilated model, from Vtop.h generated from Verilating "top.v" // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
Vtop* top = new Vtop; Vtop* top = new Vtop{contextp};
// Simulate until $finish // Simulate until $finish
while (!Verilated::gotFinish()) { while (!contextp->gotFinish()) {
// Evaluate model // Evaluate model
top->eval(); top->eval();

79
test_regress/t/t_dpi_accessors.cpp
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@ -26,11 +26,9 @@ using std::hex;
using std::setfill; using std::setfill;
using std::setw; using std::setw;
double sc_time_stamp() { return 0; }
// Convenience function to check we didn't finish unexpectedly // Convenience function to check we didn't finish unexpectedly
static void checkFinish(const char* msg) { static void checkFinish(VerilatedContext* contextp, const char* msg) {
if (Verilated::gotFinish()) { if (contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "dut", msg); vl_fatal(__FILE__, __LINE__, "dut", msg);
exit(1); exit(1);
} }
@ -61,7 +59,9 @@ static void checkResult(bool p, const char* msg_fail) {
// Main function instantiates the model and steps through the test. // Main function instantiates the model and steps through the test.
int main() { int main() {
Vt_dpi_accessors* dut = new Vt_dpi_accessors("dut"); const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
const std::unique_ptr<VM_PREFIX> dut{new VM_PREFIX{contextp.get(), "dut"}};
svScope scope = svGetScopeFromName("dut.t"); svScope scope = svGetScopeFromName("dut.t");
if (!scope) vl_fatal(__FILE__, __LINE__, "dut", "No svGetScopeFromName result"); if (!scope) vl_fatal(__FILE__, __LINE__, "dut", "No svGetScopeFromName result");
svSetScope(scope); svSetScope(scope);
@ -112,7 +112,7 @@ int main() {
cout << "===============================\n"; cout << "===============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = (int)a_read(); a = (int)a_read();
logReg(dut->clk, "read a", a, " (before clk)"); logReg(dut->clk, "read a", a, " (before clk)");
@ -130,7 +130,7 @@ int main() {
"Test of scalar register reading failed."); "Test of scalar register reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read a vector register. // Check we can read a vector register.
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -138,7 +138,7 @@ int main() {
cout << "===============================\n"; cout << "===============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
logRegHex(dut->clk, "read b", 8, b, " (before clk)"); logRegHex(dut->clk, "read b", 8, b, " (before clk)");
@ -153,7 +153,7 @@ int main() {
"Test of vector register reading failed."); "Test of vector register reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Test we can read an array element // Test we can read an array element
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -162,7 +162,7 @@ int main() {
cout << "=============================\n"; cout << "=============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int)mem32_read(); mem32 = (int)mem32_read();
logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)"); logRegHex(dut->clk, "read mem32", 8, mem32, " (before clk)");
@ -177,7 +177,7 @@ int main() {
checkResult(mem32 == 0x20, "Test of array element reading failed."); checkResult(mem32 == 0x20, "Test of array element reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read a scalar wire // Check we can read a scalar wire
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -186,7 +186,7 @@ int main() {
cout << "===========================\n"; cout << "===========================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = (int)a_read(); a = (int)a_read();
c = (int)c_read(); c = (int)c_read();
@ -206,7 +206,7 @@ int main() {
checkResult(c == (1 - a), "Test of scalar wire reading failed."); checkResult(c == (1 - a), "Test of scalar wire reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read a vector wire // Check we can read a vector wire
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -215,7 +215,7 @@ int main() {
cout << "===========================\n"; cout << "===========================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
d = (int)d_read(); d = (int)d_read();
@ -236,7 +236,7 @@ int main() {
checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed."); checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can write a scalar register // Check we can write a scalar register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -245,7 +245,7 @@ int main() {
cout << "===============================\n"; cout << "===============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
a = 1 - (int)a_read(); a = 1 - (int)a_read();
a_write(reinterpret_cast<const svBitVecVal*>(&a)); a_write(reinterpret_cast<const svBitVecVal*>(&a));
@ -265,7 +265,7 @@ int main() {
"Test of scalar register writing failed."); "Test of scalar register writing failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can write a vector register // Check we can write a vector register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -274,7 +274,7 @@ int main() {
cout << "===============================\n"; cout << "===============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read() - 1; b = (int)b_read() - 1;
b_write(reinterpret_cast<const svBitVecVal*>(&b)); b_write(reinterpret_cast<const svBitVecVal*>(&b));
@ -294,7 +294,7 @@ int main() {
"Test of vector register writing failed."); "Test of vector register writing failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Test we can write an array element // Test we can write an array element
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -303,7 +303,7 @@ int main() {
cout << "=============================\n"; cout << "=============================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int)mem32_read() - 1; mem32 = (int)mem32_read() - 1;
mem32_write(reinterpret_cast<const svBitVecVal*>(&mem32)); mem32_write(reinterpret_cast<const svBitVecVal*>(&mem32));
@ -323,7 +323,7 @@ int main() {
checkResult(mem32_after == mem32, "Test of array element writing failed."); checkResult(mem32_after == mem32, "Test of array element writing failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read a vector register slice // Check we can read a vector register slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -332,7 +332,7 @@ int main() {
cout << "=====================================\n"; cout << "=====================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
int b_slice = (int)b_slice_read(); int b_slice = (int)b_slice_read();
@ -350,7 +350,7 @@ int main() {
checkResult(b_slice == (b & 0x0f), "Test of vector register slice reading failed."); checkResult(b_slice == (b & 0x0f), "Test of vector register slice reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Test we can read an array element slice // Test we can read an array element slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -359,7 +359,7 @@ int main() {
cout << "===================================\n"; cout << "===================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int)mem32_read(); mem32 = (int)mem32_read();
int mem32_slice = (int)mem32_slice_read(); int mem32_slice = (int)mem32_slice_read();
@ -379,7 +379,7 @@ int main() {
"Test of array element slice reading failed."); "Test of array element slice reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read a vector wire slice // Check we can read a vector wire slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -388,7 +388,7 @@ int main() {
cout << "=================================\n"; cout << "=================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
d = (int)d_read(); d = (int)d_read();
@ -410,7 +410,7 @@ int main() {
checkResult(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed."); checkResult(d_slice == ((d & 0x7e) >> 1), "Test of vector wire slice reading failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can write a vector register slice // Check we can write a vector register slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -419,7 +419,7 @@ int main() {
cout << "=====================================\n"; cout << "=====================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
@ -449,7 +449,7 @@ int main() {
logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)"); logRegHex(dut->clk, "read b [3:0]", 4, b_slice, " (after clk)");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Test we can write an array element slice // Test we can write an array element slice
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -458,7 +458,7 @@ int main() {
cout << "===================================\n"; cout << "===================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
mem32 = (int)mem32_read(); mem32 = (int)mem32_read();
@ -494,7 +494,7 @@ int main() {
"Test of array element slice writing failed."); "Test of array element slice writing failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Check we can read complex registers // Check we can read complex registers
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -503,7 +503,7 @@ int main() {
cout << "================================\n"; cout << "================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
@ -540,9 +540,9 @@ int main() {
cout << endl; cout << endl;
#endif #endif
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
e = 0x05 | (i << 4); e = 0x05 | (i << 4);
@ -574,7 +574,7 @@ int main() {
"Test of complex register reading l2 failed."); "Test of complex register reading l2 failed.");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Test we can write a complex register // Test we can write a complex register
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -583,7 +583,7 @@ int main() {
cout << "================================\n"; cout << "================================\n";
#endif #endif
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
b = (int)b_read(); b = (int)b_read();
@ -632,9 +632,9 @@ int main() {
cout << endl; cout << endl;
#endif #endif
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
for (int i = 0; !Verilated::gotFinish() && (i < 4); i++) { for (int i = 0; !contextp->gotFinish() && (i < 4); i++) {
dut->clk = 1 - dut->clk; dut->clk = 1 - dut->clk;
e = (int)e_read(); e = (int)e_read();
@ -671,11 +671,10 @@ int main() {
logRegHex(dut->clk, "read l2", 8, l2, " (before clk)"); logRegHex(dut->clk, "read l2", 8, l2, " (before clk)");
} }
checkFinish("t_dpi_accessors unexpected finish"); checkFinish(contextp.get(), "t_dpi_accessors unexpected finish");
// Tidy up // Tidy up
dut->final(); dut->final();
VL_DO_DANGLING(delete dut, dut);
cout << "*-* All Finished *-*\n"; cout << "*-* All Finished *-*\n";
} }

26
test_regress/t/t_dpi_var.cpp
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@ -110,39 +110,39 @@ void mon_eval() {
//====================================================================== //======================================================================
unsigned int main_time = 0;
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
// clang-format off // clang-format off
#ifdef VERILATOR #ifdef VERILATOR
# ifdef TEST_VERBOSE # ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
# endif # endif
#endif #endif
// clang-format on // clang-format on
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

9
test_regress/t/t_hier_block_cmake/main.cpp
View File

@ -13,13 +13,14 @@
#include "Vt_hier_block.h" #include "Vt_hier_block.h"
int main(int argc, char *argv[]) { int main(int argc, char *argv[]) {
std::unique_ptr<Vt_hier_block> top{new Vt_hier_block("top")}; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv); std::unique_ptr<Vt_hier_block> top{new Vt_hier_block{contextp.get(), "top"}};
for (int i = 0; i < 100 && !Verilated::gotFinish(); ++i) { contextp->commandArgs(argc, argv);
for (int i = 0; i < 100 && !contextp->gotFinish(); ++i) {
top->eval(); top->eval();
top->clk ^= 1; top->clk ^= 1;
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
top->final(); top->final();

3
test_regress/t/t_leak.cpp
View File

@ -48,11 +48,12 @@ void make_and_destroy() {
#ifdef VL_NO_LEGACY #ifdef VL_NO_LEGACY
VerilatedContext* contextp = new VerilatedContext; VerilatedContext* contextp = new VerilatedContext;
VM_PREFIX* topp = new VM_PREFIX{contextp}; VM_PREFIX* topp = new VM_PREFIX{contextp};
contextp->debug(0);
#else #else
VM_PREFIX* topp = new VM_PREFIX; VM_PREFIX* topp = new VM_PREFIX;
Verilated::debug(0);
#endif #endif
Verilated::debug(0);
topp->eval(); topp->eval();
topp->clk = true; topp->clk = true;
while (! while (!

28
test_regress/t/t_trace_two_cc.cpp
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@ -25,21 +25,21 @@
VM_PREFIX* ap; VM_PREFIX* ap;
Vt_trace_two_b* bp; Vt_trace_two_b* bp;
uint64_t main_time = 0;
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
uint64_t sim_time = 1100; uint64_t sim_time = 1100;
Verilated::commandArgs(argc, argv); contextp->commandArgs(argc, argv);
Verilated::debug(0); contextp->debug(0);
Verilated::traceEverOn(true); contextp->traceEverOn(true);
srand48(5); srand48(5);
ap = new VM_PREFIX("topa"); ap = new VM_PREFIX{contextp.get(), "topa"};
bp = new Vt_trace_two_b("topb"); bp = new Vt_trace_two_b{contextp.get(), "topb"};
// clang-format off // clang-format off
#ifdef TEST_HDR_TRACE #ifdef TEST_HDR_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
# ifdef TEST_FST # ifdef TEST_FST
VerilatedFstC* tfp = new VerilatedFstC; VerilatedFstC* tfp = new VerilatedFstC;
ap->trace(tfp, 99); ap->trace(tfp, 99);
@ -59,14 +59,14 @@ int main(int argc, char** argv, char** env) {
bp->eval_step(); bp->eval_step();
ap->eval_end_step(); ap->eval_end_step();
bp->eval_end_step(); bp->eval_end_step();
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
{ {
ap->clk = false; ap->clk = false;
main_time += 10; contextp->timeInc(10);
} }
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
ap->clk = !ap->clk; ap->clk = !ap->clk;
bp->clk = ap->clk; bp->clk = ap->clk;
ap->eval_step(); ap->eval_step();
@ -74,11 +74,11 @@ int main(int argc, char** argv, char** env) {
ap->eval_end_step(); ap->eval_end_step();
bp->eval_end_step(); bp->eval_end_step();
#ifdef TEST_HDR_TRACE #ifdef TEST_HDR_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
main_time += 5; contextp->timeInc(5);
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
ap->final(); ap->final();

2
test_regress/t/t_tri_gate.cpp
View File

@ -8,8 +8,6 @@
VM_PREFIX* tb = nullptr; VM_PREFIX* tb = nullptr;
double sc_time_stamp() { return 0; }
bool check() { bool check() {
bool pass; bool pass;
int c = (tb->A >> tb->SEL) & 0x1; int c = (tb->A >> tb->SEL) & 0x1;

2
test_regress/t/t_var_pinsizes.cpp
View File

@ -7,8 +7,6 @@
VM_PREFIX* tb = nullptr; VM_PREFIX* tb = nullptr;
double sc_time_stamp() { return 0; }
int main() { int main() {
Verilated::debug(0); Verilated::debug(0);
tb = new VM_PREFIX("tb"); tb = new VM_PREFIX("tb");

17
test_regress/t/t_vpi_cb_iter.cpp
View File

@ -143,11 +143,15 @@ static void register_filler_cb() {
double sc_time_stamp() { return main_time; } double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
reregister_value_cb(); reregister_value_cb();
TEST_CHECK_NZ(vh_value_cb); TEST_CHECK_NZ(vh_value_cb);
@ -158,7 +162,7 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (main_time < sim_time && !contextp->gotFinish()) {
main_time += 1; main_time += 1;
if (verbose) VL_PRINTF("Sim Time %d got_error %d\n", main_time, errors); if (verbose) VL_PRINTF("Sim Time %d got_error %d\n", main_time, errors);
topp->clk = !topp->clk; topp->clk = !topp->clk;
@ -168,11 +172,10 @@ int main(int argc, char** argv, char** env) {
if (errors) vl_stop(__FILE__, __LINE__, "TOP-cpp"); if (errors) vl_stop(__FILE__, __LINE__, "TOP-cpp");
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
VL_DO_DANGLING(delete topp, topp);
return errors ? 10 : 0; return errors ? 10 : 0;
} }

35
test_regress/t/t_vpi_cbs_called.cpp
View File

@ -43,7 +43,6 @@ bool callbacks_expected_called[CB_COUNT] = {false};
std::vector<int>::const_iterator cb_iter; std::vector<int>::const_iterator cb_iter;
std::vector<CallbackState>::const_iterator state_iter; std::vector<CallbackState>::const_iterator state_iter;
unsigned int main_time = 0;
bool got_error = false; bool got_error = false;
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
@ -245,27 +244,29 @@ static int register_test_callback() {
return 0; return 0;
} }
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
uint64_t sim_time = 100; uint64_t sim_time = 100;
bool cbs_called; bool cbs_called;
Verilated::commandArgs(argc, argv); contextp->commandArgs(argc, argv);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
if (verbose) VL_PRINTF("-- { Sim Time %d } --\n", main_time); if (verbose) VL_PRINTF("-- { Sim Time %" PRId64 " } --\n", contextp->time());
register_test_callback(); register_test_callback();
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 1; contextp->timeInc(1);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
if (verbose) { if (verbose) {
VL_PRINTF("-- { Sim Time %d , Callback %s (%d) , Testcase State %d } --\n", main_time, VL_PRINTF("-- { Sim Time %" PRId64 " , Callback %s (%d) , Testcase State %d } --\n",
cb_reason_to_string(*cb_iter), *cb_iter, *state_iter); contextp->time(), cb_reason_to_string(*cb_iter), *cb_iter, *state_iter);
} }
topp->eval(); topp->eval();
@ -285,14 +286,17 @@ int main(int argc, char** argv, char** env) {
VerilatedVpi::callTimedCbs(); VerilatedVpi::callTimedCbs();
main_time = VerilatedVpi::cbNextDeadline(); int64_t next_time = VerilatedVpi::cbNextDeadline();
if (main_time == -1 && !Verilated::gotFinish()) { contextp->time(next_time);
if (verbose) VL_PRINTF("-- { Sim Time %d , No more testcases } --\n", main_time); if (next_time == -1 && !contextp->gotFinish()) {
if (verbose)
VL_PRINTF("-- { Sim Time %" PRId64 " , No more testcases } --\n",
contextp->time());
if (got_error) { if (got_error) {
vl_stop(__FILE__, __LINE__, "TOP-cpp"); vl_stop(__FILE__, __LINE__, "TOP-cpp");
} else { } else {
VL_PRINTF("*-* All Finished *-*\n"); VL_PRINTF("*-* All Finished *-*\n");
Verilated::gotFinish(true); contextp->gotFinish(true);
} }
} }
@ -302,11 +306,10 @@ int main(int argc, char** argv, char** env) {
topp->clk = !topp->clk; topp->clk = !topp->clk;
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

30
test_regress/t/t_vpi_get.cpp
View File

@ -40,8 +40,6 @@
#define TEST_MSG \ #define TEST_MSG \
if (0) printf if (0) printf
unsigned int main_time = 0;
//====================================================================== //======================================================================
#define CHECK_RESULT_VH(got, exp) \ #define CHECK_RESULT_VH(got, exp) \
@ -240,22 +238,25 @@ void vpi_compat_bootstrap(void) {
void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
#else #else
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
Vt_vpi_get* topp = new Vt_vpi_get(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -264,19 +265,19 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -285,7 +286,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

33
test_regress/t/t_vpi_memory.cpp
View File

@ -41,7 +41,6 @@
#define DEBUG \ #define DEBUG \
if (0) printf if (0) printf
unsigned int main_time = 0;
int errors = 0; int errors = 0;
//====================================================================== //======================================================================
@ -250,24 +249,27 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
#else #else
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
// we're going to be checking for these errors do don't crash out
Verilated::fatalOnVpiError(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
// we're going to be checking for these errors do don't crash out
contextp->fatalOnVpiError(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -276,19 +278,19 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -297,7 +299,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

44
test_regress/t/t_vpi_module.cpp
View File

@ -40,8 +40,6 @@
#define DEBUG \ #define DEBUG \
if (0) printf if (0) printf
unsigned int main_time = 0;
#define CHECK_RESULT_NZ(got) \ #define CHECK_RESULT_NZ(got) \
if (!(got)) { \ if (!(got)) { \
printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \
@ -172,27 +170,36 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
#else #else
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0); uint64_t sim_time = 1100;
// we're going to be checking for these errors do don't crash out contextp->commandArgs(argc, argv);
Verilated::fatalOnVpiError(0); contextp->debug(0);
// we're going to be checking for these errors do don't crash out
contextp->fatalOnVpiError(0);
{
// Construct and destroy
const std::unique_ptr<VM_PREFIX> topp{
new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
}
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out
// Test second construction // Test second construction
delete topp; const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
topp = new VM_PREFIX(""); // Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -201,19 +208,19 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -222,7 +229,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

34
test_regress/t/t_vpi_param.cpp
View File

@ -40,8 +40,6 @@
#define DEBUG \ #define DEBUG \
if (0) printf if (0) printf
unsigned int main_time = 0;
//====================================================================== //======================================================================
#define CHECK_RESULT_VH(got, exp) \ #define CHECK_RESULT_VH(got, exp) \
@ -240,24 +238,27 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
#else #else
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
// we're going to be checking for these errors do don't crash out
Verilated::fatalOnVpiError(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
// we're going to be checking for these errors do don't crash out
contextp->fatalOnVpiError(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -266,19 +267,19 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -287,7 +288,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

35
test_regress/t/t_vpi_time_cb.cpp
View File

@ -22,27 +22,27 @@
#include <iostream> #include <iostream>
unsigned int main_time = 0;
//====================================================================== //======================================================================
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
// clang-format off // clang-format off
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
// clang-format on // clang-format on
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -54,24 +54,24 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
VerilatedVpi::callTimedCbs(); VerilatedVpi::callTimedCbs();
if (main_time > 20) { // Else haven't registered callbacks if (contextp->time() > 20) { // Else haven't registered callbacks
TEST_CHECK_EQ(VerilatedVpi::cbNextDeadline(), main_time + 1); TEST_CHECK_EQ(VerilatedVpi::cbNextDeadline(), contextp->time() + 1);
} }
if ((main_time % 5) == 0) topp->clk = !topp->clk; if ((contextp->time() % 5) == 0) topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
VerilatedVpi::callCbs(cbEndOfSimulation); VerilatedVpi::callCbs(cbEndOfSimulation);
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -80,6 +80,5 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return errors ? 10 : 0; return errors ? 10 : 0;
} }

33
test_regress/t/t_vpi_unimpl.cpp
View File

@ -28,7 +28,6 @@
#define DEBUG \ #define DEBUG \
if (0) printf if (0) printf
unsigned int main_time = 0;
unsigned int callback_count = 0; unsigned int callback_count = 0;
//====================================================================== //======================================================================
@ -184,24 +183,27 @@ extern "C" int mon_check() {
//====================================================================== //======================================================================
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
// we're going to be checking for these errors do don't crash out
Verilated::fatalOnVpiError(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
// we're going to be checking for these errors do don't crash out
contextp->fatalOnVpiError(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -210,20 +212,20 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 10; contextp->timeInc(10);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
// VerilatedVpi::callValueCbs(); // Make sure can link without verilated_vpi.h included // VerilatedVpi::callValueCbs(); // Make sure can link without verilated_vpi.h included
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
if (!callback_count) vl_fatal(FILENM, __LINE__, "main", "%Error: never got callbacks"); if (!callback_count) vl_fatal(FILENM, __LINE__, "main", "%Error: never got callbacks");
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -232,6 +234,5 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

21
test_regress/t/t_vpi_var.cpp
View File

@ -693,20 +693,24 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
double sc_time_stamp() { return main_time; } double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
#ifdef VERILATOR #ifdef VERILATOR
#ifdef TEST_VERBOSE #ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
#endif #endif
#endif #endif
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -717,7 +721,7 @@ int main(int argc, char** argv, char** env) {
topp->clk = 0; topp->clk = 0;
main_time += 10; main_time += 10;
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) {
main_time += 1; main_time += 1;
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
@ -731,7 +735,7 @@ int main(int argc, char** argv, char** env) {
CHECK_RESULT(callback_count_half, 250); CHECK_RESULT(callback_count_half, 250);
CHECK_RESULT(callback_count_quad, 2); CHECK_RESULT(callback_count_quad, 2);
CHECK_RESULT(callback_count_strs, callback_count_strs_max); CHECK_RESULT(callback_count_strs, callback_count_strs_max);
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -740,7 +744,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }

30
test_regress/t/t_vpi_zero_time_cb.cpp
View File

@ -37,7 +37,6 @@
#include "TestVpi.h" #include "TestVpi.h"
int errors = 0; int errors = 0;
unsigned int main_time = 0;
unsigned int callback_count_zero_time = 0; unsigned int callback_count_zero_time = 0;
unsigned int callback_count_start_of_sim = 0; unsigned int callback_count_start_of_sim = 0;
@ -105,25 +104,27 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
#else #else
double sc_time_stamp() { return main_time; }
int main(int argc, char** argv, char** env) { int main(int argc, char** argv, char** env) {
uint64_t sim_time = 1100; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
Verilated::commandArgs(argc, argv);
Verilated::debug(0);
VM_PREFIX* topp = new VM_PREFIX(""); // Note null name - we're flattening it out uint64_t sim_time = 1100;
contextp->commandArgs(argc, argv);
contextp->debug(0);
const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp.get(),
// Note null name - we're flattening it out
""}};
// clang-format off // clang-format off
#ifdef VERILATOR #ifdef VERILATOR
# ifdef TEST_VERBOSE # ifdef TEST_VERBOSE
Verilated::scopesDump(); contextp->scopesDump();
# endif # endif
#endif #endif
// clang-format on // clang-format on
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); contextp->traceEverOn(true);
VL_PRINTF("Enabling waves...\n"); VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC; VerilatedVcdC* tfp = new VerilatedVcdC;
topp->trace(tfp, 99); topp->trace(tfp, 99);
@ -146,23 +147,23 @@ int main(int argc, char** argv, char** env) {
topp->eval(); topp->eval();
topp->clk = 0; topp->clk = 0;
main_time += 1; contextp->timeInc(1);
while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { while (contextp->time() < sim_time && !contextp->gotFinish()) {
main_time += 1; contextp->timeInc(1);
topp->eval(); topp->eval();
VerilatedVpi::callValueCbs(); VerilatedVpi::callValueCbs();
VerilatedVpi::callTimedCbs(); VerilatedVpi::callTimedCbs();
topp->clk = !topp->clk; topp->clk = !topp->clk;
// mon_do(); // mon_do();
#if VM_TRACE #if VM_TRACE
if (tfp) tfp->dump(main_time); if (tfp) tfp->dump(contextp->time());
#endif #endif
} }
VerilatedVpi::callCbs(cbEndOfSimulation); VerilatedVpi::callCbs(cbEndOfSimulation);
if (!Verilated::gotFinish()) { if (!contextp->gotFinish()) {
vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
} }
topp->final(); topp->final();
@ -171,7 +172,6 @@ int main(int argc, char** argv, char** env) {
if (tfp) tfp->close(); if (tfp) tfp->close();
#endif #endif
VL_DO_DANGLING(delete topp, topp);
return 0; return 0;
} }