In SAIF dumps include signals with TC 0 (#5914)
This commit is contained in:
Mateusz Gancarz
GitHub
parent
14e7b1076e
commit
e4771dac7f
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@ -400,11 +400,6 @@ bool VerilatedSaif::printActivityStats(VerilatedSaifActivityVar& activity,
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for (size_t i = 0; i < activity.width(); ++i) {
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VerilatedSaifActivityBit& bit = activity.bit(i);
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if (bit.toggleCount() <= 0) {
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// Skip bits with no toggles
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continue;
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}
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bit.aggregateVal(currentTime() - activity.lastUpdateTime(), bit.bitValue());
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if (!anyNetWritten) {
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -10,14 +10,77 @@
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)
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(INSTANCE t
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(NET
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(CLK_PERIOD\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(CLK_PERIOD\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(CLK_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(CLK_HALF_PERIOD\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(CLK_HALF_PERIOD\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(CLK_HALF_PERIOD\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(rst (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(clk (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 20))
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(a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(b (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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(c (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
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(d (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(ev (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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)
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)
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)
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File diff suppressed because it is too large
Load Diff
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@ -12,13 +12,55 @@
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)
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(INSTANCE t
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(NET
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(P\[0\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(P\[1\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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(P\[2\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(P\[3\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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(P\[4\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(P\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(P\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(P\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(clk (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 5))
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(cyc\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[1\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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(cyc\[2\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[3\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[4\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[8\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[9\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[10\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[11\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[12\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[13\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[14\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[15\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[16\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[17\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[18\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[19\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[20\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[21\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[22\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[23\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[24\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[25\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[26\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[27\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[28\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[29\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[30\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[31\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[0\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[1\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[2\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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(Q\[3\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[4\] (T0 0) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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(Q\[5\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[6\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(Q\[7\] (T0 30) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_a (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2))
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(v_b\[0\] (T0 20) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2))
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(v_b\[1\] (T0 10) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
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@ -21,6 +21,35 @@
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(cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
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(cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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(cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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@ -39,6 +68,12 @@
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(v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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@ -47,6 +82,262 @@
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(v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
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(v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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(v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
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|
||||
(v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
|
|
@ -55,15 +346,126 @@
|
|||
(v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_str32x2\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
(v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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@ -73,32 +475,209 @@
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(a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,35 @@
|
|||
(cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
|
|
@ -39,6 +68,12 @@
|
|||
(v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
|
|
@ -47,6 +82,262 @@
|
|||
(v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[0]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arr_real[1]\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[32\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[33\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[34\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[35\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(v_str32x2\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(v_str32x2\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
|
|
@ -55,15 +346,126 @@
|
|||
(v_str32x2\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_str32x2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
(v_str32x2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
(v_str32x2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
(v_str32x2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
(v_str32x2\[33\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
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|
||||
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|
||||
(v_str32x2\[36\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[37\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[38\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[39\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_str32x2\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
|
|
@ -73,32 +475,209 @@
|
|||
(v_enumb2_str\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
|
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|
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|
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|
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|
||||
)
|
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(INSTANCE a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed
|
||||
(NET
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||||
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||||
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|
||||
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|
||||
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||||
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||||
)
|
||||
)
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||||
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||||
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|
||||
(PARAM\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(PARAM\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk1
|
||||
(NET
|
||||
(b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -21,25 +21,399 @@
|
|||
(cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
(cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arrp_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_real\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
(v_real\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_real\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_real\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(v_chandle\[40\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[41\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[42\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[43\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[44\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[45\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[46\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[47\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[48\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[49\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[50\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[51\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[52\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[53\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[54\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[55\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[56\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[57\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[58\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[59\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[60\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[61\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[62\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_chandle\[63\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_enumed\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(v_enumed\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_enumed\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_enumed2\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(v_enumed2\[3\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_enumed2\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed2\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumb\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(v_enumb\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(v_enumb\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE v_strp
|
||||
(NET
|
||||
|
|
@ -109,6 +483,30 @@
|
|||
(data\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(data\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(data\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE v_str32x2[1]
|
||||
|
|
@ -116,6 +514,35 @@
|
|||
(data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(data\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(data\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(data\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(data\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE v_enumb2_str
|
||||
|
|
@ -131,12 +558,72 @@
|
|||
(INSTANCE unnamedblk1
|
||||
(NET
|
||||
(b\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(b\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(b\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(b\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(a\[0\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[2\] (T0 10) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -17,114 +17,732 @@
|
|||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub1a
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub2a
|
||||
(NET
|
||||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2b
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 13) (T1 7) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2c
|
||||
(NET
|
||||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
(INSTANCE sub1b
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub2a
|
||||
(NET
|
||||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2b
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2c
|
||||
|
|
@ -132,17 +750,99 @@
|
|||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -13,20 +13,133 @@
|
|||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub1a
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub2a
|
||||
)
|
||||
|
|
@ -37,49 +150,301 @@
|
|||
)
|
||||
(INSTANCE sub1b
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 7) (T1 13) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub2a
|
||||
(NET
|
||||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(value\[2\] (T0 8) (T1 12) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(value\[3\] (T0 5) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2b
|
||||
(NET
|
||||
(ADD\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(value\[1\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 9) (T1 11) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 1) (T1 19) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[5\] (T0 19) (T1 1) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE sub2c
|
||||
|
|
@ -87,17 +452,99 @@
|
|||
(ADD\[0\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[1\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[3\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(ADD\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(ADD\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 10))
|
||||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[0\] (T0 10) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(value\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(value\[2\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 4))
|
||||
(value\[3\] (T0 4) (T1 16) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[4\] (T0 3) (T1 17) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(value\[5\] (T0 17) (T1 3) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(value\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(value\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -13,8 +13,16 @@
|
|||
(INSTANCE t
|
||||
(NET
|
||||
(clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v_enumed\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_enumed\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_other_enumed\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v_other_enumed\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sink
|
||||
(NET
|
||||
(state\[0\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(state\[1\] (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -18,15 +18,69 @@
|
|||
(cyc\[1\] (T0 11) (T1 9) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(cyc\[2\] (T0 12) (T1 8) (TZ 0) (TX 0) (TB 0) (TC 2))
|
||||
(cyc\[3\] (T0 15) (T1 5) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE sub
|
||||
(NET
|
||||
(a\[0\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[1\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[2\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[3\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[4\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[5\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[6\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[7\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[8\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[9\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[10\] (T0 0) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(a\[11\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[12\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[13\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[14\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[15\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[16\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[17\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[18\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[19\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[20\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[21\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[22\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[23\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[24\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[25\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[26\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[27\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[28\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[29\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[30\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a\[31\] (T0 20) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -15,24 +15,324 @@
|
|||
(clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
|
||||
(cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cnt\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[0]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[0]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[29\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[1]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[1]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[60\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[61\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[1]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[1]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[92\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[1]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[1]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[28\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[2]\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[32\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[2]\[33\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[34\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[35\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[36\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[37\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[38\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[39\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[40\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[41\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[42\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[43\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[44\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[45\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[46\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[47\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[48\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[49\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[50\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[51\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[52\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[53\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[54\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[55\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[56\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[57\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[58\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[59\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[60\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[2]\[61\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[62\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[63\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[64\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[65\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[2]\[66\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[67\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[68\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[69\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[70\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[71\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[72\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[73\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[74\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[75\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[76\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[77\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[78\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[79\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[80\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[81\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[82\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[83\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[84\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[85\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[92\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(v[2]\[93\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(v[2]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -7,15 +7,93 @@
|
|||
(TIMESCALE 1ps)
|
||||
(DURATION 0)
|
||||
(INSTANCE top
|
||||
(NET
|
||||
(i_clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE my_module_types
|
||||
(NET
|
||||
(MY_PARAM\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(MY_PARAM\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(MY_PARAM\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(MY_PARAM2\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(MY_PARAM2\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(MY_PARAM2\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE t
|
||||
(NET
|
||||
(i_clk (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i_d\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(o_q\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -17,6 +17,34 @@
|
|||
(cyc\[1\] (T0 60) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[2\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[3\] (T0 80) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[4\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[5\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[6\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[7\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 120) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(a (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
|
||||
(b (T0 70) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
(z (T0 100) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
|
||||
|
|
|
|||
|
|
@ -25,24 +25,453 @@
|
|||
(cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_bit (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_logic (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE test
|
||||
(NET
|
||||
|
|
@ -78,11 +507,72 @@
|
|||
(NET
|
||||
(i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -25,24 +25,453 @@
|
|||
(cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(fst_gparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_bit (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_logic (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[32\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[33\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[34\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[35\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[36\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[37\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[38\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[39\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[40\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[41\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[42\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[43\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[44\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[45\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[46\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[47\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[48\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[49\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[50\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[51\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[52\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[53\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[54\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[55\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[56\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[57\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[58\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[59\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[60\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[61\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[62\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[63\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[1\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri0 (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_wire (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
(INSTANCE test
|
||||
(NET
|
||||
|
|
@ -78,11 +507,72 @@
|
|||
(NET
|
||||
(i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(i\[0\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1000) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -6,78 +6,568 @@
|
|||
(DIVIDER / )
|
||||
(TIMESCALE 1ps)
|
||||
(DURATION 1004)
|
||||
(INSTANCE top
|
||||
(INSTANCE top
|
||||
(INSTANCE t
|
||||
(NET
|
||||
(clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199))
|
||||
(cyc\[0\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100))
|
||||
(cyc\[1\] (T0 504) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50))
|
||||
(cyc\[2\] (T0 520) (T1 484) (TZ 0) (TX 0) (TB 0) (TC 25))
|
||||
(cyc\[3\] (T0 524) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12))
|
||||
(cyc\[4\] (T0 524) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6))
|
||||
(cyc\[5\] (T0 640) (T1 364) (TZ 0) (TX 0) (TB 0) (TC 3))
|
||||
(cyc\[6\] (T0 640) (T1 364) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(cyc\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(cyc\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(rstn (T0 110) (T1 894) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_gparam_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_gparam_real\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam_real\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
(fst_real\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(fst_real\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_real\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(fst_integer\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
(fst_integer\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(fst_integer\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
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|
||||
(fst_integer\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_integer\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_bit (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
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|
||||
(fst_int\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_int\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_shortint\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[32\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[33\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[34\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[35\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[36\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[37\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[38\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[39\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[40\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[41\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[42\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[43\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[44\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[45\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[46\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[47\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[48\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[49\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[50\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[51\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[52\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[53\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[54\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[55\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[56\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[57\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[58\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[59\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[60\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[61\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[62\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_longint\[63\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_byte\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[0\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[1\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[3\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[4\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[5\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[6\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_parameter\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_parameter\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[1\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[3\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[6\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[7\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[8\] (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_lparam\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_lparam\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_supply1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri0 (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_tri1 (T0 0) (T1 1004) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(fst_tri (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(fst_wire (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
)
|
||||
(INSTANCE test
|
||||
(NET
|
||||
(clk (T0 505) (T1 499) (TX 0) (TC 199))
|
||||
(cyc\[0\] (T0 504) (T1 500) (TX 0) (TC 100))
|
||||
(cyc\[1\] (T0 504) (T1 500) (TX 0) (TC 50))
|
||||
(cyc\[2\] (T0 520) (T1 484) (TX 0) (TC 25))
|
||||
(cyc\[3\] (T0 524) (T1 480) (TX 0) (TC 12))
|
||||
(cyc\[4\] (T0 524) (T1 480) (TX 0) (TC 6))
|
||||
(cyc\[5\] (T0 640) (T1 364) (TX 0) (TC 3))
|
||||
(cyc\[6\] (T0 640) (T1 364) (TX 0) (TC 1))
|
||||
(rstn (T0 110) (T1 894) (TX 0) (TC 1))
|
||||
(fst_parameter\[0\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_parameter\[1\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_parameter\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_parameter\[4\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_parameter\[5\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_parameter\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_lparam\[3\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_lparam\[6\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_lparam\[7\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_lparam\[8\] (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_supply1 (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(fst_tri1 (T0 0) (T1 1004) (TX 0) (TC 1))
|
||||
(state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(clk (T0 505) (T1 499) (TZ 0) (TX 0) (TB 0) (TC 199))
|
||||
(rstn (T0 110) (T1 894) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(state\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state_w\[0\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_w\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_w\[2\] (T0 434) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_w\[3\] (T0 530) (T1 474) (TZ 0) (TX 0) (TB 0) (TC 47))
|
||||
(state_w\[4\] (T0 424) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
|
||||
(state_array[0]\[0\] (T0 414) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[0]\[1\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state_array[0]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[0]\[3\] (T0 544) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44))
|
||||
(state_array[0]\[4\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state_array[1]\[0\] (T0 420) (T1 584) (TZ 0) (TX 0) (TB 0) (TC 47))
|
||||
(state_array[1]\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[1]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[1]\[3\] (T0 540) (T1 464) (TZ 0) (TX 0) (TB 0) (TC 45))
|
||||
(state_array[1]\[4\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[2]\[0\] (T0 424) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48))
|
||||
(state_array[2]\[1\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[2]\[2\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[2]\[3\] (T0 534) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46))
|
||||
(state_array[2]\[4\] (T0 530) (T1 474) (TZ 0) (TX 0) (TB 0) (TC 47))
|
||||
)
|
||||
(INSTANCE test
|
||||
(NET
|
||||
(clk (T0 505) (T1 499) (TX 0) (TC 199))
|
||||
(rstn (T0 110) (T1 894) (TX 0) (TC 1))
|
||||
(state\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
|
||||
(state\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
|
||||
(state\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state_w\[0\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_w\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_w\[2\] (T0 434) (T1 570) (TX 0) (TC 46))
|
||||
(state_w\[3\] (T0 530) (T1 474) (TX 0) (TC 47))
|
||||
(state_w\[4\] (T0 424) (T1 580) (TX 0) (TC 48))
|
||||
(state_array[0]\[0\] (T0 414) (T1 590) (TX 0) (TC 46))
|
||||
(state_array[0]\[1\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state_array[0]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[0]\[3\] (T0 544) (T1 460) (TX 0) (TC 44))
|
||||
(state_array[0]\[4\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state_array[1]\[0\] (T0 420) (T1 584) (TX 0) (TC 47))
|
||||
(state_array[1]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[1]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[1]\[3\] (T0 540) (T1 464) (TX 0) (TC 45))
|
||||
(state_array[1]\[4\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[2]\[0\] (T0 424) (T1 580) (TX 0) (TC 48))
|
||||
(state_array[2]\[1\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[2]\[2\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[2]\[3\] (T0 534) (T1 470) (TX 0) (TC 46))
|
||||
(state_array[2]\[4\] (T0 530) (T1 474) (TX 0) (TC 47))
|
||||
)
|
||||
(INSTANCE unnamedblk1
|
||||
(NET
|
||||
(i\[0\] (T0 10) (T1 994) (TX 0) (TC 1))
|
||||
(i\[1\] (T0 10) (T1 994) (TX 0) (TC 1))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(i\[1\] (T0 120) (T1 884) (TX 0) (TC 1))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk1
|
||||
(NET
|
||||
(i\[0\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[1\] (T0 10) (T1 994) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
(INSTANCE unnamedblk2
|
||||
(NET
|
||||
(i\[0\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[1\] (T0 120) (T1 884) (TZ 0) (TX 0) (TB 0) (TC 1))
|
||||
(i\[2\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[3\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[4\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[5\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[6\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[7\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[8\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[9\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[10\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[11\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[12\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[13\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[14\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[15\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[16\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[17\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[18\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[19\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[20\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[21\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[22\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[23\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[24\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[25\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[26\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[27\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[28\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[29\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[30\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
(i\[31\] (T0 1004) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
Loading…
Reference in New Issue