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Add lib.map information to unsupported message, etc

This commit is contained in:
Wilson Snyder 2025-05-03 05:30:40 -04:00
parent e837f780a2
commit ea65bcd86b
12 changed files with 157 additions and 38 deletions
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2
docs/guide/languages.rst
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@ -536,4 +536,4 @@ $test$plusargs, $value$plusargs
{VerilatedContext*} ->commandArgs(argc, argv);
to register the command line before calling $test$plusargs or
$value$plusargs.
$value$plusargs. Or use :vlopt:`--binary` or :vlopt:`--main`.

23
src/verilog.l
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@ -441,18 +441,19 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Verilog 2001 Config */
<V01C,V05,VA5,S05,S09,S12,S17,S23,SAX>{
/* Generic unsupported keywords */
"cell" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"config" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"design" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"endconfig" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"incdir" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"include" { FL; yylval.fl->v3warn(E_UNSUPPORTED, "Unsupported: Verilog 2001-config reserved word not implemented;"
" suggest you want `include instead: '" << yytext << "'");
"cell" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"config" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"design" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"endconfig" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"incdir" { FL; ERROR_RSVD_WORD("Verilog 2001-config lib.map"); }
"include" { FL; yylval.fl->v3warn(E_UNSUPPORTED, "Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'\n"
<< yylval.fl->warnMore() << "... Suggest unless in a lib.map file,"
" want `include instead");
FL_BRK; }
"instance" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"liblist" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"library" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"use" { ERROR_RSVD_WORD("Verilog 2001-config"); }
"instance" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"liblist" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
"library" { FL; ERROR_RSVD_WORD("Verilog 2001-config lib.map"); }
"use" { FL; ERROR_RSVD_WORD("Verilog 2001-config"); }
}
/* Verilog 2005 */

32
src/verilog.y
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@ -7733,6 +7733,38 @@ colon<fl>: // Generic colon that isn't making a label (e.g.
| yP_COLON__FORK { $$ = $1; }
;
//**********************************************************************
// Config - config...endconfig
//**********************************************************************
// Config - lib.map
//UNSUP library_text: // == IEEE: library_text (note is top-level entry point)
//UNSUP library_description { }
//UNSUP | library_text library_description { }
//UNSUP ;
//UNSUP library_description: // == IEEE: library_description
//UNSUP // // IEEE: library_declaration
//UNSUP yLIBRARY idAny/*library_identifier*/ file_path_specList ';'
//UNSUP { BBUNSUP($<fl>1, "Unsupported: config lib.map library"); }
//UNSUP yLIBRARY idAny/*library_identifier*/ file_path_specList '-' yINCDIR file_path_specList ';'
//UNSUP { BBUNSUP($<fl>1, "Unsupported: config lib.map library"); }
//UNSUP // // IEEE: include_statement
//UNSUP | yINCLUDE file_path_spec ';' { BBUNSUP($<fl>1, "Unsupported: config include"); }
//UNSUP | config_declaration { }
//UNSUP | ';' { }
//UNSUP ;
//UNSUP file_path_specList: // IEEE: file_path_spec { ',' file_path_spec }
//UNSUP file_path_spec { }
//UNSUP | file_path_specList ',' file_path_spec { }
//UNSUP ;
//UNSUP file_path_spec: // IEEE: file_path_spec
//UNSUP Needs to be lexer rule, Note '/' '*' must not be a comment.
//UNSUP ;
//**********************************************************************
// VLT Files

3
test_regress/t/t_config_include_bad.out
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@ -1,4 +1,5 @@
%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include'
%Error-UNSUPPORTED: t/t_config_include_bad.v:7:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
7 | include "meant_to_tick_include.v"
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest

4
test_regress/t/t_config_include_bad.py
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@ -11,8 +11,6 @@ import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=["--lint-only -Wwarn-REALCVT"],
fails=True,
expect_filename=test.golden_filename)
test.lint(verilator_flags2=["--lint-only"], fails=True, expect_filename=test.golden_filename)
test.passes()

17
test_regress/t/t_config_libmap.map Normal file
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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// lib.map file:
include ./t_config_libmap_inc.map
library rtllib *.v;
library rtllib2 *.v, *.sv;
library rtllib3 *.v -incdir *.vh;
library rtllib4 *.v -incdir *.vh, *.svh;
config cfg;
design t;
endconfig

29
test_regress/t/t_config_libmap.out Normal file
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@ -0,0 +1,29 @@
%Error-UNSUPPORTED: t/t_config_libmap.map:8:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
8 | include ./t_config_libmap_inc.map
| ^~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_config_libmap.map:8:9: syntax error, unexpected '.'
8 | include ./t_config_libmap_inc.map
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_config_libmap.map:10:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
10 | library rtllib *.v;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
11 | library rtllib2 *.v, *.sv;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
12 | library rtllib3 *.v -incdir *.vh;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:12:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
%Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
13 | library rtllib4 *.v -incdir *.vh, *.svh;
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:13:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir'
13 | library rtllib4 *.v -incdir *.vh, *.svh;
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_config_libmap.map:15:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config'
%Error-UNSUPPORTED: t/t_config_libmap.map:16:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design'
%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
%Error: Exiting due to

18
test_regress/t/t_config_libmap.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(verilator_flags2=["--lint-only", "t/" + test.name + ".map"],
fails=test.vlt_all,
expect_filename=test.golden_filename)
test.passes()

12
test_regress/t/t_config_libmap.v Normal file
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@ -0,0 +1,12 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

17
test_regress/t/t_config_libmap_inc.map Normal file
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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// lib.map file:
include ./t_config_libmap_inc.map
library rtllib *.v;
library rtllib2 *.v, *.sv;
library rtllib3 *.v -incdir *.vh;
library rtllib4 *.v -incdir *.vh, *.svh;
config cfg;
design t;
endconfig

2
test_regress/t/t_dist_copyright.py
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@ -12,7 +12,7 @@ import datetime
test.scenarios('dist')
RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)'
RELEASE_OK_RE = r'(^test_regress/t/.*\.(cpp|h|map|mk|sv|v|vlt)|^test_regress/t_done/|^examples/)'
EXEMPT_AUTHOR_RE = r'(^ci/|^nodist/fastcov.py|^nodist/fuzzer|^test_regress/t/.*\.(cpp|h|v|vlt)$)'

36
test_regress/t/t_lint_rsvd_bad.out
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@ -1,42 +1,36 @@
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config'
7 | config cfgBad;
| ^~~~~~
| ^~~~~~~~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER
7 | config cfgBad;
| ^~~~~~
%Error: t/t_lint_rsvd_bad.v:7:14: syntax error, unexpected IDENTIFIER
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design'
8 | design rtlLib.top;
| ^~~~~~
| ^~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:9:12: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist'
9 | default liblist rtlLib;
| ^~~~~~~
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:4: Unsupported: Verilog 2001-config reserved word not implemented: 'instance'
10 | instance top.a2 liblist gateLib;
| ^~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:20: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist'
10 | instance top.a2 liblist gateLib;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:11:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include'
| ^~~~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:28: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist'
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:11:4: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
11 | include none;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:12:4: Unsupported: Verilog 2001-config reserved word not implemented: 'library'
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:12:4: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library'
12 | library rtlLib *.v;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:13:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include'
| ^~~~~~~~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:13:4: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include'
: ... Suggest unless in a lib.map file, want `include instead
13 | include aa;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:14:4: Unsupported: Verilog 2001-config reserved word not implemented: 'use'
14 | use gateLib;
| ^~~
| ^~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:4: Unsupported: Verilog 2001-config reserved word not implemented: 'cell'
15 | cell rtlLib.cell;
| ^~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:16: Unsupported: Verilog 2001-config reserved word not implemented: 'cell'
15 | cell rtlLib.cell;
| ^~~~
| ^~~~~~~~
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:20: Unsupported: Verilog 2001-config reserved word not implemented: 'cell'
%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:16:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
16 | endconfig
| ^~~~~~~~~
%Error: Exiting due to