Tests: Cover --error-limit and update docs (found via coverage).

bin/verilator

@@ -768,8 +768,8 @@ will also go to standard out.
 
 =item --error-limit I<value>
 
-After this number of errors or warnings are encountered, exit.  Defaults to
-50.
+After this number of errors are encountered, exit.  Warnings are not
+counted in this limit.  Defaults to 50.
 
 =item --exe
 

test_regress/t/t_flag_errorlimit_bad.out

@@ -0,0 +1,5 @@
+%Error: t/t_flag_errorlimit_bad.v:9: Duplicate declaration of signal: u1
+        t/t_flag_errorlimit_bad.v:8: ... Location of original declaration
+%Error: t/t_flag_errorlimit_bad.v:10: Duplicate declaration of signal: u1
+        t/t_flag_errorlimit_bad.v:8: ... Location of original declaration
+%Error: Exiting due to

test_regress/t/t_flag_errorlimit_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["-Wall -Wno-DECLFILENAME --error-limit 2"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_flag_errorlimit_bad.v

@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   int u1;
+   int u1;
+   int u1;
+   int u1;
+   int u1;
+   int u1;
+   int u1;
+
+endmodule