Introduction of a test

Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>

test_regress/t/t_class_param_subtype2.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_class_param_subtype2.v

@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Class1 #(type T);
+   static function int get();
+      return T::Helper::getter();
+   endfunction
+endclass
+
+class Class2;
+   typedef Class2 Helper;
+   static function int getter();
+      return 13;
+   endfunction
+endclass
+
+module t;
+   initial begin
+      if (Class1#(Class2)::get() != 13) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule