From f77af4e6f65e28bf218e47cbaf07e5398b69aea2 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 3 Jul 2025 19:36:28 -0400 Subject: [PATCH] Important: Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. --- Changes | 4 ++++ bin/verilator | 4 ++-- docs/guide/exe_verilator.rst | 14 ++++++++++---- docs/guide/faq.rst | 2 +- docs/guide/languages.rst | 14 +++++++------- docs/guide/simulating.rst | 11 +++++------ docs/guide/warnings.rst | 4 ++-- src/V3Assert.cpp | 2 +- src/V3Options.cpp | 5 ++++- src/V3Options.h | 6 +++--- test_regress/t/t_assert_disabled.py | 2 +- test_regress/t/t_assert_procedural_clk_bad.py | 2 +- test_regress/t/t_assert_synth_off.py | 3 ++- test_regress/t/t_debug_emitv.out | 2 +- 14 files changed, 44 insertions(+), 31 deletions(-) diff --git a/Changes b/Changes index 9064d011d..b594569e1 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,10 @@ contributors that suggested or implemented a given issue are shown in []. Thanks Verilator 5.037 devel ========================== +**Important:** + +* Change `--assert` to be the default; use `--no-assert` for legacy behavior and faster runtimes. + **Other:** * Support redeclaring type as non-type; major parsing change (#2412) (#6020) (#6042) (#6044). diff --git a/bin/verilator b/bin/verilator index 2709e6cd0..f27e64c84 100755 --- a/bin/verilator +++ b/bin/verilator @@ -311,8 +311,8 @@ detailed descriptions of these arguments. +1800-2012ext+ Use SystemVerilog 2012 with file extension +1800-2017ext+ Use SystemVerilog 2017 with file extension +1800-2023ext+ Use SystemVerilog 2023 with file extension - --assert Enable all assertions - --assert-case Enable unique/unique0/priority case related checks + --no-assert Disable all assertions + --no-assert-case Disable unique/unique0/priority-case assertions --autoflush Flush streams after all $displays --bbox-sys Blackbox unknown $system calls --bbox-unsup Blackbox unsupported language features diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 1ec9a8f3b..a98de32eb 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -86,13 +86,19 @@ Summary: grammar and other semantic extensions which might not be legal when set to an older standard. -.. option:: --assert +.. option:: --no-assert - Enable all assertions. Implies :vlopt:`--assert-case`. + Disable all assertions. Implies :vlopt:`--no-assert-case`. -.. option:: --assert-case + In versions before 5.038, these were disabled by default, and `--assert` + was required to enable assertions. - Enable unique/unique0/priority case related checks. +.. option:: --no-assert-case + + Disable unique/unique0/priority case related checks. + + In versions before 5.038, these were disabled by default, and `--assert` + or `--assert-case` was required to enable case assertions. .. option:: --autoflush diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 3b634adc6..d1bf9f530 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -335,7 +335,7 @@ How do I prevent my assertions from firing during reset? Call :code:`Verilated::assertOn(false)` before you first call the model, then turn it back on after reset. It defaults to true. When false, all -assertions controlled by :vlopt:`--assert` are disabled. +assertions are disabled. Why do I get "undefined reference to sc_time_stamp()? diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index 24f2e0fbd..4a4d8762b 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -90,14 +90,14 @@ wreal. Synthesis Directive Assertion Support ------------------------------------- -With the :vlopt:`--assert` option, Verilator reads any +Verilator reads any :code:`//synopsys full_case` or :code:`//synopsys +parallel_case` directives. The same applies to any :code:`//ambit +synthesis`, :code:`//cadence` or :code:`//pragma` directives of the same +form. -:code:`//synopsys full_case` or :code:`//synopsys parallel_case` -directives. The same applies to any :code:`//ambit synthesis`, -:code:`//cadence` or :code:`//pragma` directives of the same form. - -When these synthesis directives are discovered, Verilator will either -formally prove the directive to be true, or, failing that, will insert the +When these synthesis directives are discovered, unless +:vlopt:`--no-assert-case` option is used, Verilator will either formally +prove the directive to be true, or, failing that, will insert the appropriate code to detect failing cases at simulation runtime and print an "Assertion failed" error message. diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index c18126a8a..5758af4d3 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -76,12 +76,14 @@ Benchmarking & Optimization For best performance, run Verilator with the :vlopt:`-O3` :vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast <--x-initial>` -:vlopt:`--noassert <--assert>` options. The :vlopt:`-O3` +:vlopt:`--no-assert` options. The :vlopt:`-O3` option will require a longer time to run Verilator, and :vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast <--x-assign>` -may increase the risk of reset bugs in trade for performance; see the above -documentation for these options. +may increase the risk of reset bugs in trade for performance. The +:vlopt:`--no-assert` will suppress checking assertions, which is faster and +appropriate for known-good models running software, but may hide design +errors. See the above documentation for these options. If using Verilated multithreaded, consider overriding Verilator's default thread-to-processor assignment by using ``numactl``; see @@ -203,9 +205,6 @@ With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will translate functional coverage points the user has inserted manually in SystemVerilog code through into the Verilated model. -Currently, all functional coverage points are specified using SystemVerilog -assertion syntax, which must be separately enabled with :vlopt:`--assert`. - For example, the following SystemVerilog statement will add a coverage point under the coverage name "DefaultClock": diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 11257859d..d377d6236 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -333,8 +333,8 @@ List Of Warnings Unique case statements that select on an enumerated variable, where all of the enumerated values are covered by case items, are considered complete even if the case statement does not cover illegal - non-enumerated values (IEEE 1800-2023 12.5.3). To check that illegal - values are not hit, use :vlopt:`--assert`. + non-enumerated values (IEEE 1800-2023 12.5.3). Verilator checks that + illegal values are not hit, unless :vlopt:`--no-assert-case` was used. Ignoring this warning will only suppress the lint check; it will simulate correctly. diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 83ccfcc5c..bd1423034 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -57,7 +57,7 @@ class AssertVisitor final : public VNVisitor { switch (directiveType) { case VAssertDirectiveType::INTRINSIC: return new AstConst{fl, AstConst::BitTrue{}}; case VAssertDirectiveType::VIOLATION_CASE: { - if (v3Global.opt.assertCaseOn()) { + if (v3Global.opt.assertCase()) { return new AstCExpr{fl, "vlSymsp->_vm_contextp__->assertOn()", 1}; } // If assertions are off, have constant propagation rip them out later diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 6c4f4fbe3..4c99cdbba 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1180,7 +1180,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2023); }); // Minus options - DECL_OPTION("-assert", OnOff, &m_assert); + DECL_OPTION("-assert", CbOnOff, [this](bool flag) { + m_assert = flag; + m_assertCase = flag; + }); DECL_OPTION("-assert-case", OnOff, &m_assertCase); DECL_OPTION("-autoflush", OnOff, &m_autoflush); diff --git a/src/V3Options.h b/src/V3Options.h index e70fbe4ad..2d062fcb9 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -251,8 +251,8 @@ private: bool m_preprocResolve = false; // main switch: --preproc-resolve bool m_makePhony = false; // main switch: -MP bool m_preprocNoLine = false; // main switch: -P - bool m_assert = false; // main switch: --assert - bool m_assertCase = false; // main switch: --assert-case + bool m_assert = true; // main switch: --assert + bool m_assertCase = true; // main switch: --assert-case bool m_autoflush = false; // main switch: --autoflush bool m_bboxSys = false; // main switch: --bbox-sys bool m_bboxUnsup = false; // main switch: --bbox-unsup @@ -520,7 +520,7 @@ public: bool stdWaiver() const { return m_stdWaiver; } bool structsPacked() const { return m_structsPacked; } bool assertOn() const { return m_assert; } // assertOn as __FILE__ may be defined - bool assertCaseOn() const { return m_assertCase || m_assert; } + bool assertCase() const { return m_assertCase; } bool autoflush() const { return m_autoflush; } bool bboxSys() const { return m_bboxSys; } bool bboxUnsup() const { return m_bboxUnsup; } diff --git a/test_regress/t/t_assert_disabled.py b/test_regress/t/t_assert_disabled.py index b45b81326..e6adf4fde 100755 --- a/test_regress/t/t_assert_disabled.py +++ b/test_regress/t/t_assert_disabled.py @@ -12,7 +12,7 @@ import vltest_bootstrap test.scenarios('simulator') test.top_filename = "t/t_assert_on.v" -test.compile() +test.compile(verilator_flags2=['--no-assert']) test.execute() diff --git a/test_regress/t/t_assert_procedural_clk_bad.py b/test_regress/t/t_assert_procedural_clk_bad.py index 7e5bcdfe5..af14b700f 100755 --- a/test_regress/t/t_assert_procedural_clk_bad.py +++ b/test_regress/t/t_assert_procedural_clk_bad.py @@ -11,6 +11,6 @@ import vltest_bootstrap test.scenarios('vlt') -test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) +test.lint(expect_filename=test.golden_filename, fails=True) test.passes() diff --git a/test_regress/t/t_assert_synth_off.py b/test_regress/t/t_assert_synth_off.py index ce86721c2..13a912951 100755 --- a/test_regress/t/t_assert_synth_off.py +++ b/test_regress/t/t_assert_synth_off.py @@ -13,7 +13,8 @@ test.scenarios('simulator') test.top_filename = "t/t_assert_synth.v" test.compile(v_flags2=[ - '+define+FAILING_FULL', '+define+FAILING_PARALLEL', '+define+FAILING_OH', '+define+FAILING_OC' + '--no-assert-case', '+define+FAILING_FULL', '+define+FAILING_PARALLEL', '+define+FAILING_OH', + '+define+FAILING_OC' ]) test.execute() diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index 322c8fcfb..4976ecd1e 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -223,7 +223,7 @@ module Vt_debug_emitv_t; $stop; end case (in) - 'sh1: begin $display("1"); + // synopsys full_case parallel_case'sh1: begin $display("1"); end default: begin $display("default"); end