Merge ea62a51589 into 9f04ee68c8
This commit is contained in:
G-A. Kamendje
GitHub
commit
f971bca8a1
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// // verilator_coverage annotation
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// DESCRIPTION: Verilator: SystemVerilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2008 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
module t_cover_else_points ;
|
||||
%000002 logic is_su_mode;
|
||||
-000002 point: comment=is_su_mode
|
||||
%000002 logic is_em_emul;
|
||||
-000002 point: comment=is_em_emul
|
||||
%000001 logic is_ata_emul;
|
||||
-000001 point: comment=is_ata_emul
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
%000000 logic [3:0] user_word_cnt;
|
||||
-000002 point: comment=user_word_cnt[0]
|
||||
-000002 point: comment=user_word_cnt[1]
|
||||
-000001 point: comment=user_word_cnt[2]
|
||||
-000000 point: comment=user_word_cnt[3]
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
%000002 logic page;
|
||||
-000002 point: comment=page
|
||||
%000001 logic [6:0] cfg;
|
||||
-000002 point: comment=cfg[0]
|
||||
-000002 point: comment=cfg[1]
|
||||
-000002 point: comment=cfg[2]
|
||||
-000000 point: comment=cfg[3]
|
||||
-000003 point: comment=cfg[4]
|
||||
-000002 point: comment=cfg[5]
|
||||
-000001 point: comment=cfg[6]
|
||||
%000001 initial begin
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h05;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h06;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h10;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h60;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h60;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h40;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 is_su_mode =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_em_emul =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 is_ata_emul =1'b1;
|
||||
-000001 point: comment=block
|
||||
%000001 page =1'b0;
|
||||
-000001 point: comment=block
|
||||
%000001 cfg =7'h50;
|
||||
-000001 point: comment=block
|
||||
%000001 #100;
|
||||
-000001 point: comment=block
|
||||
%000001 $write("*-* All Finished *-*\n");
|
||||
-000001 point: comment=block
|
||||
%000001 $finish;
|
||||
-000001 point: comment=block
|
||||
end
|
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a a_inst(
|
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.i_is_su_mode ( is_su_mode ),
|
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.i_page ( page ),
|
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.i_cfg ( cfg ),
|
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.i_is_em_emul ( is_em_emul ),
|
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.i_is_ata_emul ( is_ata_emul ),
|
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.o_user_word_count( user_word_cnt)
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);
|
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endmodule
|
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/* verilator lint_off DECLFILENAME */
|
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module a (
|
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/* verilator lint_on DECLFILENAME */
|
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%000002 input logic i_is_su_mode ,
|
||||
-000002 point: comment=i_is_su_mode
|
||||
%000002 input logic i_page ,
|
||||
-000002 point: comment=i_page
|
||||
%000001 input logic [6:0] i_cfg ,
|
||||
-000002 point: comment=i_cfg[0]
|
||||
-000002 point: comment=i_cfg[1]
|
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-000002 point: comment=i_cfg[2]
|
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-000000 point: comment=i_cfg[3]
|
||||
-000003 point: comment=i_cfg[4]
|
||||
-000002 point: comment=i_cfg[5]
|
||||
-000001 point: comment=i_cfg[6]
|
||||
%000002 input logic i_is_em_emul ,
|
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-000002 point: comment=i_is_em_emul
|
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%000001 input logic i_is_ata_emul,
|
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-000001 point: comment=i_is_ata_emul
|
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%000000 output logic [3:0] o_user_word_count
|
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-000002 point: comment=o_user_word_count[0]
|
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-000002 point: comment=o_user_word_count[1]
|
||||
-000001 point: comment=o_user_word_count[2]
|
||||
-000000 point: comment=o_user_word_count[3]
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||||
);
|
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%000001 always_comb begin
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-000001 point: comment=block
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%000001 o_user_word_count='0;
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-000001 point: comment=block
|
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%000001 if (i_is_su_mode == 1'b1) begin
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-000001 point: comment=elsif
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%000001 o_user_word_count = 4'b0000;
|
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-000001 point: comment=elsif
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end
|
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%000002 else if (i_is_em_emul == 1'b1 ) begin
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-000002 point: comment=elsif
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%000002 case(i_cfg[3:0])
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-000002 point: comment=elsif
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||||
%000000 4'b0101: begin
|
||||
-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0000;
|
||||
-000000 point: comment=case
|
||||
end
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%000002 4'b0110: begin
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-000002 point: comment=case
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||||
%000002 o_user_word_count = 4'b0001;
|
||||
-000002 point: comment=case
|
||||
end
|
||||
%000000 4'b0111: begin
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||||
-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0010;
|
||||
-000000 point: comment=case
|
||||
end
|
||||
%000000 4'b1000: begin
|
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-000000 point: comment=case
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%000000 o_user_word_count = 4'b0011;
|
||||
-000000 point: comment=case
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end
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%000000 4'b1001: begin
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-000000 point: comment=case
|
||||
%000000 o_user_word_count = 4'b0100;
|
||||
-000000 point: comment=case
|
||||
end
|
||||
%000000 4'b1010: begin
|
||||
-000000 point: comment=case
|
||||
%000000 o_user_word_count = 4'b0101;
|
||||
-000000 point: comment=case
|
||||
end
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||||
%000000 4'b1011: begin
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-000000 point: comment=case
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%000000 o_user_word_count = 4'b0110;
|
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-000000 point: comment=case
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||||
end
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%000000 4'b1100: begin
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-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0111;
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-000000 point: comment=case
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||||
end
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%000000 4'b1101: begin
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-000000 point: comment=case
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%000000 o_user_word_count = 4'b1000;
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-000000 point: comment=case
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||||
end
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||||
%000000 default: begin
|
||||
-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0011;
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-000000 point: comment=case
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end
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endcase
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end
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%000000 else if (i_is_ata_emul == 1'b1) begin
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+000012 point: comment=if
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-000000 point: comment=else
|
||||
000012 case(i_cfg[6:4])
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+000012 point: comment=if
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||||
%000000 3'b000: begin
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||||
-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0000;
|
||||
-000000 point: comment=case
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||||
end
|
||||
%000002 3'b001: begin
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||||
-000002 point: comment=case
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||||
%000002 o_user_word_count = 4'b0000;
|
||||
-000002 point: comment=case
|
||||
end
|
||||
%000000 3'b010: begin
|
||||
-000000 point: comment=case
|
||||
%000000 o_user_word_count = 4'b0001;
|
||||
-000000 point: comment=case
|
||||
end
|
||||
%000000 3'b011: begin
|
||||
-000000 point: comment=case
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||||
%000000 o_user_word_count = 4'b0010;
|
||||
-000000 point: comment=case
|
||||
end
|
||||
%000002 3'b100: begin
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||||
-000002 point: comment=case
|
||||
%000000 if (i_page == 1'b1) begin
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||||
-000002 point: comment=if
|
||||
-000000 point: comment=else
|
||||
%000002 o_user_word_count = 4'b0010;
|
||||
-000002 point: comment=if
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||||
%000000 end else begin
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||||
-000000 point: comment=else
|
||||
%000000 o_user_word_count = 4'b0011;
|
||||
-000000 point: comment=else
|
||||
end
|
||||
end
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||||
%000004 3'b101: begin
|
||||
-000004 point: comment=case
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||||
%000004 if (i_page == 1'b1) begin
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-000000 point: comment=if
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||||
-000004 point: comment=else
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||||
%000000 o_user_word_count = 4'b0010;
|
||||
-000000 point: comment=if
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||||
%000004 end else begin
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||||
-000004 point: comment=else
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||||
%000004 o_user_word_count = 4'b0100;
|
||||
-000004 point: comment=else
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||||
end
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||||
end
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||||
%000004 3'b110: begin
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||||
-000004 point: comment=case
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||||
%000000 if (i_page == 1'b1) begin
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||||
-000004 point: comment=if
|
||||
-000000 point: comment=else
|
||||
%000004 o_user_word_count = 4'b0010;
|
||||
-000004 point: comment=if
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||||
%000000 end else begin
|
||||
-000000 point: comment=else
|
||||
%000000 o_user_word_count = 4'b0101;
|
||||
-000000 point: comment=else
|
||||
end
|
||||
end
|
||||
%000000 3'b111: begin
|
||||
-000000 point: comment=case
|
||||
%000000 if (i_page == 1'b1) begin
|
||||
-000000 point: comment=if
|
||||
-000000 point: comment=else
|
||||
%000000 o_user_word_count = 4'b0010;
|
||||
-000000 point: comment=if
|
||||
%000000 end else begin
|
||||
-000000 point: comment=else
|
||||
%000000 o_user_word_count = 4'b0110;
|
||||
-000000 point: comment=else
|
||||
end
|
||||
end
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||||
%000000 default: begin
|
||||
-000000 point: comment=case
|
||||
%000000 o_user_word_count = 4'b0010;
|
||||
-000000 point: comment=case
|
||||
end
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||||
endcase
|
||||
end
|
||||
%000000 else begin // default
|
||||
-000000 point: comment=else
|
||||
%000000 o_user_word_count = 4'b0000;
|
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-000000 point: comment=else
|
||||
end
|
||||
end
|
||||
endmodule
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||||
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@ -0,0 +1,36 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
compile(
|
||||
verilator_flags2 => [ "--binary --coverage --timing -Wall" ],
|
||||
);
|
||||
|
||||
execute(
|
||||
all_run_flags => [" +verilator+coverage+file+$Self->{obj_dir}/coverage.dat"],
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
# Read the input .v file and do any CHECK_COVER requests
|
||||
inline_checks();
|
||||
|
||||
run(cmd => ["../bin/verilator_coverage",
|
||||
"--annotate-points",
|
||||
"--annotate", "$Self->{obj_dir}/annotated",
|
||||
"$Self->{obj_dir}/coverage.dat",
|
||||
],
|
||||
verilator_run => 1,
|
||||
) if !$Self->errors && !$Self->skips;
|
||||
|
||||
files_identical("$Self->{obj_dir}/annotated/t_cover_else_points.v", $Self->{golden_filename});
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
// DESCRIPTION: Verilator: SystemVerilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2008 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
module t_cover_else_points ;
|
||||
logic is_su_mode;
|
||||
logic is_em_emul;
|
||||
logic is_ata_emul;
|
||||
/* verilator lint_off UNUSEDSIGNAL */
|
||||
logic [3:0] user_word_cnt;
|
||||
/* verilator lint_on UNUSEDSIGNAL */
|
||||
logic page;
|
||||
logic [6:0] cfg;
|
||||
initial begin
|
||||
is_su_mode =1'b1;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b0;
|
||||
page =1'b0;
|
||||
cfg =7'h05;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b1;
|
||||
is_ata_emul =1'b0;
|
||||
page =1'b0;
|
||||
cfg =7'h06;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b1;
|
||||
page =1'b0;
|
||||
cfg =7'h10;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b1;
|
||||
page =1'b1;
|
||||
cfg =7'h60;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b1;
|
||||
page =1'b1;
|
||||
cfg =7'h60;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b1;
|
||||
page =1'b1;
|
||||
cfg =7'h40;
|
||||
#100;
|
||||
is_su_mode =1'b0;
|
||||
is_em_emul =1'b0;
|
||||
is_ata_emul =1'b1;
|
||||
page =1'b0;
|
||||
cfg =7'h50;
|
||||
#100;
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
a a_inst(
|
||||
.i_is_su_mode ( is_su_mode ),
|
||||
.i_page ( page ),
|
||||
.i_cfg ( cfg ),
|
||||
.i_is_em_emul ( is_em_emul ),
|
||||
.i_is_ata_emul ( is_ata_emul ),
|
||||
.o_user_word_count( user_word_cnt)
|
||||
);
|
||||
endmodule
|
||||
/* verilator lint_off DECLFILENAME */
|
||||
module a (
|
||||
/* verilator lint_on DECLFILENAME */
|
||||
input logic i_is_su_mode ,
|
||||
input logic i_page ,
|
||||
input logic [6:0] i_cfg ,
|
||||
input logic i_is_em_emul ,
|
||||
input logic i_is_ata_emul,
|
||||
output logic [3:0] o_user_word_count
|
||||
);
|
||||
always_comb begin
|
||||
o_user_word_count='0;
|
||||
if (i_is_su_mode == 1'b1) begin
|
||||
o_user_word_count = 4'b0000;
|
||||
end
|
||||
else if (i_is_em_emul == 1'b1 ) begin
|
||||
case(i_cfg[3:0])
|
||||
4'b0101: begin
|
||||
o_user_word_count = 4'b0000;
|
||||
end
|
||||
4'b0110: begin
|
||||
o_user_word_count = 4'b0001;
|
||||
end
|
||||
4'b0111: begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end
|
||||
4'b1000: begin
|
||||
o_user_word_count = 4'b0011;
|
||||
end
|
||||
4'b1001: begin
|
||||
o_user_word_count = 4'b0100;
|
||||
end
|
||||
4'b1010: begin
|
||||
o_user_word_count = 4'b0101;
|
||||
end
|
||||
4'b1011: begin
|
||||
o_user_word_count = 4'b0110;
|
||||
end
|
||||
4'b1100: begin
|
||||
o_user_word_count = 4'b0111;
|
||||
end
|
||||
4'b1101: begin
|
||||
o_user_word_count = 4'b1000;
|
||||
end
|
||||
default: begin
|
||||
o_user_word_count = 4'b0011;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if (i_is_ata_emul == 1'b1) begin
|
||||
case(i_cfg[6:4])
|
||||
3'b000: begin
|
||||
o_user_word_count = 4'b0000;
|
||||
end
|
||||
3'b001: begin
|
||||
o_user_word_count = 4'b0000;
|
||||
end
|
||||
3'b010: begin
|
||||
o_user_word_count = 4'b0001;
|
||||
end
|
||||
3'b011: begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end
|
||||
3'b100: begin
|
||||
if (i_page == 1'b1) begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end else begin
|
||||
o_user_word_count = 4'b0011;
|
||||
end
|
||||
end
|
||||
3'b101: begin
|
||||
if (i_page == 1'b1) begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end else begin
|
||||
o_user_word_count = 4'b0100;
|
||||
end
|
||||
end
|
||||
3'b110: begin
|
||||
if (i_page == 1'b1) begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end else begin
|
||||
o_user_word_count = 4'b0101;
|
||||
end
|
||||
end
|
||||
3'b111: begin
|
||||
if (i_page == 1'b1) begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end else begin
|
||||
o_user_word_count = 4'b0110;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
o_user_word_count = 4'b0010;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin // default
|
||||
o_user_word_count = 4'b0000;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
Loading…
Reference in New Issue