Fix ignoring joins in stringify in preprocessor (#5777)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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Krzysztof Bieganski 2025-02-14 00:33:12 +01:00 committed by GitHub
parent f753ae2518
commit ffb02cea15
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4 changed files with 51 additions and 0 deletions

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@ -1065,6 +1065,11 @@ int V3PreProcImp::getStateToken() {
// FALLTHRU, handle as with VP_SYMBOL_JOIN
}
}
if (state() == ps_STRIFY) {
// Ignore joins and symbol joins in stringify as they don't affect the final string
if (tok == VP_JOIN) goto next_tok;
if (tok == VP_SYMBOL_JOIN) tok = VP_SYMBOL;
}
if (tok == VP_SYMBOL_JOIN // not else if, can fallthru from above if()
|| tok == VP_DEFREF_JOIN || tok == VP_JOIN) {
// a`` -> string doesn't include the ``, so can just grab next and continue

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@ -0,0 +1,3 @@
"foo-bar-qux"
""foo-bar-qux""
""

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@ -0,0 +1,24 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('vlt')
stdout_filename = os.path.join(test.obj_dir, test.name + "__test.vpp")
test.compile(verilator_flags2=['-E -P'],
verilator_make_gmake=False,
make_top_shell=False,
make_main=False,
stdout_filename=stdout_filename)
test.files_identical(stdout_filename, test.golden_filename)
test.passes()

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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2025 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
`define FOO foo
`define BAR bar
`define QUX qux
`define STRIFY `"`FOO``-```BAR``-```QUX```"
`define NESTED_STRIFY `"`STRIFY```"
`define EMPTY
`define EMPTY_STRIFY `"`EMPTY```"
`STRIFY
`NESTED_STRIFY
`EMPTY_STRIFY