47 lines
957 B
Systemverilog
47 lines
957 B
Systemverilog
// DESCRIPTION: Verilator: --protect-lib example module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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// See also https://verilator.org/guide/latest/examples.html"
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module top (input clk);
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int cyc;
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logic reset_l;
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] x;
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verilated_secret secret (.a, .b, .x, .clk, .reset_l);
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always @(posedge clk) begin
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$display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);
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cyc <= cyc + 1;
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if (cyc == 0) begin
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reset_l <= 0;
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a <= 0;
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b <= 0;
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end
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else if (cyc == 1) begin
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reset_l <= 1;
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a <= 5;
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b <= 7;
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end
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else if (cyc == 2) begin
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a <= 6;
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b <= 2;
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end
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else if (cyc == 3) begin
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a <= 1;
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b <= 9;
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end
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else if (cyc > 4) begin
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$display("Done");
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$finish;
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end
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end
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endmodule
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