verilator/docs/gen/ex_PROCASSINIT_fixed.rst

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.. comment: generated by t_lint_procassinit_bad
.. code-block:: sv
:linenos:
:emphasize-lines: 5
logic flop2_out;
always @(posedge clk, negedge reset_l) begin
if (!reset_l) begin
flop2_out <= '1; // <--- Added reset init
end
else if (enable) begin
flop2_out <= ~in;
end
end