38 lines
888 B
Systemverilog
38 lines
888 B
Systemverilog
// DESCRIPTION: Verilator: --protect-lib example secret module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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// This module will be used as libsecret.a or libsecret.so without
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// exposing the source.
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module secret_impl
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(
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input [31:0] a,
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input [31:0] b,
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output logic [31:0] x,
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input clk,
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input reset_l);
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logic [31:0] accum_q;
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logic [31:0] secret_value;
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initial $display("[%0t] %m: initialized", $time);
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always @(posedge clk) begin
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if (!reset_l) begin
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accum_q <= 0;
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secret_value <= 9;
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end
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else begin
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accum_q <= accum_q + a;
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if (accum_q > 10)
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x <= b;
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else
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x <= a + b + secret_value;
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end
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end
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endmodule
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