34 lines
645 B
Systemverilog
34 lines
645 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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int x;
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int y;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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x <= 1;
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end
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else if (cyc == 1) begin
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y <= (x = 2);
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end else begin
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if (x != 2) $stop;
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if (y != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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